pinctrl: qcom: move out of mach-snapdragon

Move the Qualcomm pinctrl drivers out of mach-snapdragon and over to the
rest of the pinctrl drivers, adjust the drivers so that support for each
platform can be enabled/disabled individually and introduce platform
specific configuration options.

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>

10 files changed, 540 insertions, 0 deletions

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index fceafea..a1d53cf 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -355,6 +355,7 @@ source "drivers/pinctrl/mvebu/Kconfig"
 source "drivers/pinctrl/nexell/Kconfig"
 source "drivers/pinctrl/nuvoton/Kconfig"
 source "drivers/pinctrl/nxp/Kconfig"
+source "drivers/pinctrl/qcom/Kconfig"
 source "drivers/pinctrl/renesas/Kconfig"
 source "drivers/pinctrl/rockchip/Kconfig"
 source "drivers/pinctrl/sunxi/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 96a0516..0e929d8 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_ARCH_ATH79) += ath79/
 obj-$(CONFIG_PINCTRL_INTEL) += intel/
 obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
 obj-$(CONFIG_ARCH_NPCM)         += nuvoton/
+obj-$(CONFIG_PINCTRL_QCOM) += qcom/
 obj-$(CONFIG_ARCH_RMOBILE) += renesas/
 obj-$(CONFIG_ARCH_RZN1) += renesas/
 obj-$(CONFIG_PINCTRL_SANDBOX)	+= pinctrl-sandbox.o
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
new file mode 100644
index 0000000..412925c
--- /dev/null
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -0,0 +1,39 @@
+if ARCH_SNAPDRAGON
+
+config PINCTRL_QCOM
+	depends on PINCTRL_GENERIC
+	def_bool n
+
+menu "Qualcomm pinctrl drivers"
+
+config PINCTRL_QCOM_APQ8016
+	bool "Qualcomm APQ8016 GCC"
+	select PINCTRL_QCOM
+	help
+	  Say Y here to enable support for pinctrl on the MSM8916 / APQ8016
+	  Snapdragon 410 SoC, as well as the associated GPIO driver.
+
+config PINCTRL_QCOM_APQ8096
+	bool "Qualcomm APQ8096 GCC"
+	select PINCTRL_QCOM
+	help
+	  Say Y here to enable support for pinctrl on the MSM8996 / APQ8096
+	  Snapdragon 820 SoC, as well as the associated GPIO driver.
+
+config PINCTRL_QCOM_QCS404
+	bool "Qualcomm QCS404 GCC"
+	select PINCTRL_QCOM
+	help
+	  Say Y here to enable support for pinctrl on the Snapdragon QCS404 SoC,
+	  as well as the associated GPIO driver.
+
+config PINCTRL_QCOM_SDM845
+	bool "Qualcomm SDM845 GCC"
+	select PINCTRL_QCOM
+	help
+	  Say Y here to enable support for pinctrl on the Snapdragon 845 SoC,
+	  as well as the associated GPIO driver.
+
+endmenu
+
+endif
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
new file mode 100644
index 0000000..86f5074
--- /dev/null
+++ b/drivers/pinctrl/qcom/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2023 Linaro Ltd.
+
+obj-$(CONFIG_PINCTRL_QCOM) += pinctrl-qcom.o
+obj-$(CONFIG_PINCTRL_QCOM_APQ8016) += pinctrl-apq8016.o
+obj-$(CONFIG_PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o
+obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o
+obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c b/drivers/pinctrl/qcom/pinctrl-apq8016.c
new file mode 100644
index 0000000..bcbc0df
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm APQ8016 pinctrl
+ *
+ * (C) Copyright 2018 Ramon Fried <ramon.fried@gmail.com>
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+
+#include "pinctrl-qcom.h"
+
+#define MAX_PIN_NAME_LEN 32
+static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+static const char * const msm_pinctrl_pins[] = {
+	"SDC1_CLK",
+	"SDC1_CMD",
+	"SDC1_DATA",
+	"SDC2_CLK",
+	"SDC2_CMD",
+	"SDC2_DATA",
+	"QDSD_CLK",
+	"QDSD_CMD",
+	"QDSD_DATA0",
+	"QDSD_DATA1",
+	"QDSD_DATA2",
+	"QDSD_DATA3",
+};
+
+static const struct pinctrl_function msm_pinctrl_functions[] = {
+	{"blsp1_uart", 2},
+};
+
+static const char *apq8016_get_function_name(struct udevice *dev,
+					     unsigned int selector)
+{
+	return msm_pinctrl_functions[selector].name;
+}
+
+static const char *apq8016_get_pin_name(struct udevice *dev,
+					unsigned int selector)
+{
+	if (selector < 122) {
+		snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
+		return pin_name;
+	} else {
+		return msm_pinctrl_pins[selector - 122];
+	}
+}
+
+static unsigned int apq8016_get_function_mux(unsigned int selector)
+{
+	return msm_pinctrl_functions[selector].val;
+}
+
+static const struct msm_pinctrl_data apq8016_data = {
+	.pin_count = 133,
+	.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
+	.get_function_name = apq8016_get_function_name,
+	.get_function_mux = apq8016_get_function_mux,
+	.get_pin_name = apq8016_get_pin_name,
+};
+
+static const struct udevice_id msm_pinctrl_ids[] = {
+	{ .compatible = "qcom,msm8916-pinctrl", .data = (ulong)&apq8016_data },
+	{ /* Sentinal */ }
+};
+
+U_BOOT_DRIVER(pinctrl_apq8016) = {
+	.name		= "pinctrl_apq8016",
+	.id		= UCLASS_NOP,
+	.of_match	= msm_pinctrl_ids,
+	.ops		= &msm_pinctrl_ops,
+	.bind		= msm_pinctrl_bind,
+};
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8096.c b/drivers/pinctrl/qcom/pinctrl-apq8096.c
new file mode 100644
index 0000000..5250856
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-apq8096.c
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm APQ8096 pinctrl
+ *
+ * (C) Copyright 2019 Ramon Fried <ramon.fried@gmail.com>
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+
+#include "pinctrl-qcom.h"
+
+#define MAX_PIN_NAME_LEN 32
+static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+static const char * const msm_pinctrl_pins[] = {
+	"SDC1_CLK",
+	"SDC1_CMD",
+	"SDC1_DATA",
+	"SDC2_CLK",
+	"SDC2_CMD",
+	"SDC2_DATA",
+	"SDC1_RCLK",
+};
+
+static const struct pinctrl_function msm_pinctrl_functions[] = {
+	{"blsp_uart8", 2},
+};
+
+static const char *apq8096_get_function_name(struct udevice *dev,
+					     unsigned int selector)
+{
+	return msm_pinctrl_functions[selector].name;
+}
+
+static const char *apq8096_get_pin_name(struct udevice *dev,
+					unsigned int selector)
+{
+	if (selector < 150) {
+		snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
+		return pin_name;
+	} else {
+		return msm_pinctrl_pins[selector - 150];
+	}
+}
+
+static unsigned int apq8096_get_function_mux(unsigned int selector)
+{
+	return msm_pinctrl_functions[selector].val;
+}
+
+static const struct msm_pinctrl_data apq8096_data = {
+	.pin_count = 157,
+	.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
+	.get_function_name = apq8096_get_function_name,
+	.get_function_mux = apq8096_get_function_mux,
+	.get_pin_name = apq8096_get_pin_name,
+};
+
+static const struct udevice_id msm_pinctrl_ids[] = {
+	{ .compatible = "qcom,msm8996-pinctrl", .data = (ulong)&apq8096_data },
+	{ /* Sentinal */ }
+};
+
+U_BOOT_DRIVER(pinctrl_apq8096) = {
+	.name		= "pinctrl_apq8096",
+	.id		= UCLASS_NOP,
+	.of_match	= msm_pinctrl_ids,
+	.ops		= &msm_pinctrl_ops,
+	.bind		= msm_pinctrl_bind,
+};
diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.c b/drivers/pinctrl/qcom/pinctrl-qcom.c
new file mode 100644
index 0000000..1cface7
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-qcom.c
@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * TLMM driver for Qualcomm APQ8016, APQ8096
+ *
+ * (C) Copyright 2018 Ramon Fried <ramon.fried@gmail.com>
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <dm/device_compat.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/pinctrl.h>
+#include <linux/bitops.h>
+#include "pinctrl-qcom.h"
+
+struct msm_pinctrl_priv {
+	phys_addr_t base;
+	struct msm_pinctrl_data *data;
+};
+
+#define GPIO_CONFIG_OFFSET(x)         ((x) * 0x1000)
+#define TLMM_GPIO_PULL_MASK GENMASK(1, 0)
+#define TLMM_FUNC_SEL_MASK GENMASK(5, 2)
+#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6)
+#define TLMM_GPIO_DISABLE BIT(9)
+
+static const struct pinconf_param msm_conf_params[] = {
+	{ "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 2 },
+	{ "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
+	{ "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 3 },
+};
+
+static int msm_get_functions_count(struct udevice *dev)
+{
+	struct msm_pinctrl_priv *priv = dev_get_priv(dev);
+
+	return priv->data->functions_count;
+}
+
+static int msm_get_pins_count(struct udevice *dev)
+{
+	struct msm_pinctrl_priv *priv = dev_get_priv(dev);
+
+	return priv->data->pin_count;
+}
+
+static const char *msm_get_function_name(struct udevice *dev,
+					 unsigned int selector)
+{
+	struct msm_pinctrl_priv *priv = dev_get_priv(dev);
+
+	return priv->data->get_function_name(dev, selector);
+}
+
+static int msm_pinctrl_probe(struct udevice *dev)
+{
+	struct msm_pinctrl_priv *priv = dev_get_priv(dev);
+
+	priv->base = dev_read_addr(dev);
+	priv->data = (struct msm_pinctrl_data *)dev->driver_data;
+
+	return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0;
+}
+
+static const char *msm_get_pin_name(struct udevice *dev, unsigned int selector)
+{
+	struct msm_pinctrl_priv *priv = dev_get_priv(dev);
+
+	return priv->data->get_pin_name(dev, selector);
+}
+
+static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector,
+			  unsigned int func_selector)
+{
+	struct msm_pinctrl_priv *priv = dev_get_priv(dev);
+
+	clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
+			TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE,
+			priv->data->get_function_mux(func_selector) << 2);
+	return 0;
+}
+
+static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector,
+			   unsigned int param, unsigned int argument)
+{
+	struct msm_pinctrl_priv *priv = dev_get_priv(dev);
+
+	switch (param) {
+	case PIN_CONFIG_DRIVE_STRENGTH:
+		argument = (argument / 2) - 1;
+		clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
+				TLMM_DRV_STRENGTH_MASK, argument << 6);
+		break;
+	case PIN_CONFIG_BIAS_DISABLE:
+		clrbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
+			     TLMM_GPIO_PULL_MASK);
+		break;
+	case PIN_CONFIG_BIAS_PULL_UP:
+		clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
+				TLMM_GPIO_PULL_MASK, argument);
+		break;
+	default:
+		return 0;
+	}
+
+	return 0;
+}
+
+struct pinctrl_ops msm_pinctrl_ops = {
+	.get_pins_count = msm_get_pins_count,
+	.get_pin_name = msm_get_pin_name,
+	.set_state = pinctrl_generic_set_state,
+	.pinmux_set = msm_pinmux_set,
+	.pinconf_num_params = ARRAY_SIZE(msm_conf_params),
+	.pinconf_params = msm_conf_params,
+	.pinconf_set = msm_pinconf_set,
+	.get_functions_count = msm_get_functions_count,
+	.get_function_name = msm_get_function_name,
+};
+
+int msm_pinctrl_bind(struct udevice *dev)
+{
+	ofnode node = dev_ofnode(dev);
+	struct msm_pinctrl_data *data = (struct msm_pinctrl_data *)dev_get_driver_data(dev);
+	struct driver *drv;
+	struct udevice *pinctrl_dev;
+	const char *name;
+	int ret;
+
+	drv = lists_driver_lookup_name("pinctrl_qcom");
+	if (!drv)
+		return -ENOENT;
+
+	ret = device_bind_with_driver_data(dev_get_parent(dev), drv, ofnode_get_name(node), (ulong)data,
+					   dev_ofnode(dev), &pinctrl_dev);
+	if (ret)
+		return ret;
+
+	ofnode_get_property(node, "gpio-controller", &ret);
+	if (ret < 0)
+		return 0;
+
+	/* Get the name of gpio node */
+	name = ofnode_get_name(node);
+	if (!name)
+		return -EINVAL;
+
+	/* Bind gpio node */
+	ret = device_bind_driver_to_node(dev, "gpio_msm",
+					 name, node, NULL);
+	if (ret) {
+		device_unbind(pinctrl_dev);
+		return ret;
+	}
+
+	return 0;
+}
+
+U_BOOT_DRIVER(pinctrl_qcom) = {
+	.name		= "pinctrl_qcom",
+	.id		= UCLASS_PINCTRL,
+	.priv_auto	= sizeof(struct msm_pinctrl_priv),
+	.ops		= &msm_pinctrl_ops,
+	.probe		= msm_pinctrl_probe,
+};
diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.h b/drivers/pinctrl/qcom/pinctrl-qcom.h
new file mode 100644
index 0000000..1edd9a4
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-qcom.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Qualcomm Pin control
+ *
+ * (C) Copyright 2018 Ramon Fried <ramon.fried@gmail.com>
+ *
+ */
+#ifndef _PINCTRL_QCOM_H
+#define _PINCTRL_QCOM_H
+
+struct udevice;
+
+struct msm_pinctrl_data {
+	int pin_count;
+	int functions_count;
+	const char *(*get_function_name)(struct udevice *dev,
+					 unsigned int selector);
+	unsigned int (*get_function_mux)(unsigned int selector);
+	const char *(*get_pin_name)(struct udevice *dev,
+				    unsigned int selector);
+};
+
+struct pinctrl_function {
+	const char *name;
+	int val;
+};
+
+extern struct pinctrl_ops msm_pinctrl_ops;
+
+int msm_pinctrl_bind(struct udevice *dev);
+
+#endif
diff --git a/drivers/pinctrl/qcom/pinctrl-qcs404.c b/drivers/pinctrl/qcom/pinctrl-qcs404.c
new file mode 100644
index 0000000..272331c
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-qcs404.c
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm QCS404 pinctrl
+ *
+ * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+
+#include "pinctrl-qcom.h"
+
+#define MAX_PIN_NAME_LEN 32
+static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+static const char * const msm_pinctrl_pins[] = {
+	"SDC1_RCLK",
+	"SDC1_CLK",
+	"SDC1_CMD",
+	"SDC1_DATA",
+	"SDC2_CLK",
+	"SDC2_CMD",
+	"SDC2_DATA",
+};
+
+static const struct pinctrl_function msm_pinctrl_functions[] = {
+	{"blsp_uart2", 1},
+	{"rgmii_int", 1},
+	{"rgmii_ck", 1},
+	{"rgmii_tx", 1},
+	{"rgmii_ctl", 1},
+	{"rgmii_rx", 1},
+	{"rgmii_mdio", 1},
+	{"rgmii_mdc", 1},
+	{"blsp_i2c0", 3},
+	{"blsp_i2c1", 2},
+	{"blsp_i2c_sda_a2", 3},
+	{"blsp_i2c_scl_a2", 3},
+	{"blsp_i2c3", 2},
+	{"blsp_i2c4", 1},
+};
+
+static const char *qcs404_get_function_name(struct udevice *dev,
+					    unsigned int selector)
+{
+	return msm_pinctrl_functions[selector].name;
+}
+
+static const char *qcs404_get_pin_name(struct udevice *dev,
+				       unsigned int selector)
+{
+	if (selector < 120) {
+		snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
+		return pin_name;
+	} else {
+		return msm_pinctrl_pins[selector - 120];
+	}
+}
+
+static unsigned int qcs404_get_function_mux(unsigned int selector)
+{
+	return msm_pinctrl_functions[selector].val;
+}
+
+static struct msm_pinctrl_data qcs404_data = {
+	.pin_count = 126,
+	.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
+	.get_function_name = qcs404_get_function_name,
+	.get_function_mux = qcs404_get_function_mux,
+	.get_pin_name = qcs404_get_pin_name,
+};
+
+static const struct udevice_id msm_pinctrl_ids[] = {
+	{ .compatible = "qcom,qcs404-pinctrl", .data = (ulong)&qcs404_data },
+	{ /* Sentinal */ }
+};
+
+U_BOOT_DRIVER(pinctrl_qcs404) = {
+	.name		= "pinctrl_qcs404",
+	.id		= UCLASS_NOP,
+	.of_match	= msm_pinctrl_ids,
+	.ops		= &msm_pinctrl_ops,
+	.bind		= msm_pinctrl_bind,
+};
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c
new file mode 100644
index 0000000..1a09c5c
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm SDM845 pinctrl
+ *
+ * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+
+#include "pinctrl-qcom.h"
+
+#define MAX_PIN_NAME_LEN 32
+static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+
+static const struct pinctrl_function msm_pinctrl_functions[] = {
+	{"qup9", 1},
+	{"gpio", 0},
+};
+
+static const char *sdm845_get_function_name(struct udevice *dev,
+					     unsigned int selector)
+{
+	return msm_pinctrl_functions[selector].name;
+}
+
+static const char *sdm845_get_pin_name(struct udevice *dev,
+					unsigned int selector)
+{
+	snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
+	return pin_name;
+}
+
+static unsigned int sdm845_get_function_mux(unsigned int selector)
+{
+	return msm_pinctrl_functions[selector].val;
+}
+
+static struct msm_pinctrl_data sdm845_data = {
+	.pin_count = 150,
+	.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
+	.get_function_name = sdm845_get_function_name,
+	.get_function_mux = sdm845_get_function_mux,
+	.get_pin_name = sdm845_get_pin_name,
+};
+
+static const struct udevice_id msm_pinctrl_ids[] = {
+	{ .compatible = "qcom,sdm845-pinctrl", .data = (ulong)&sdm845_data },
+	{ /* Sentinal */ }
+};
+
+U_BOOT_DRIVER(pinctrl_sdm845) = {
+	.name		= "pinctrl_sdm845",
+	.id		= UCLASS_NOP,
+	.of_match	= msm_pinctrl_ids,
+	.ops		= &msm_pinctrl_ops,
+	.bind		= msm_pinctrl_bind,
+};