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authorMurali Karicheri <m-karicheri2@ti.com>2020-04-17 11:12:09 -0400
committerLokesh Vutla <lokeshvutla@ti.com>2020-05-09 19:58:58 +0530
commit39821d58c91d97b48a36ea340adedc4c9b8f5b85 (patch)
tree7ce7d0ec0edde6b6269ae941b4cdce4914b4664f /drivers
parent552f19f8fe069500c024bbe44e25e1ed9535d27c (diff)
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net: ethernet: ti: am65-cpsw-nuss: enable 10Mbps link speed in rgmii mode
In RGMII mode the 10Mbps link speed is supported only when CPSW2G MAC SL is configured for External Control ("in band") mode CPSW_PN_MAC_CONTROL_REG.CTL_EN(18) = 1 Hence update am65_cpsw_update_link() to follow documentation. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/ti/am65-cpsw-nuss.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c
index 2b77213..7531a07 100644
--- a/drivers/net/ti/am65-cpsw-nuss.c
+++ b/drivers/net/ti/am65-cpsw-nuss.c
@@ -61,6 +61,7 @@
#define AM65_CPSW_MACSL_CTL_REG 0x0
#define AM65_CPSW_MACSL_CTL_REG_IFCTL_A BIT(15)
+#define AM65_CPSW_MACSL_CTL_EXT_EN BIT(18)
#define AM65_CPSW_MACSL_CTL_REG_GIG BIT(7)
#define AM65_CPSW_MACSL_CTL_REG_GMII_EN BIT(5)
#define AM65_CPSW_MACSL_CTL_REG_LOOPBACK BIT(1)
@@ -187,6 +188,9 @@ static int am65_cpsw_update_link(struct am65_cpsw_priv *priv)
AM65_CPSW_MACSL_CTL_REG_GMII_EN;
if (phy->speed == 1000)
mac_control |= AM65_CPSW_MACSL_CTL_REG_GIG;
+ if (phy->speed == 10 && phy_interface_is_rgmii(phy))
+ /* Can be used with in band mode only */
+ mac_control |= AM65_CPSW_MACSL_CTL_EXT_EN;
if (phy->duplex == DUPLEX_FULL)
mac_control |= AM65_CPSW_MACSL_CTL_REG_FULL_DUPLEX;
if (phy->speed == 100)