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| author | Gabriel Fernandez <gabriel.fernandez@foss.st.com> | 2022-02-01 14:02:14 +0100 |
|---|---|---|
| committer | Patrice Chotard <patrice.chotard@foss.st.com> | 2022-03-15 09:11:11 +0100 |
| commit | 310ef93028014914efd9c5a210443b378670f5e3 (patch) | |
| tree | 85dc9df7b0c6f60f98f31298e8c40d60e85e3236 /drivers/video/stm32/stm32_ltdc.c | |
| parent | 6ed21f3d704370d5b1a5db8ee953fd7c5cea08d6 (diff) | |
| download | u-boot-310ef93028014914efd9c5a210443b378670f5e3.zip u-boot-310ef93028014914efd9c5a210443b378670f5e3.tar.gz u-boot-310ef93028014914efd9c5a210443b378670f5e3.tar.bz2 | |
video: stm32: stm32_ltdc: fix the check of return value of clk_set_rate()
The clk_set_rate() function returns rate as an 'ulong' not
an 'int' and rate > 0 by default.
This patch avoids to display the associated warning when
the set rate function returns the new frequency.
Fixes: aeaf330649e8 ("video: stm32: stm32_ltdc: add bridge to display controller")
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Diffstat (limited to 'drivers/video/stm32/stm32_ltdc.c')
| -rw-r--r-- | drivers/video/stm32/stm32_ltdc.c | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c index 87e5fd5..e741e74 100644 --- a/drivers/video/stm32/stm32_ltdc.c +++ b/drivers/video/stm32/stm32_ltdc.c @@ -338,6 +338,7 @@ static int stm32_ltdc_probe(struct udevice *dev) struct display_timing timings; struct clk pclk; struct reset_ctl rst; + ulong rate; int ret; priv->regs = (void *)dev_read_addr(dev); @@ -375,13 +376,13 @@ static int stm32_ltdc_probe(struct udevice *dev) } } - ret = clk_set_rate(&pclk, timings.pixelclock.typ); - if (ret) - dev_warn(dev, "fail to set pixel clock %d hz\n", - timings.pixelclock.typ); + rate = clk_set_rate(&pclk, timings.pixelclock.typ); + if (IS_ERR_VALUE(rate)) + dev_warn(dev, "fail to set pixel clock %d hz, ret=%ld\n", + timings.pixelclock.typ, rate); dev_dbg(dev, "Set pixel clock req %d hz get %ld hz\n", - timings.pixelclock.typ, clk_get_rate(&pclk)); + timings.pixelclock.typ, rate); ret = reset_get_by_index(dev, 0, &rst); if (ret) { |