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author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2020-07-10 01:12:08 +0900 |
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committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2020-07-11 21:30:21 +0900 |
commit | b053515e91258ece015a26b06f812ca5dca37e5a (patch) | |
tree | 8f13ea25a3a8f2afc72a354a6539d8c85f1cd8a2 /drivers/serial/serial_uniphier.c | |
parent | 26f7a7deab33e9fb46abec50a5209878fc3b53dc (diff) | |
download | u-boot-b053515e91258ece015a26b06f812ca5dca37e5a.zip u-boot-b053515e91258ece015a26b06f812ca5dca37e5a.tar.gz u-boot-b053515e91258ece015a26b06f812ca5dca37e5a.tar.bz2 |
serial: uniphier: enable FIFO
This UART controller is integrated with a FIFO. Enable it.
You can put the next character into the FIFO while the transmitter
is sending out the current character. This works slightly faster.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'drivers/serial/serial_uniphier.c')
-rw-r--r-- | drivers/serial/serial_uniphier.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/serial/serial_uniphier.c b/drivers/serial/serial_uniphier.c index aaf8657..ad691b6 100644 --- a/drivers/serial/serial_uniphier.c +++ b/drivers/serial/serial_uniphier.c @@ -23,6 +23,7 @@ #define UNIPHIER_UART_TX UNIPHIER_UART_RX /* bit[15:8] = CHAR, bit[7:0] = FCR */ #define UNIPHIER_UART_CHAR_FCR (3 << (UNIPHIER_UART_REGSHIFT)) +#define UNIPHIER_UART_FCR_MASK GENMASK(7, 0) /* bit[15:8] = LCR, bit[7:0] = MCR */ #define UNIPHIER_UART_LCR_MCR (4 << (UNIPHIER_UART_REGSHIFT)) #define UNIPHIER_UART_LCR_MASK GENMASK(15, 8) @@ -140,6 +141,12 @@ static int uniphier_serial_probe(struct udevice *dev) while (!(readl(priv->membase + UNIPHIER_UART_LSR) & UART_LSR_TEMT)) ; + /* enable FIFO */ + tmp = readl(priv->membase + UNIPHIER_UART_CHAR_FCR); + tmp &= ~UNIPHIER_UART_FCR_MASK; + tmp |= FIELD_PREP(UNIPHIER_UART_FCR_MASK, UART_FCR_ENABLE_FIFO); + writel(tmp, priv->membase + UNIPHIER_UART_CHAR_FCR); + tmp = readl(priv->membase + UNIPHIER_UART_LCR_MCR); tmp &= ~UNIPHIER_UART_LCR_MASK; tmp |= FIELD_PREP(UNIPHIER_UART_LCR_MASK, UART_LCR_WLEN8); |