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| author | Kever Yang <kever.yang@rock-chips.com> | 2017-04-20 16:15:34 +0800 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2017-05-10 13:37:21 -0600 |
| commit | 602778d3c7ea367bb55f73ec33e8ef8c2c1dcb12 (patch) | |
| tree | d444c69ef398e6005b9c10034ecc20177bc96391 /drivers/pinctrl/rockchip/pinctrl_rk3399.c | |
| parent | fd9884e292c8fb981bf25cf5aefaa1b685bda21e (diff) | |
| download | u-boot-602778d3c7ea367bb55f73ec33e8ef8c2c1dcb12.zip u-boot-602778d3c7ea367bb55f73ec33e8ef8c2c1dcb12.tar.gz u-boot-602778d3c7ea367bb55f73ec33e8ef8c2c1dcb12.tar.bz2 | |
rockchip: pinctrl: rk3399: add gmac io strength support
GMAC controller need to init the tx io driver strength to 13mA,
just like the description in dts pinctrl node, or else the controller
may only work in 100MHz Mode, and fail to work at 1000MHz mode.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com <mailto:philipp.tomsich@theobroma-systems.com>>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers/pinctrl/rockchip/pinctrl_rk3399.c')
| -rw-r--r-- | drivers/pinctrl/rockchip/pinctrl_rk3399.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3399.c b/drivers/pinctrl/rockchip/pinctrl_rk3399.c index 6eb657f..c09cd82 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3399.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3399.c @@ -244,6 +244,24 @@ static void pinctrl_rk3399_gmac_config(struct rk3399_grf_regs *grf, int mmc_id) rk_clrsetreg(&grf->gpio3c_iomux, GRF_GPIO3C1_SEL_MASK, GRF_MAC_TXCLK << GRF_GPIO3C1_SEL_SHIFT); + + /* Set drive strength for GMAC tx io, value 3 means 13mA */ + rk_clrsetreg(&grf->gpio3_e[0], + GRF_GPIO3A0_E_MASK | GRF_GPIO3A1_E_MASK | + GRF_GPIO3A4_E_MASK | GRF_GPIO3A5_E0_MASK, + 3 << GRF_GPIO3A0_E_SHIFT | + 3 << GRF_GPIO3A1_E_SHIFT | + 3 << GRF_GPIO3A4_E_SHIFT | + 1 << GRF_GPIO3A5_E0_SHIFT); + rk_clrsetreg(&grf->gpio3_e[1], + GRF_GPIO3A5_E12_MASK, + 1 << GRF_GPIO3A5_E12_SHIFT); + rk_clrsetreg(&grf->gpio3_e[2], + GRF_GPIO3B4_E_MASK, + 3 << GRF_GPIO3B4_E_SHIFT); + rk_clrsetreg(&grf->gpio3_e[4], + GRF_GPIO3C1_E_MASK, + 3 << GRF_GPIO3C1_E_SHIFT); } #endif |