Merge tag 'v2021.07-rc5' into next

Prepare v2021.07-rc5

# gpg: Signature made Mon 28 Jun 2021 03:39:36 PM EDT
# gpg:                using RSA key 1A3C7F70E08FAB1707809BBF147C39FF9634B72C
# gpg: Good signature from "Thomas Rini <trini@konsulko.com>" [ultimate]

# Conflicts:
#	configs/am64x_evm_r5_defconfig

12 files changed, 1237 insertions, 35 deletions

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 3826390..9fc28b1 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -673,6 +673,14 @@ config SNI_AVE
 	  This driver implements support for the Socionext AVE Ethernet
 	  controller, as found on the Socionext UniPhier family.
 
+config SNI_NETSEC
+	bool "Socionext NETSEC Ethernet support"
+	depends on DM_ETH && SYNQUACER_SPI
+	select PHYLIB
+	help
+	  This driver implements support for the Socionext SynQuacer NETSEC
+	  ethernet controller, as found on the Socionext SynQuacer family.
+
 source "drivers/net/mscc_eswitch/Kconfig"
 
 config ETHER_ON_FEC1
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index a44a7d3..d56baa6 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -89,6 +89,7 @@ obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
 obj-$(CONFIG_FSL_PFE) += pfe_eth/
 obj-y += qe/
 obj-$(CONFIG_SNI_AVE) += sni_ave.o
+obj-$(CONFIG_SNI_NETSEC) += sni_netsec.o
 obj-y += ti/
 obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o
 obj-y += mscc_eswitch/
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index e8242ca..b012bed 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -172,8 +172,6 @@ struct eqos_mtl_regs {
 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK		0x3f
 #define EQOS_MTL_RXQ0_OPERATION_MODE_EHFC		BIT(7)
 #define EQOS_MTL_RXQ0_OPERATION_MODE_RSF		BIT(5)
-#define EQOS_MTL_RXQ0_OPERATION_MODE_FEP		BIT(4)
-#define EQOS_MTL_RXQ0_OPERATION_MODE_FUP		BIT(3)
 
 #define EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT			16
 #define EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK			0x7fff
@@ -321,6 +319,7 @@ struct eqos_priv {
 	void *rx_pkt;
 	bool started;
 	bool reg_access_ok;
+	bool clk_ck_enabled;
 };
 
 /*
@@ -591,12 +590,13 @@ static int eqos_start_clks_stm32(struct udevice *dev)
 		goto err_disable_clk_rx;
 	}
 
-	if (clk_valid(&eqos->clk_ck)) {
+	if (clk_valid(&eqos->clk_ck) && !eqos->clk_ck_enabled) {
 		ret = clk_enable(&eqos->clk_ck);
 		if (ret < 0) {
 			pr_err("clk_enable(clk_ck) failed: %d", ret);
 			goto err_disable_clk_tx;
 		}
+		eqos->clk_ck_enabled = true;
 	}
 #endif
 
@@ -648,8 +648,6 @@ static void eqos_stop_clks_stm32(struct udevice *dev)
 	clk_disable(&eqos->clk_tx);
 	clk_disable(&eqos->clk_rx);
 	clk_disable(&eqos->clk_master_bus);
-	if (clk_valid(&eqos->clk_ck))
-		clk_disable(&eqos->clk_ck);
 #endif
 
 	debug("%s: OK\n", __func__);
@@ -1222,7 +1220,6 @@ static int eqos_start(struct udevice *dev)
 	}
 
 	/* Configure MTL */
-	writel(0x60, &eqos->mtl_regs->txq0_quantum_weight - 0x100);
 
 	/* Enable Store and Forward mode for TX */
 	/* Program Tx operating mode */
@@ -1236,9 +1233,7 @@ static int eqos_start(struct udevice *dev)
 
 	/* Enable Store and Forward mode for RX, since no jumbo frame */
 	setbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
-		     EQOS_MTL_RXQ0_OPERATION_MODE_RSF |
-		     EQOS_MTL_RXQ0_OPERATION_MODE_FEP |
-		     EQOS_MTL_RXQ0_OPERATION_MODE_FUP);
+		     EQOS_MTL_RXQ0_OPERATION_MODE_RSF);
 
 	/* Transmit/Receive queue fifo size; use all RAM for 1 queue */
 	val = readl(&eqos->mac_regs->hw_feature1);
@@ -1314,12 +1309,6 @@ static int eqos_start(struct udevice *dev)
 			eqos->config->config_mac <<
 			EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT);
 
-	clrsetbits_le32(&eqos->mac_regs->rxq_ctrl0,
-			EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK <<
-			EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT,
-			0x2 <<
-			EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT);
-
 	/* Multicast and Broadcast Queue Enable */
 	setbits_le32(&eqos->mac_regs->unused_0a4,
 		     0x00100000);
diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index 694114e..60613b7 100644
--- a/drivers/net/e1000.c
+++ b/drivers/net/e1000.c
@@ -5673,6 +5673,10 @@ static int e1000_write_hwaddr(struct eth_device *dev)
 
 	DEBUGOUT("%s: mac=%pM\n", __func__, mac);
 
+	if ((hw->eeprom.type == e1000_eeprom_invm) &&
+	    !(E1000_READ_REG(hw, EECD) & E1000_EECD_FLASH_DETECTED_I210))
+		return -ENOSYS;
+
 	memset(current_mac, 0, 6);
 
 	/* Read from EEPROM, not from registers, to make sure
diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h
index 072851b..082154a 100644
--- a/drivers/net/e1000.h
+++ b/drivers/net/e1000.h
@@ -1245,6 +1245,7 @@ struct e1000_hw {
 #define E1000_EECD_FLUPD     0x00080000 /* Update FLASH */
 #define E1000_EECD_FLUPD_I210       0x00800000 /* Update FLASH */
 #define E1000_EECD_FLUDONE_I210     0x04000000 /* Update FLASH done*/
+#define E1000_EECD_FLASH_DETECTED_I210	0x00080000 /* FLASH detected */
 #define E1000_FLUDONE_ATTEMPTS      20000
 #define E1000_EECD_AUPDEN    0x00100000 /* Enable Autonomous FLASH update */
 #define E1000_EECD_SHADV     0x00200000 /* Shadow RAM Data Valid */
diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index 0e89e66..7c23ccc 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -288,8 +288,10 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
 
 	/* alloc Rx buffer from main memory */
 	rx_buf_pool = malloc(MAX_RXBUF_LEN * RX_BD_RING_SIZE);
-	if (!rx_buf_pool)
+	if (!rx_buf_pool) {
+		free(rx_bd_ring_base);
 		return -ENOMEM;
+	}
 
 	memset(rx_buf_pool, 0, MAX_RXBUF_LEN * RX_BD_RING_SIZE);
 	debug("%s: rx_buf_pool = %p\n", __func__, rx_buf_pool);
diff --git a/drivers/net/octeontx/smi.c b/drivers/net/octeontx/smi.c
index 27f4423..d70fa82 100644
--- a/drivers/net/octeontx/smi.c
+++ b/drivers/net/octeontx/smi.c
@@ -314,10 +314,12 @@ read_error:
 
 int octeontx_smi_probe(struct udevice *dev)
 {
-	int ret, subnode, cnt = 0, node = dev_ofnode(dev).of_offset;
-	struct mii_dev *bus;
-	struct octeontx_smi_priv *priv;
 	pci_dev_t bdf = dm_pci_get_bdf(dev);
+	struct octeontx_smi_priv *priv;
+	struct mii_dev *bus;
+	int ret, cnt = 0;
+	ofnode subnode;
+	u64 baseaddr;
 
 	debug("SMI PCI device: %x\n", bdf);
 	if (!dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM)) {
@@ -325,14 +327,12 @@ int octeontx_smi_probe(struct udevice *dev)
 		return -1;
 	}
 
-	node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
-					     "cavium,thunder-8890-mdio-nexus");
-	fdt_for_each_subnode(subnode, gd->fdt_blob, node) {
-		ret = fdt_node_check_compatible(gd->fdt_blob, subnode,
-						"cavium,thunder-8890-mdio");
-		if (ret)
+	dev_for_each_subnode(subnode, dev) {
+		if (!ofnode_device_is_compatible(subnode,
+						 "cavium,thunder-8890-mdio"))
+			continue;
+		if (ofnode_read_u64(subnode, "reg", &baseaddr))
 			continue;
-
 		bus = mdio_alloc();
 		priv = malloc(sizeof(*priv));
 		if (!bus || !priv) {
@@ -347,9 +347,7 @@ int octeontx_smi_probe(struct udevice *dev)
 		bus->priv = priv;
 
 		priv->mode = CLAUSE22;
-		priv->baseaddr = (void __iomem *)fdtdec_get_addr(gd->fdt_blob,
-								 subnode,
-								 "reg");
+		priv->baseaddr = (void __iomem *)baseaddr;
 		debug("mdio base addr %p\n", priv->baseaddr);
 
 		/* use given name or generate its own unique name */
diff --git a/drivers/net/pfe_eth/pfe_cmd.c b/drivers/net/pfe_eth/pfe_cmd.c
index 1e69525..364750f 100644
--- a/drivers/net/pfe_eth/pfe_cmd.c
+++ b/drivers/net/pfe_eth/pfe_cmd.c
@@ -418,7 +418,7 @@ static void send_dummy_pkt_to_hif(void)
 	writel(buf, TMU_PHY_INQ_PKTINFO);
 }
 
-static void pfe_command_stop(int argc, char *const argv[])
+void pfe_command_stop(int argc, char *const argv[])
 {
 	int pfe_pe_id, hif_stop_loop = 10;
 	u32 rx_status;
diff --git a/drivers/net/pfe_eth/pfe_firmware.c b/drivers/net/pfe_eth/pfe_firmware.c
index eee70a2..ac86e33 100644
--- a/drivers/net/pfe_eth/pfe_firmware.c
+++ b/drivers/net/pfe_eth/pfe_firmware.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2015-2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
+ * Copyright 2017,2021 NXP
  */
 
 /*
@@ -262,7 +262,8 @@ int pfe_firmware_init(void)
 	uintptr_t pfe_img_addr = 0;
 #endif
 	int ret = 0;
-	int fw_count;
+	int fw_count, max_fw_count;
+	const char *p;
 
 	ret = pfe_spi_flash_init();
 	if (ret)
@@ -293,6 +294,61 @@ int pfe_firmware_init(void)
 	}
 #endif
 
+	p = env_get("load_util");
+	if (!p) {
+		max_fw_count = 2;
+	} else {
+		max_fw_count = simple_strtoul(p, NULL, 10);
+		if (max_fw_count)
+			max_fw_count = 3;
+		else
+			max_fw_count = 2;
+	}
+
+	for (fw_count = 0; fw_count < max_fw_count; fw_count++) {
+		switch (fw_count) {
+		case 0:
+			pfe_firmware_name = "class_slowpath";
+			break;
+		case 1:
+			pfe_firmware_name = "tmu_slowpath";
+			break;
+		case 2:
+			pfe_firmware_name = "util_slowpath";
+			break;
+		}
+
+		if (pfe_get_fw(&raw_image_addr, &raw_image_size,
+			       pfe_firmware_name)) {
+			printf("%s firmware couldn't be found in FIT image\n",
+			       pfe_firmware_name);
+			break;
+		}
+		pfe_firmware = malloc(raw_image_size);
+		if (!pfe_firmware)
+			return -ENOMEM;
+		memcpy((void *)pfe_firmware, (void *)raw_image_addr,
+		       raw_image_size);
+
+		switch (fw_count) {
+		case 0:
+			env_set_addr("class_elf_firmware", pfe_firmware);
+			env_set_addr("class_elf_size", (void *)raw_image_size);
+			break;
+		case 1:
+			env_set_addr("tmu_elf_firmware", pfe_firmware);
+			env_set_addr("tmu_elf_size", (void *)raw_image_size);
+			break;
+		case 2:
+			env_set_addr("util_elf_firmware", pfe_firmware);
+			env_set_addr("util_elf_size", (void *)raw_image_size);
+			break;
+		}
+	}
+
+	raw_image_addr = NULL;
+	pfe_firmware = NULL;
+	raw_image_size = 0;
 	for (fw_count = 0; fw_count < 2; fw_count++) {
 		if (fw_count == 0)
 			pfe_firmware_name = "class";
diff --git a/drivers/net/sni_netsec.c b/drivers/net/sni_netsec.c
new file mode 100644
index 0000000..a9ebf6a
--- /dev/null
+++ b/drivers/net/sni_netsec.c
@@ -0,0 +1,1134 @@
+// SPDX-License-Identifier: GPL-2.0+
+/**
+ * netsec.c - Socionext Synquacer Netsec driver
+ * Copyright 2021 Linaro Ltd.
+ */
+
+#include <clk.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <fdt_support.h>
+#include <log.h>
+#include <malloc.h>
+#include <miiphy.h>
+#include <net.h>
+#include <regmap.h>
+#include <reset.h>
+#include <syscon.h>
+#include <asm/cache.h>
+#include <asm/global_data.h>
+#include <dm/device_compat.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <spi.h>
+#include <spi_flash.h>
+
+#define NETSEC_REG_SOFT_RST			0x104
+#define NETSEC_REG_COM_INIT			0x120
+
+#define NETSEC_REG_TOP_STATUS			0x200
+#define NETSEC_IRQ_RX				BIT(1)
+#define NETSEC_IRQ_TX				BIT(0)
+
+#define NETSEC_REG_TOP_INTEN			0x204
+#define NETSEC_REG_INTEN_SET			0x234
+#define NETSEC_REG_INTEN_CLR			0x238
+
+#define NETSEC_REG_NRM_TX_STATUS		0x400
+#define NETSEC_REG_NRM_TX_INTEN			0x404
+#define NETSEC_REG_NRM_TX_INTEN_SET		0x428
+#define NETSEC_REG_NRM_TX_INTEN_CLR		0x42c
+#define NRM_TX_ST_NTOWNR	BIT(17)
+#define NRM_TX_ST_TR_ERR	BIT(16)
+#define NRM_TX_ST_TXDONE	BIT(15)
+#define NRM_TX_ST_TMREXP	BIT(14)
+
+#define NETSEC_REG_NRM_RX_STATUS		0x440
+#define NETSEC_REG_NRM_RX_INTEN			0x444
+#define NETSEC_REG_NRM_RX_INTEN_SET		0x468
+#define NETSEC_REG_NRM_RX_INTEN_CLR		0x46c
+#define NRM_RX_ST_RC_ERR	BIT(16)
+#define NRM_RX_ST_PKTCNT	BIT(15)
+#define NRM_RX_ST_TMREXP	BIT(14)
+
+#define NETSEC_REG_PKT_CMD_BUF			0xd0
+
+#define NETSEC_REG_CLK_EN			0x100
+
+#define NETSEC_REG_PKT_CTRL			0x140
+
+#define NETSEC_REG_DMA_TMR_CTRL			0x20c
+#define NETSEC_REG_F_TAIKI_MC_VER		0x22c
+#define NETSEC_REG_F_TAIKI_VER			0x230
+#define NETSEC_REG_DMA_HM_CTRL			0x214
+#define NETSEC_REG_DMA_MH_CTRL			0x220
+#define NETSEC_REG_ADDR_DIS_CORE		0x218
+#define NETSEC_REG_DMAC_HM_CMD_BUF		0x210
+#define NETSEC_REG_DMAC_MH_CMD_BUF		0x21c
+
+#define NETSEC_REG_NRM_TX_PKTCNT		0x410
+
+#define NETSEC_REG_NRM_TX_DONE_PKTCNT		0x414
+#define NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT	0x418
+
+#define NETSEC_REG_NRM_TX_TMR			0x41c
+
+#define NETSEC_REG_NRM_RX_PKTCNT		0x454
+#define NETSEC_REG_NRM_RX_RXINT_PKTCNT		0x458
+#define NETSEC_REG_NRM_TX_TXINT_TMR		0x420
+#define NETSEC_REG_NRM_RX_RXINT_TMR		0x460
+
+#define NETSEC_REG_NRM_RX_TMR			0x45c
+
+#define NETSEC_REG_NRM_TX_DESC_START_UP		0x434
+#define NETSEC_REG_NRM_TX_DESC_START_LW		0x408
+#define NETSEC_REG_NRM_RX_DESC_START_UP		0x474
+#define NETSEC_REG_NRM_RX_DESC_START_LW		0x448
+
+#define NETSEC_REG_NRM_TX_CONFIG		0x430
+#define NETSEC_REG_NRM_RX_CONFIG		0x470
+
+#define MAC_REG_STATUS				0x1024
+#define MAC_REG_DATA				0x11c0
+#define MAC_REG_CMD				0x11c4
+#define MAC_REG_FLOW_TH				0x11cc
+#define MAC_REG_INTF_SEL			0x11d4
+#define MAC_REG_DESC_INIT			0x11fc
+#define MAC_REG_DESC_SOFT_RST			0x1204
+#define NETSEC_REG_MODE_TRANS_COMP_STATUS	0x500
+
+#define GMAC_REG_MCR				0x0000
+#define GMAC_REG_MFFR				0x0004
+#define GMAC_REG_GAR				0x0010
+#define GMAC_REG_GDR				0x0014
+#define GMAC_REG_FCR				0x0018
+#define GMAC_REG_BMR				0x1000
+#define GMAC_REG_RDLAR				0x100c
+#define GMAC_REG_TDLAR				0x1010
+#define GMAC_REG_OMR				0x1018
+
+#define MHZ(n)		((n) * 1000 * 1000)
+
+#define NETSEC_TX_SHIFT_OWN_FIELD		31
+#define NETSEC_TX_SHIFT_LD_FIELD		30
+#define NETSEC_TX_SHIFT_DRID_FIELD		24
+#define NETSEC_TX_SHIFT_PT_FIELD		21
+#define NETSEC_TX_SHIFT_TDRID_FIELD		16
+#define NETSEC_TX_SHIFT_CC_FIELD		15
+#define NETSEC_TX_SHIFT_FS_FIELD		9
+#define NETSEC_TX_LAST				8
+#define NETSEC_TX_SHIFT_CO			7
+#define NETSEC_TX_SHIFT_SO			6
+#define NETSEC_TX_SHIFT_TRS_FIELD		4
+
+#define NETSEC_RX_PKT_OWN_FIELD			31
+#define NETSEC_RX_PKT_LD_FIELD			30
+#define NETSEC_RX_PKT_SDRID_FIELD		24
+#define NETSEC_RX_PKT_FR_FIELD			23
+#define NETSEC_RX_PKT_ER_FIELD			21
+#define NETSEC_RX_PKT_ERR_FIELD			16
+#define NETSEC_RX_PKT_TDRID_FIELD		12
+#define NETSEC_RX_PKT_FS_FIELD			9
+#define NETSEC_RX_PKT_LS_FIELD			8
+#define NETSEC_RX_PKT_CO_FIELD			6
+
+#define NETSEC_RX_PKT_ERR_MASK			3
+
+#define NETSEC_MAX_TX_PKT_LEN			1518
+#define NETSEC_MAX_TX_JUMBO_PKT_LEN		9018
+
+#define NETSEC_RING_GMAC			15
+#define NETSEC_RING_MAX				2
+
+#define NETSEC_TCP_SEG_LEN_MAX			1460
+#define NETSEC_TCP_JUMBO_SEG_LEN_MAX		8960
+
+#define NETSEC_RX_CKSUM_NOTAVAIL		0
+#define NETSEC_RX_CKSUM_OK			1
+#define NETSEC_RX_CKSUM_NG			2
+
+#define NETSEC_TOP_IRQ_REG_ME_START			BIT(20)
+#define NETSEC_IRQ_TRANSITION_COMPLETE		BIT(4)
+
+#define NETSEC_MODE_TRANS_COMP_IRQ_N2T		BIT(20)
+#define NETSEC_MODE_TRANS_COMP_IRQ_T2N		BIT(19)
+
+#define NETSEC_INT_PKTCNT_MAX			2047
+
+#define NETSEC_FLOW_START_TH_MAX		95
+#define NETSEC_FLOW_STOP_TH_MAX			95
+#define NETSEC_FLOW_PAUSE_TIME_MIN		5
+
+#define NETSEC_CLK_EN_REG_DOM_ALL		0x3f
+
+#define NETSEC_PKT_CTRL_REG_MODE_NRM		BIT(28)
+#define NETSEC_PKT_CTRL_REG_EN_JUMBO		BIT(27)
+#define NETSEC_PKT_CTRL_REG_LOG_CHKSUM_ER	BIT(3)
+#define NETSEC_PKT_CTRL_REG_LOG_HD_INCOMPLETE	BIT(2)
+#define NETSEC_PKT_CTRL_REG_LOG_HD_ER		BIT(1)
+#define NETSEC_PKT_CTRL_REG_DRP_NO_MATCH	BIT(0)
+
+#define NETSEC_CLK_EN_REG_DOM_G			BIT(5)
+#define NETSEC_CLK_EN_REG_DOM_C			BIT(1)
+#define NETSEC_CLK_EN_REG_DOM_D			BIT(0)
+
+#define NETSEC_COM_INIT_REG_DB			BIT(2)
+#define NETSEC_COM_INIT_REG_CLS			BIT(1)
+#define NETSEC_COM_INIT_REG_ALL			(NETSEC_COM_INIT_REG_CLS | \
+						 NETSEC_COM_INIT_REG_DB)
+
+#define NETSEC_SOFT_RST_REG_RESET		0
+#define NETSEC_SOFT_RST_REG_RUN			BIT(31)
+
+#define NETSEC_DMA_CTRL_REG_STOP		1
+#define MH_CTRL__MODE_TRANS			BIT(20)
+
+#define NETSEC_GMAC_CMD_ST_READ			0
+#define NETSEC_GMAC_CMD_ST_WRITE		BIT(28)
+#define NETSEC_GMAC_CMD_ST_BUSY			BIT(31)
+
+#define NETSEC_GMAC_BMR_REG_COMMON		0x00412080
+#define NETSEC_GMAC_BMR_REG_RESET		0x00020181
+#define NETSEC_GMAC_BMR_REG_SWR			0x00000001
+
+#define NETSEC_GMAC_OMR_REG_ST			BIT(13)
+#define NETSEC_GMAC_OMR_REG_SR			BIT(1)
+
+#define NETSEC_GMAC_MCR_REG_IBN			BIT(30)
+#define NETSEC_GMAC_MCR_REG_CST			BIT(25)
+#define NETSEC_GMAC_MCR_REG_JE			BIT(20)
+#define NETSEC_MCR_PS				BIT(15)
+#define NETSEC_GMAC_MCR_REG_FES			BIT(14)
+#define NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON	0x0000280c
+#define NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON	0x0001a00c
+
+#define NETSEC_FCR_RFE				BIT(2)
+#define NETSEC_FCR_TFE				BIT(1)
+
+#define NETSEC_GMAC_GAR_REG_GW			BIT(1)
+#define NETSEC_GMAC_GAR_REG_GB			BIT(0)
+
+#define NETSEC_GMAC_GAR_REG_SHIFT_PA		11
+#define NETSEC_GMAC_GAR_REG_SHIFT_GR		6
+#define GMAC_REG_SHIFT_CR_GAR			2
+
+#define NETSEC_GMAC_GAR_REG_CR_25_35_MHZ	2
+#define NETSEC_GMAC_GAR_REG_CR_35_60_MHZ	3
+#define NETSEC_GMAC_GAR_REG_CR_60_100_MHZ	0
+#define NETSEC_GMAC_GAR_REG_CR_100_150_MHZ	1
+#define NETSEC_GMAC_GAR_REG_CR_150_250_MHZ	4
+#define NETSEC_GMAC_GAR_REG_CR_250_300_MHZ	5
+
+#define NETSEC_GMAC_RDLAR_REG_COMMON		0x18000
+#define NETSEC_GMAC_TDLAR_REG_COMMON		0x1c000
+
+#define NETSEC_REG_NETSEC_VER_F_TAIKI		0x50000
+
+#define NETSEC_REG_DESC_RING_CONFIG_CFG_UP	BIT(31)
+#define NETSEC_REG_DESC_RING_CONFIG_CH_RST	BIT(30)
+#define NETSEC_REG_DESC_TMR_MODE		4
+#define NETSEC_REG_DESC_ENDIAN			0
+
+#define NETSEC_MAC_DESC_SOFT_RST_SOFT_RST	1
+#define NETSEC_MAC_DESC_INIT_REG_INIT		1
+
+#define NETSEC_EEPROM_MAC_ADDRESS		0x00
+#define NETSEC_EEPROM_HM_ME_ADDRESS_H		0x08
+#define NETSEC_EEPROM_HM_ME_ADDRESS_L		0x0C
+#define NETSEC_EEPROM_HM_ME_SIZE		0x10
+#define NETSEC_EEPROM_MH_ME_ADDRESS_H		0x14
+#define NETSEC_EEPROM_MH_ME_ADDRESS_L		0x18
+#define NETSEC_EEPROM_MH_ME_SIZE		0x1C
+#define NETSEC_EEPROM_PKT_ME_ADDRESS		0x20
+#define NETSEC_EEPROM_PKT_ME_SIZE		0x24
+
+#define DESC_SZ	sizeof(struct netsec_de)
+
+#define NETSEC_F_NETSEC_VER_MAJOR_NUM(x)	((x) & 0xffff0000)
+
+#define EERPROM_MAP_OFFSET	0x8000000
+#define NOR_BLOCK	1024
+
+struct netsec_de { /* Netsec Descriptor layout */
+	u32 attr;
+	u32 data_buf_addr_up;
+	u32 data_buf_addr_lw;
+	u32 buf_len_info;
+};
+
+struct netsec_priv {
+	struct netsec_de rxde[PKTBUFSRX];
+	struct netsec_de txde[1];
+	u16 rxat;
+
+	phys_addr_t eeprom_base;
+	phys_addr_t ioaddr;
+
+	struct mii_dev *bus;
+	struct phy_device *phydev;
+	u32 phy_addr, freq;
+	int phy_mode;
+	int max_speed;
+};
+
+struct netsec_tx_pkt_ctrl {
+	u16 tcp_seg_len;
+	bool tcp_seg_offload_flag;
+	bool cksum_offload_flag;
+};
+
+struct netsec_rx_pkt_info {
+	int rx_cksum_result;
+	int err_code;
+	bool err_flag;
+};
+
+static void netsec_write_reg(struct netsec_priv *priv, u32 reg_addr, u32 val)
+{
+	writel(val, priv->ioaddr + reg_addr);
+}
+
+static u32 netsec_read_reg(struct netsec_priv *priv, u32 reg_addr)
+{
+	return readl(priv->ioaddr + reg_addr);
+}
+
+/************* MDIO BUS OPS FOLLOW *************/
+
+#define TIMEOUT_SPINS_MAC		1000
+#define TIMEOUT_SECONDARY_MS_MAC	100
+
+static u32 netsec_clk_type(u32 freq)
+{
+	if (freq < MHZ(35))
+		return NETSEC_GMAC_GAR_REG_CR_25_35_MHZ;
+	if (freq < MHZ(60))
+		return NETSEC_GMAC_GAR_REG_CR_35_60_MHZ;
+	if (freq < MHZ(100))
+		return NETSEC_GMAC_GAR_REG_CR_60_100_MHZ;
+	if (freq < MHZ(150))
+		return NETSEC_GMAC_GAR_REG_CR_100_150_MHZ;
+	if (freq < MHZ(250))
+		return NETSEC_GMAC_GAR_REG_CR_150_250_MHZ;
+
+	return NETSEC_GMAC_GAR_REG_CR_250_300_MHZ;
+}
+
+static int netsec_wait_while_busy(struct netsec_priv *priv, u32 addr, u32 mask)
+{
+	u32 timeout = TIMEOUT_SPINS_MAC;
+
+	while (--timeout && netsec_read_reg(priv, addr) & mask)
+		cpu_relax();
+	if (timeout)
+		return 0;
+
+	timeout = TIMEOUT_SECONDARY_MS_MAC;
+	while (--timeout && netsec_read_reg(priv, addr) & mask)
+		udelay(2000);
+
+	if (timeout)
+		return 0;
+
+	pr_err("%s: timeout\n", __func__);
+
+	return -ETIMEDOUT;
+}
+
+static int netsec_set_mac_reg(struct netsec_priv *priv, u32 addr, u32 value)
+{
+	netsec_write_reg(priv, MAC_REG_DATA, value);
+	netsec_write_reg(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_WRITE);
+	return netsec_wait_while_busy(priv,
+				      MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY);
+}
+
+static int netsec_get_mac_reg(struct netsec_priv *priv, u32 addr, u32 *read)
+{
+	int ret;
+
+	netsec_write_reg(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_READ);
+	ret = netsec_wait_while_busy(priv,
+				     MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY);
+	if (ret)
+		return ret;
+
+	*read = netsec_read_reg(priv, MAC_REG_DATA);
+
+	return 0;
+}
+
+static int netsec_mac_wait_while_busy(struct netsec_priv *priv,
+				      u32 addr, u32 mask)
+{
+	u32 timeout = TIMEOUT_SPINS_MAC;
+	u32 data;
+	int ret;
+
+	do {
+		ret = netsec_get_mac_reg(priv, addr, &data);
+		if (ret)
+			break;
+		udelay(1);
+	} while (--timeout && (data & mask));
+
+	if (timeout)
+		return 0;
+
+	timeout = TIMEOUT_SECONDARY_MS_MAC;
+	do {
+		udelay(2000);
+
+		ret = netsec_get_mac_reg(priv, addr, &data);
+		if (ret)
+			break;
+		cpu_relax();
+	} while (--timeout && (data & mask));
+
+	if (timeout && !ret)
+		return 0;
+
+	return -ETIMEDOUT;
+}
+
+static void netsec_cache_invalidate(uintptr_t vaddr, int len)
+{
+	invalidate_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN),
+				roundup(vaddr + len, ARCH_DMA_MINALIGN));
+}
+
+static void netsec_cache_flush(uintptr_t vaddr, int len)
+{
+	flush_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN),
+			   roundup(vaddr + len, ARCH_DMA_MINALIGN));
+}
+
+static void netsec_set_rx_de(struct netsec_priv *priv, u16 idx, void *addr)
+{
+	struct netsec_de *de = &priv->rxde[idx];
+	u32 attr = (1 << NETSEC_RX_PKT_OWN_FIELD) |
+		   (1 << NETSEC_RX_PKT_FS_FIELD) |
+		   (1 << NETSEC_RX_PKT_LS_FIELD);
+
+	if (idx == PKTBUFSRX - 1)
+		attr |= (1 << NETSEC_RX_PKT_LD_FIELD);
+
+	de->data_buf_addr_up = upper_32_bits((dma_addr_t)addr);
+	de->data_buf_addr_lw = lower_32_bits((dma_addr_t)addr);
+	de->buf_len_info = PKTSIZE;
+	de->attr = attr;
+	dmb();
+	netsec_cache_flush((uintptr_t)de, sizeof(*de));
+}
+
+static void netsec_set_tx_de(struct netsec_priv *priv, void *addr, int len)
+{
+	struct netsec_de *de = &priv->txde[0];
+	u32 attr;
+
+	attr = (1 << NETSEC_TX_SHIFT_OWN_FIELD) |
+	       (1 << NETSEC_TX_SHIFT_PT_FIELD) |
+	       (NETSEC_RING_GMAC << NETSEC_TX_SHIFT_TDRID_FIELD) |
+	       (1 << NETSEC_TX_SHIFT_FS_FIELD) |
+	       (1 << NETSEC_TX_LAST) |
+	       (1 << NETSEC_TX_SHIFT_TRS_FIELD) |
+			(1 << NETSEC_TX_SHIFT_LD_FIELD);
+
+	de->data_buf_addr_up = upper_32_bits((dma_addr_t)addr);
+	de->data_buf_addr_lw = lower_32_bits((dma_addr_t)addr);
+	de->buf_len_info = len;
+	de->attr = attr;
+	dmb();
+	netsec_cache_flush((uintptr_t)de, sizeof(*de));
+}
+
+static int netsec_get_phy_reg(struct netsec_priv *priv,
+			      int phy_addr, int reg_addr)
+{
+	u32 data;
+	int ret;
+
+	if (phy_addr != 7)
+		return -EINVAL;
+
+	if (netsec_set_mac_reg(priv, GMAC_REG_GAR, NETSEC_GMAC_GAR_REG_GB |
+			       phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA |
+			       reg_addr << NETSEC_GMAC_GAR_REG_SHIFT_GR |
+			       (netsec_clk_type(priv->freq) <<
+				GMAC_REG_SHIFT_CR_GAR)))
+		return -ETIMEDOUT;
+
+	ret = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR,
+					 NETSEC_GMAC_GAR_REG_GB);
+	if (ret)
+		return ret;
+
+	ret = netsec_get_mac_reg(priv, GMAC_REG_GDR, &data);
+	if (ret)
+		return ret;
+
+	return data;
+}
+
+static int netsec_set_phy_reg(struct netsec_priv *priv,
+			      int phy_addr, int reg_addr, u16 val)
+{
+	int ret;
+
+	if (phy_addr != 7)
+		return -EINVAL;
+	if (netsec_set_mac_reg(priv, GMAC_REG_GDR, val))
+		return -ETIMEDOUT;
+
+	if (netsec_set_mac_reg(priv, GMAC_REG_GAR,
+			       phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA |
+			       reg_addr << NETSEC_GMAC_GAR_REG_SHIFT_GR |
+			       NETSEC_GMAC_GAR_REG_GW | NETSEC_GMAC_GAR_REG_GB |
+			       (netsec_clk_type(priv->freq) <<
+				GMAC_REG_SHIFT_CR_GAR)))
+		return -ETIMEDOUT;
+
+	ret = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR,
+					 NETSEC_GMAC_GAR_REG_GB);
+
+	/* Developerbox implements RTL8211E PHY and there is
+	 * a compatibility problem with F_GMAC4.
+	 * RTL8211E expects MDC clock must be kept toggling for several
+	 * clock cycle with MDIO high before entering the IDLE state.
+	 * To meet this requirement, netsec driver needs to issue dummy
+	 * read(e.g. read PHYID1(offset 0x2) register) right after write.
+	 */
+	netsec_get_phy_reg(priv, phy_addr, MII_PHYSID1);
+
+	return ret;
+}
+
+static int netsec_mac_update_to_phy_state(struct netsec_priv *priv)
+{
+	struct phy_device *phydev = priv->phydev;
+	u32 value = 0;
+
+	value = phydev->duplex ? NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON :
+				 NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON;
+
+	if (phydev->speed != SPEED_1000)
+		value |= NETSEC_MCR_PS;
+
+	if (phydev->interface != PHY_INTERFACE_MODE_GMII &&
+	    phydev->speed == SPEED_100)
+		value |= NETSEC_GMAC_MCR_REG_FES;
+
+	value |= NETSEC_GMAC_MCR_REG_CST | NETSEC_GMAC_MCR_REG_JE;
+
+	if (phy_interface_is_rgmii(phydev))
+		value |= NETSEC_GMAC_MCR_REG_IBN;
+
+	if (netsec_set_mac_reg(priv, GMAC_REG_MCR, value))
+		return -ETIMEDOUT;
+
+	return 0;
+}
+
+static int netsec_start_gmac(struct netsec_priv *priv)
+{
+	u32 value = 0;
+	int ret;
+
+	if (priv->max_speed != SPEED_1000)
+		value = (NETSEC_GMAC_MCR_REG_CST |
+			 NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON);
+
+	if (netsec_set_mac_reg(priv, GMAC_REG_MCR, value))
+		return -ETIMEDOUT;
+
+	if (netsec_set_mac_reg(priv, GMAC_REG_BMR,
+			       NETSEC_GMAC_BMR_REG_RESET))
+		return -ETIMEDOUT;
+
+	/* Wait soft reset */
+	mdelay(5);
+
+	ret = netsec_get_mac_reg(priv, GMAC_REG_BMR, &value);
+	if (ret)
+		return ret;
+
+	if (value & NETSEC_GMAC_BMR_REG_SWR)
+		return -EAGAIN;
+
+	netsec_write_reg(priv, MAC_REG_DESC_SOFT_RST, 1);
+	if (netsec_wait_while_busy(priv, MAC_REG_DESC_SOFT_RST, 1))
+		return -ETIMEDOUT;
+
+	netsec_write_reg(priv, MAC_REG_DESC_INIT, 1);
+	if (netsec_wait_while_busy(priv, MAC_REG_DESC_INIT, 1))
+		return -ETIMEDOUT;
+
+	if (netsec_set_mac_reg(priv, GMAC_REG_BMR,
+			       NETSEC_GMAC_BMR_REG_COMMON))
+		return -ETIMEDOUT;
+
+	if (netsec_set_mac_reg(priv, GMAC_REG_RDLAR,
+			       NETSEC_GMAC_RDLAR_REG_COMMON))
+		return -ETIMEDOUT;
+
+	if (netsec_set_mac_reg(priv, GMAC_REG_TDLAR,
+			       NETSEC_GMAC_TDLAR_REG_COMMON))
+		return -ETIMEDOUT;
+
+	if (netsec_set_mac_reg(priv, GMAC_REG_MFFR, 0x80000001))
+		return -ETIMEDOUT;
+
+	ret = netsec_mac_update_to_phy_state(priv);
+	if (ret)
+		return ret;
+
+	ret = netsec_get_mac_reg(priv, GMAC_REG_OMR, &value);
+	if (ret)
+		return ret;
+
+	value |= NETSEC_GMAC_OMR_REG_SR;
+	value |= NETSEC_GMAC_OMR_REG_ST;
+
+	netsec_write_reg(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0);
+	netsec_write_reg(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0);
+
+	if (netsec_set_mac_reg(priv, GMAC_REG_OMR, value))
+		return -ETIMEDOUT;
+
+	return 0;
+}
+
+static int netsec_stop_gmac(struct netsec_priv *priv)
+{
+	u32 value;
+	int ret;
+
+	ret = netsec_get_mac_reg(priv, GMAC_REG_OMR, &value);
+	if (ret)
+		return ret;
+	value &= ~NETSEC_GMAC_OMR_REG_SR;
+	value &= ~NETSEC_GMAC_OMR_REG_ST;
+
+	/* disable all interrupts */
+	netsec_write_reg(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0);
+	netsec_write_reg(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0);
+
+	return netsec_set_mac_reg(priv, GMAC_REG_OMR, value);
+}
+
+static void netsec_spi_read(char *buf, loff_t len, loff_t offset)
+{
+	struct udevice *new;
+	struct spi_flash *flash;
+
+	spi_flash_probe_bus_cs(CONFIG_SF_DEFAULT_BUS, CONFIG_SF_DEFAULT_CS,
+			       CONFIG_SF_DEFAULT_SPEED, CONFIG_SF_DEFAULT_MODE, &new);
+	flash = dev_get_uclass_priv(new);
+
+	spi_flash_read(flash, offset, len, buf);
+}
+
+static int netsec_read_rom_hwaddr(struct udevice *dev)
+{
+	struct netsec_priv *priv = dev_get_priv(dev);
+	struct eth_pdata *pdata = dev_get_plat(dev);
+	char macp[NOR_BLOCK];
+
+	netsec_spi_read(macp, sizeof(macp), priv->eeprom_base);
+
+	pdata->enetaddr[0] = readb(macp + 3);
+	pdata->enetaddr[1] = readb(macp + 2);
+	pdata->enetaddr[2] = readb(macp + 1);
+	pdata->enetaddr[3] = readb(macp + 0);
+	pdata->enetaddr[4] = readb(macp + 7);
+	pdata->enetaddr[5] = readb(macp + 6);
+	return 0;
+}
+
+static int netsec_send(struct udevice *dev, void *packet, int length)
+{
+	struct netsec_priv *priv = dev_get_priv(dev);
+	u32 val, tout;
+
+	val = netsec_read_reg(priv, NETSEC_REG_NRM_TX_STATUS);
+	netsec_cache_flush((uintptr_t)packet, length);
+	netsec_set_tx_de(priv, packet, length);
+	netsec_write_reg(priv, NETSEC_REG_NRM_TX_PKTCNT, 1); /* submit another tx */
+
+	val = netsec_read_reg(priv, NETSEC_REG_NRM_TX_PKTCNT);
+
+	tout = 10000;
+	do {
+		val = netsec_read_reg(priv, NETSEC_REG_NRM_TX_DONE_PKTCNT);
+		udelay(2);
+	} while (--tout && !val);
+
+	if (!tout) {
+		val = netsec_read_reg(priv, NETSEC_REG_NRM_TX_PKTCNT);
+		pr_err("%s: ETIMEDOUT:  %dpackets\n", __func__, val);
+		return -ETIMEDOUT;
+	}
+
+	return 0;
+}
+
+static int netsec_free_packet(struct udevice *dev, uchar *packet, int length)
+{
+	struct netsec_priv *priv = dev_get_priv(dev);
+
+	netsec_set_rx_de(priv, priv->rxat, net_rx_packets[priv->rxat]);
+
+	priv->rxat++;
+	if (priv->rxat == PKTBUFSRX)
+		priv->rxat = 0;
+
+	return 0;
+}
+
+static int netsec_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+	struct netsec_priv *priv = dev_get_priv(dev);
+	int idx = priv->rxat;
+	uchar *ptr = net_rx_packets[idx];
+	struct netsec_de *de = &priv->rxde[idx];
+	int length = 0;
+
+	netsec_cache_invalidate((uintptr_t)de, sizeof(*de));
+
+	if (de->attr & (1U << NETSEC_RX_PKT_OWN_FIELD))
+		return -EAGAIN;
+
+	length = de->buf_len_info >> 16;
+
+	/* invalidate after DMA is done */
+	netsec_cache_invalidate((uintptr_t)ptr, length);
+	*packetp = ptr;
+
+	return length;
+}
+
+static int _netsec_get_phy_reg(struct mii_dev *bus,
+			       int phy_addr, int devad, int reg_addr)
+{
+	return netsec_get_phy_reg(bus->priv, phy_addr, reg_addr);
+}
+
+static int _netsec_set_phy_reg(struct mii_dev *bus,
+			       int phy_addr, int devad, int reg_addr, u16 val)
+{
+	return netsec_set_phy_reg(bus->priv, phy_addr, reg_addr, val);
+}
+
+static int netsec_mdiobus_init(struct netsec_priv *priv, const char *name)
+{
+	struct mii_dev *bus = mdio_alloc();
+
+	if (!bus)
+		return -ENOMEM;
+
+	bus->read = _netsec_get_phy_reg;
+	bus->write = _netsec_set_phy_reg;
+	snprintf(bus->name, sizeof(bus->name), "%s", name);
+	bus->priv = priv;
+
+	return mdio_register(bus);
+}
+
+static int netsec_phy_init(struct netsec_priv *priv, void *dev)
+{
+	struct phy_device *phydev;
+	int ret;
+
+	phydev = phy_connect(priv->bus, priv->phy_addr, dev, priv->phy_mode);
+
+	phydev->supported &= PHY_GBIT_FEATURES;
+	if (priv->max_speed) {
+		ret = phy_set_supported(phydev, priv->max_speed);
+		if (ret)
+			return ret;
+	}
+	phydev->advertising = phydev->supported;
+
+	priv->phydev = phydev;
+	phy_config(phydev);
+
+	return 0;
+}
+
+static int netsec_netdev_load_ucode_region(struct netsec_priv *priv, u32 reg,
+					   u32 addr_h, u32 addr_l, u32 size)
+{
+	u64 base = ((u64)addr_h << 32 | addr_l) - EERPROM_MAP_OFFSET;
+
+	while (size > 0) {
+		char buf[NOR_BLOCK];
+		u32 *ucode = (u32 *)buf;
+		u64 off;
+		int i;
+
+		off = base % NOR_BLOCK;
+		base -= off;
+		netsec_spi_read(buf, sizeof(buf), base);
+
+		for (i = off / 4; i < sizeof(buf) / 4 && size > 0; i++, size--)
+			netsec_write_reg(priv, reg, ucode[i]);
+		base += NOR_BLOCK;
+	}
+
+	return 0;
+}
+
+static int netsec_netdev_load_microcode(struct netsec_priv *priv)
+{
+	u32 addr_h, addr_l, size;
+	char buf[NOR_BLOCK];
+	u32 *ucinfo = (u32 *)buf;
+	int err;
+
+	netsec_spi_read(buf, sizeof(buf), priv->eeprom_base);
+
+	addr_h = ucinfo[NETSEC_EEPROM_HM_ME_ADDRESS_H >> 2];
+	addr_l = ucinfo[NETSEC_EEPROM_HM_ME_ADDRESS_L >> 2];
+	size = ucinfo[NETSEC_EEPROM_HM_ME_SIZE >> 2];
+
+	err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_DMAC_HM_CMD_BUF,
+					      addr_h, addr_l, size);
+	if (err)
+		return err;
+
+	addr_h = ucinfo[NETSEC_EEPROM_MH_ME_ADDRESS_H >> 2];
+	addr_l = ucinfo[NETSEC_EEPROM_MH_ME_ADDRESS_L >> 2];
+	size = ucinfo[NETSEC_EEPROM_MH_ME_SIZE >> 2];
+
+	err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_DMAC_MH_CMD_BUF,
+					      addr_h, addr_l, size);
+	if (err)
+		return err;
+
+	addr_h = 0;
+	addr_l = ucinfo[NETSEC_EEPROM_PKT_ME_ADDRESS >> 2];
+	size = ucinfo[NETSEC_EEPROM_PKT_ME_SIZE >> 2];
+
+	err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_PKT_CMD_BUF,
+					      addr_h, addr_l, size);
+	if (err)
+		return err;
+
+	return 0;
+}
+
+void netsec_pre_init_microengine(struct netsec_priv *priv)
+{
+	u32 data;
+
+	/* Remove dormant settings */
+	data = netsec_get_phy_reg(priv, priv->phy_addr, MII_BMCR);
+	data &= ~BMCR_PDOWN;
+	data |= BMCR_ISOLATE;
+	netsec_set_phy_reg(priv, priv->phy_addr, MII_BMCR, data);
+	mdelay(100);
+
+	/* Put phy in loopback mode to guarantee RXCLK input */
+	data |= BMCR_LOOPBACK;
+	netsec_set_phy_reg(priv, priv->phy_addr, MII_BMCR, data);
+	mdelay(100);
+}
+
+void netsec_post_init_microengine(struct netsec_priv *priv)
+{
+	u32 data;
+
+	/* Get phy back to normal operation */
+	data = netsec_get_phy_reg(priv, priv->phy_addr, MII_BMCR);
+	data &= ~BMCR_LOOPBACK;
+	netsec_set_phy_reg(priv, priv->phy_addr, MII_BMCR, data);
+	mdelay(100);
+
+	/* Apply software reset */
+	data |= BMCR_RESET;
+	netsec_set_phy_reg(priv, priv->phy_addr, MII_BMCR, data);
+	mdelay(100);
+}
+
+static int netsec_reset_hardware(struct netsec_priv *priv, bool load_ucode)
+{
+	u32 value;
+	int err;
+
+	netsec_write_reg(priv, NETSEC_REG_CLK_EN, 0x24);
+
+	/* stop DMA engines */
+	if (!netsec_read_reg(priv, NETSEC_REG_ADDR_DIS_CORE)) {
+		netsec_write_reg(priv, NETSEC_REG_DMA_HM_CTRL,
+				 NETSEC_DMA_CTRL_REG_STOP);
+		netsec_write_reg(priv, NETSEC_REG_DMA_MH_CTRL,
+				 NETSEC_DMA_CTRL_REG_STOP);
+
+		value = 100;
+		while (netsec_read_reg(priv, NETSEC_REG_DMA_HM_CTRL) &
+		       NETSEC_DMA_CTRL_REG_STOP) {
+			udelay(1000);
+			if (--value == 0) {
+				pr_err("%s:%d timeout!\n", __func__, __LINE__);
+				break;
+			}
+		}
+
+		value = 100;
+		while (netsec_read_reg(priv, NETSEC_REG_DMA_MH_CTRL) &
+		       NETSEC_DMA_CTRL_REG_STOP) {
+			udelay(1000);
+			if (--value == 0) {
+				pr_err("%s:%d timeout!\n", __func__, __LINE__);
+				break;
+			}
+		}
+	}
+
+	netsec_set_mac_reg(priv, GMAC_REG_BMR, NETSEC_GMAC_BMR_REG_RESET);
+
+	netsec_write_reg(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RESET);
+	netsec_write_reg(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RUN);
+	netsec_write_reg(priv, NETSEC_REG_COM_INIT, NETSEC_COM_INIT_REG_ALL);
+
+	value = 100;
+	while (netsec_read_reg(priv, NETSEC_REG_COM_INIT) != 0) {
+		udelay(1000);
+		if (--value == 0) {
+			pr_err("%s:%d COM_INIT timeout!\n", __func__, __LINE__);
+			break;
+		}
+	}
+
+	/* MAC desc init */
+	netsec_write_reg(priv, MAC_REG_DESC_INIT, 1);
+	netsec_wait_while_busy(priv, MAC_REG_DESC_INIT, 1);
+	/* set MAC_INTF_SEL */
+	netsec_write_reg(priv, MAC_REG_INTF_SEL, 1);
+
+	netsec_write_reg(priv, NETSEC_REG_CLK_EN, 1 << 5);
+
+	/* set desc_start addr */
+	netsec_write_reg(priv, NETSEC_REG_NRM_RX_DESC_START_UP,
+			 upper_32_bits((dma_addr_t)priv->rxde));
+	netsec_write_reg(priv, NETSEC_REG_NRM_RX_DESC_START_LW,
+			 lower_32_bits((dma_addr_t)priv->rxde));
+
+	netsec_write_reg(priv, NETSEC_REG_NRM_TX_DESC_START_UP,
+			 upper_32_bits((dma_addr_t)priv->txde));
+	netsec_write_reg(priv, NETSEC_REG_NRM_TX_DESC_START_LW,
+			 lower_32_bits((dma_addr_t)priv->txde));
+
+	/* set normal tx dring ring config */
+	netsec_write_reg(priv, NETSEC_REG_NRM_TX_CONFIG,
+			 1 << NETSEC_REG_DESC_ENDIAN);
+	netsec_write_reg(priv, NETSEC_REG_NRM_RX_CONFIG,
+			 1 << NETSEC_REG_DESC_ENDIAN);
+
+	if (load_ucode) {
+		err = netsec_netdev_load_microcode(priv);
+		if (err) {
+			pr_err("%s: failed to load microcode (%d)\n",
+			       __func__, err);
+			return err;
+		}
+	}
+
+	/* set desc_start addr */
+	netsec_write_reg(priv, NETSEC_REG_NRM_RX_DESC_START_UP,
+			 upper_32_bits((dma_addr_t)priv->rxde));
+	netsec_write_reg(priv, NETSEC_REG_NRM_RX_DESC_START_LW,
+			 lower_32_bits((dma_addr_t)priv->rxde));
+
+	netsec_write_reg(priv, NETSEC_REG_NRM_TX_DESC_START_UP,
+			 upper_32_bits((dma_addr_t)priv->txde));
+	netsec_write_reg(priv, NETSEC_REG_NRM_TX_DESC_START_LW,
+			 lower_32_bits((dma_addr_t)priv->txde));
+
+	netsec_write_reg(priv, NETSEC_REG_CLK_EN, 1 << 5);
+
+	/* start DMA engines */
+	netsec_write_reg(priv, NETSEC_REG_DMA_TMR_CTRL, priv->freq / 1000000 - 1);
+
+	netsec_pre_init_microengine(priv);
+
+	netsec_write_reg(priv, NETSEC_REG_ADDR_DIS_CORE, 0);
+
+	mdelay(100);
+
+	if (!(netsec_read_reg(priv, NETSEC_REG_TOP_STATUS) &
+	      NETSEC_TOP_IRQ_REG_ME_START)) {
+		pr_err("microengine start failed\n");
+		return -ENXIO;
+	}
+
+	netsec_post_init_microengine(priv);
+
+	/* clear microcode load end status */
+	netsec_write_reg(priv, NETSEC_REG_TOP_STATUS,
+			 NETSEC_TOP_IRQ_REG_ME_START);
+
+	netsec_write_reg(priv, NETSEC_REG_CLK_EN, 1 << 5);
+
+	value = netsec_read_reg(priv, NETSEC_REG_PKT_CTRL);
+	value |= NETSEC_PKT_CTRL_REG_MODE_NRM;
+	/* change to normal mode */
+	netsec_write_reg(priv, NETSEC_REG_DMA_MH_CTRL, MH_CTRL__MODE_TRANS);
+	netsec_write_reg(priv, NETSEC_REG_PKT_CTRL, value);
+
+	value = 100;
+	while ((netsec_read_reg(priv, NETSEC_REG_MODE_TRANS_COMP_STATUS) &
+		NETSEC_MODE_TRANS_COMP_IRQ_T2N) == 0) {
+		udelay(1000);
+		if (--value == 0) {
+			value = netsec_read_reg(priv, NETSEC_REG_MODE_TRANS_COMP_STATUS);
+			pr_err("%s:%d timeout! val=%x\n", __func__, __LINE__, value);
+			break;
+		}
+	}
+
+	/* clear any pending EMPTY/ERR irq status */
+	netsec_write_reg(priv, NETSEC_REG_NRM_TX_STATUS, ~0);
+
+	/* Disable TX & RX intr */
+	netsec_write_reg(priv, NETSEC_REG_INTEN_CLR, ~0);
+
+	return 0;
+}
+
+static void netsec_stop(struct udevice *dev)
+{
+	struct netsec_priv *priv = dev_get_priv(dev);
+
+	netsec_write_reg(priv, NETSEC_REG_ADDR_DIS_CORE, 7);
+	netsec_stop_gmac(priv);
+	phy_shutdown(priv->phydev);
+	netsec_reset_hardware(priv, false);
+}
+
+static int netsec_start(struct udevice *dev)
+{
+	struct netsec_priv *priv = dev_get_priv(dev);
+	int i;
+
+	phy_startup(priv->phydev);
+	netsec_start_gmac(priv);
+
+	priv->rxat = 0;
+	for (i = 0; i < PKTBUFSRX; i++)
+		netsec_set_rx_de(priv, i, net_rx_packets[i]);
+
+	return 0;
+}
+
+static int netsec_of_to_plat(struct udevice *dev)
+{
+	struct eth_pdata *pdata = dev_get_plat(dev);
+	struct netsec_priv *priv = dev_get_priv(dev);
+	struct ofnode_phandle_args phandle_args;
+	const char *phy_mode;
+
+	pdata->iobase = dev_read_addr_index(dev, 0);
+	priv->eeprom_base = dev_read_addr_index(dev, 1) - EERPROM_MAP_OFFSET;
+
+	pdata->phy_interface = -1;
+	phy_mode = dev_read_prop(dev, "phy-mode", NULL);
+	if (phy_mode)
+		pdata->phy_interface = phy_get_interface_by_name(phy_mode);
+	if (pdata->phy_interface == -1) {
+		pr_err("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
+		return -EINVAL;
+	}
+
+	if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
+					&phandle_args))
+		priv->phy_addr = ofnode_read_u32_default(phandle_args.node, "reg", 7);
+	else
+		priv->phy_addr = 7;
+
+	pdata->max_speed = dev_read_u32_default(dev, "max-speed", SPEED_1000);
+
+	priv->ioaddr = pdata->iobase;
+	priv->phy_mode = pdata->phy_interface;
+	priv->max_speed = pdata->max_speed;
+	priv->freq = 250000000UL;
+
+	return 0;
+}
+
+#define SMMU_SCR0_SHCFG_INNER             (0x2 << 22)
+#define SMMU_SCR0_MTCFG                   (0x1 << 20)
+#define SMMU_SCR0_MEMATTR_INNER_OUTER_WB  (0xf << 16)
+
+static int netsec_probe(struct udevice *dev)
+{
+	struct netsec_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	writel(SMMU_SCR0_SHCFG_INNER | SMMU_SCR0_MTCFG | SMMU_SCR0_MEMATTR_INNER_OUTER_WB,
+	       (phys_addr_t)0x52E00000);
+
+	netsec_reset_hardware(priv, true);
+
+	ret = netsec_mdiobus_init(priv, dev->name);
+	if (ret) {
+		pr_err("Failed to initialize mdiobus: %d\n", ret);
+		return ret;
+	}
+
+	priv->bus = miiphy_get_dev_by_name(dev->name);
+
+	ret = netsec_phy_init(priv, dev);
+	if (ret) {
+		pr_err("Failed to initialize phy: %d\n", ret);
+		goto out_mdiobus_release;
+	}
+
+	return 0;
+out_mdiobus_release:
+	mdio_unregister(priv->bus);
+	mdio_free(priv->bus);
+	return ret;
+}
+
+static int netsec_remove(struct udevice *dev)
+{
+	struct netsec_priv *priv = dev_get_priv(dev);
+
+	free(priv->phydev);
+	mdio_unregister(priv->bus);
+	mdio_free(priv->bus);
+
+	return 0;
+}
+
+static const struct eth_ops netsec_ops = {
+	.start        = netsec_start,
+	.stop         = netsec_stop,
+	.send         = netsec_send,
+	.recv         = netsec_recv,
+	.free_pkt     = netsec_free_packet,
+	.read_rom_hwaddr = netsec_read_rom_hwaddr,
+};
+
+static const struct udevice_id netsec_ids[] = {
+	{
+		.compatible = "socionext,synquacer-netsec",
+	},
+	{}
+};
+
+U_BOOT_DRIVER(ave) = {
+	.name     = "synquacer_netsec",
+	.id       = UCLASS_ETH,
+	.of_match = netsec_ids,
+	.probe	  = netsec_probe,
+	.remove	  = netsec_remove,
+	.of_to_plat = netsec_of_to_plat,
+	.ops	  = &netsec_ops,
+	.priv_auto	= sizeof(struct netsec_priv),
+	.plat_auto	= sizeof(struct eth_pdata),
+};
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index 5a1b38b..d7553fe 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -211,7 +211,9 @@ static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
 	 * The EMAC clock is either 200 or 300 MHz, so we need a divider
 	 * of 128 to get the MDIO frequency below the required 2.5 MHz.
 	 */
-	mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 << MDIO_CMD_MII_CLK_CSR_SHIFT;
+	if (!priv->use_internal_phy)
+		mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 <<
+			   MDIO_CMD_MII_CLK_CSR_SHIFT;
 
 	mii_cmd |= MDIO_CMD_MII_BUSY;
 
@@ -242,7 +244,9 @@ static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
 	 * The EMAC clock is either 200 or 300 MHz, so we need a divider
 	 * of 128 to get the MDIO frequency below the required 2.5 MHz.
 	 */
-	mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 << MDIO_CMD_MII_CLK_CSR_SHIFT;
+	if (!priv->use_internal_phy)
+		mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 <<
+			   MDIO_CMD_MII_CLK_CSR_SHIFT;
 
 	mii_cmd |= MDIO_CMD_MII_WRITE;
 	mii_cmd |= MDIO_CMD_MII_BUSY;
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index c68e4b7..ee820aa 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -828,6 +828,7 @@ int tsec_probe(struct udevice *dev)
 	const char *phy_mode;
 	ofnode parent, child;
 	fdt_addr_t reg;
+	u32 max_speed;
 	int ret;
 
 	data = (struct tsec_data *)dev_get_driver_data(dev);
@@ -893,8 +894,12 @@ int tsec_probe(struct udevice *dev)
 	}
 	priv->interface = pdata->phy_interface;
 
+	/* Check for speed limit, default is 1000Mbps */
+	max_speed = dev_read_u32_default(dev, "max-speed", 1000);
+
 	/* Initialize flags */
-	priv->flags = TSEC_GIGABIT;
+	if (max_speed == 1000)
+		priv->flags = TSEC_GIGABIT;
 	if (priv->interface == PHY_INTERFACE_MODE_SGMII)
 		priv->flags |= TSEC_SGMII;