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| author | Vladimir Oltean <vladimir.oltean@nxp.com> | 2020-05-07 00:11:50 +0200 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-05-07 11:05:00 -0400 |
| commit | a234ae863a413d371a0abc36f9e0aa9c1726e331 (patch) | |
| tree | f2bd5590fbd10ccc881cc7865d5b8f40a10f30f2 /drivers/net/phy | |
| parent | 29602f9c4b8efd9afcb2212eda0e13483ca6ec5d (diff) | |
| download | u-boot-a234ae863a413d371a0abc36f9e0aa9c1726e331.zip u-boot-a234ae863a413d371a0abc36f9e0aa9c1726e331.tar.gz u-boot-a234ae863a413d371a0abc36f9e0aa9c1726e331.tar.bz2 | |
phy: atheros: Clarify the configuration of the CLK_25M output pin
Also take the opportunity to use the phy_read_mmd and phy_write_mmd
convenience functions.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Diffstat (limited to 'drivers/net/phy')
| -rw-r--r-- | drivers/net/phy/atheros.c | 19 |
1 files changed, 14 insertions, 5 deletions
diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index c0c2b4d..1da18eb 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -17,6 +17,15 @@ #define AR803x_DEBUG_REG_0 0x0 #define AR803x_RGMII_RX_CLK_DLY BIT(15) +/* CLK_25M register is at MMD 7, address 0x8016 */ +#define AR803x_CLK_25M_SEL_REG 0x8016 +/* AR8035: Select frequency on CLK_25M pin through bits 4:3 */ +#define AR8035_CLK_25M_FREQ_25M (0 | 0) +#define AR8035_CLK_25M_FREQ_50M (0 | BIT(3)) +#define AR8035_CLK_25M_FREQ_62M (BIT(4) | 0) +#define AR8035_CLK_25M_FREQ_125M (BIT(4) | BIT(3)) +#define AR8035_CLK_25M_MASK GENMASK(4, 3) + static void ar803x_enable_rx_delay(struct phy_device *phydev, bool on) { int regval; @@ -78,11 +87,11 @@ static int ar8035_config(struct phy_device *phydev) { int regval; - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x0007); - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); - regval = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, (regval|0x0018)); + /* Configure CLK_25M output clock at 125 MHz */ + regval = phy_read_mmd(phydev, MDIO_MMD_AN, AR803x_CLK_25M_SEL_REG); + regval &= ~AR8035_CLK_25M_MASK; /* No surprises */ + regval |= AR8035_CLK_25M_FREQ_125M; + phy_write_mmd(phydev, MDIO_MMD_AN, AR803x_CLK_25M_SEL_REG, regval); if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) || (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) |