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| author | Pratyush Yadav <p.yadav@ti.com> | 2021-06-26 00:47:22 +0530 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2021-06-28 12:04:09 +0530 |
| commit | b058f108d7d91f9a5f47c1d0d3ddf4e6ae030440 (patch) | |
| tree | 3cc97af664187c128a6ccde9ceddb63a25a1147c /drivers/mtd | |
| parent | 6b808e0864dbd492d33e7149fb1666bef7e56049 (diff) | |
| download | u-boot-b058f108d7d91f9a5f47c1d0d3ddf4e6ae030440.zip u-boot-b058f108d7d91f9a5f47c1d0d3ddf4e6ae030440.tar.gz u-boot-b058f108d7d91f9a5f47c1d0d3ddf4e6ae030440.tar.bz2 | |
mtd: spi-nor-core: Do not make invalid quad enable fatal
The Micron MT35XU512ABA flash does not support the quad enable bit. But
instead of programming the Quad Enable Require field to 000b ("Device
does not have a QE bit"), it is programmed to 111b ("Reserved").
While this is technically incorrect, it is not reason enough to abort
BFPT parsing. Instead, continue BFPT parsing assuming there is no quad
enable bit present.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'drivers/mtd')
| -rw-r--r-- | drivers/mtd/spi/spi-nor-core.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index cdb4648..b5b1ac8 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -2100,7 +2100,8 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, break; #endif default: - return -EINVAL; + dev_dbg(nor->dev, "BFPT QER reserved value used\n"); + break; } /* Stop here if JESD216 rev B. */ |