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author | Peter Griffin <peter.griffin@linaro.org> | 2015-07-30 18:55:18 +0100 |
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committer | Tom Rini <trini@konsulko.com> | 2015-08-12 20:47:58 -0400 |
commit | 152f489841769531f2ba7d0ffc7a3bb239c43421 (patch) | |
tree | d8e42d9d89a1d8d0c1d54a4638d2e2d294d9fec0 /drivers/gpio | |
parent | 210fbee901b13d8e21568fc3e00932f3e082c178 (diff) | |
download | u-boot-152f489841769531f2ba7d0ffc7a3bb239c43421.zip u-boot-152f489841769531f2ba7d0ffc7a3bb239c43421.tar.gz u-boot-152f489841769531f2ba7d0ffc7a3bb239c43421.tar.bz2 |
dm: gpio: hi6220: Add a hi6220 GPIO driver model driver.
This patch adds support for the GPIO perif found on hi6220
SoC.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Diffstat (limited to 'drivers/gpio')
-rw-r--r-- | drivers/gpio/Makefile | 2 | ||||
-rw-r--r-- | drivers/gpio/hi6220_gpio.c | 95 |
2 files changed, 97 insertions, 0 deletions
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 67c6374..26f2574 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -42,3 +42,5 @@ obj-$(CONFIG_LPC32XX_GPIO) += lpc32xx_gpio.o obj-$(CONFIG_STM32_GPIO) += stm32_gpio.o obj-$(CONFIG_ZYNQ_GPIO) += zynq_gpio.o obj-$(CONFIG_VYBRID_GPIO) += vybrid_gpio.o +obj-$(CONFIG_HIKEY_GPIO) += hi6220_gpio.o + diff --git a/drivers/gpio/hi6220_gpio.c b/drivers/gpio/hi6220_gpio.c new file mode 100644 index 0000000..3f41bff --- /dev/null +++ b/drivers/gpio/hi6220_gpio.c @@ -0,0 +1,95 @@ +/* + * Copyright (C) 2015 Linaro + * Peter Griffin <peter.griffin@linaro.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <errno.h> + +static int hi6220_gpio_direction_input(struct udevice *dev, unsigned int gpio) +{ + struct gpio_bank *bank = dev_get_priv(dev); + u8 data; + + data = readb(bank->base + HI6220_GPIO_DIR); + data &= ~(1 << gpio); + writeb(data, bank->base + HI6220_GPIO_DIR); + + return 0; +} + +static int hi6220_gpio_set_value(struct udevice *dev, unsigned gpio, + int value) +{ + struct gpio_bank *bank = dev_get_priv(dev); + + writeb(!!value << gpio, bank->base + (BIT(gpio + 2))); + return 0; +} + +static int hi6220_gpio_direction_output(struct udevice *dev, unsigned gpio, + int value) +{ + struct gpio_bank *bank = dev_get_priv(dev); + u8 data; + + data = readb(bank->base + HI6220_GPIO_DIR); + data |= 1 << gpio; + writeb(data, bank->base + HI6220_GPIO_DIR); + + hi6220_gpio_set_value(dev, gpio, value); + + return 0; +} + +static int hi6220_gpio_get_value(struct udevice *dev, unsigned gpio) +{ + struct gpio_bank *bank = dev_get_priv(dev); + + return !!readb(bank->base + (BIT(gpio + 2))); +} + + + +static const struct dm_gpio_ops gpio_hi6220_ops = { + .direction_input = hi6220_gpio_direction_input, + .direction_output = hi6220_gpio_direction_output, + .get_value = hi6220_gpio_get_value, + .set_value = hi6220_gpio_set_value, +}; + +static int hi6220_gpio_probe(struct udevice *dev) +{ + struct gpio_bank *bank = dev_get_priv(dev); + struct hikey_gpio_platdata *plat = dev_get_platdata(dev); + struct gpio_dev_priv *uc_priv = dev->uclass_priv; + char name[18], *str; + + sprintf(name, "GPIO%d_", plat->bank_index); + + str = strdup(name); + if (!str) + return -ENOMEM; + + uc_priv->bank_name = str; + uc_priv->gpio_count = HI6220_GPIO_PER_BANK; + + bank->base = (u8 *)plat->base; + + return 0; +} + +U_BOOT_DRIVER(gpio_hi6220) = { + .name = "gpio_hi6220", + .id = UCLASS_GPIO, + .ops = &gpio_hi6220_ops, + .probe = hi6220_gpio_probe, + .priv_auto_alloc_size = sizeof(struct gpio_bank), +}; + + |