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| author | Caleb Connolly <caleb.connolly@linaro.org> | 2024-02-26 17:26:17 +0000 |
|---|---|---|
| committer | Caleb Connolly <caleb.connolly@linaro.org> | 2024-03-01 14:44:36 +0000 |
| commit | a245aece2acfbbaf01f41c595f9bfb02a9aedb70 (patch) | |
| tree | b85ecd5a7a36f9b851d8c56c8908568dcf6aafc7 /drivers/gpio/msm_gpio.c | |
| parent | cc18d5486b2cb520d50d2154fc2e9fe2566f480c (diff) | |
| download | u-boot-a245aece2acfbbaf01f41c595f9bfb02a9aedb70.zip u-boot-a245aece2acfbbaf01f41c595f9bfb02a9aedb70.tar.gz u-boot-a245aece2acfbbaf01f41c595f9bfb02a9aedb70.tar.bz2 | |
pinctrl: qcom: stub support for special GPIOs
Most platforms have a handful of "special" GPIOs, like the MMC
clock/data lanes, UFS reset, etc. These don't follow the usual naming
scheme of "gpioX" and also have unique capabilities and registers. We
can get away without supporting them all for now, but DT compatibility
is still an issue.
Add support for allowing these to be specified after the other pins, and
make all pinmux/pinconf calls for them nop.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Diffstat (limited to 'drivers/gpio/msm_gpio.c')
| -rw-r--r-- | drivers/gpio/msm_gpio.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c index 80cd28b..5e57b0c 100644 --- a/drivers/gpio/msm_gpio.c +++ b/drivers/gpio/msm_gpio.c @@ -39,6 +39,10 @@ static int msm_gpio_direction_input(struct udevice *dev, unsigned int gpio) { struct msm_gpio_bank *priv = dev_get_priv(dev); + /* Always NOP for special pins, assume they're in the correct state */ + if (qcom_is_special_pin(priv->pin_data, gpio)) + return 0; + /* Disable OE bit */ clrsetbits_le32(priv->base + GPIO_CONFIG_REG(dev, gpio), GPIO_OE_MASK, GPIO_OE_DISABLE); @@ -50,6 +54,10 @@ static int msm_gpio_set_value(struct udevice *dev, unsigned int gpio, int value) { struct msm_gpio_bank *priv = dev_get_priv(dev); + /* Always NOP for special pins, assume they're in the correct state */ + if (qcom_is_special_pin(priv->pin_data, gpio)) + return 0; + value = !!value; /* set value */ writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_REG(dev, gpio)); @@ -62,6 +70,10 @@ static int msm_gpio_direction_output(struct udevice *dev, unsigned int gpio, { struct msm_gpio_bank *priv = dev_get_priv(dev); + /* Always NOP for special pins, assume they're in the correct state */ + if (qcom_is_special_pin(priv->pin_data, gpio)) + return 0; + value = !!value; /* set value */ writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_REG(dev, gpio)); @@ -76,6 +88,10 @@ static int msm_gpio_get_value(struct udevice *dev, unsigned int gpio) { struct msm_gpio_bank *priv = dev_get_priv(dev); + /* Always NOP for special pins, assume they're in the correct state */ + if (qcom_is_special_pin(priv->pin_data, gpio)) + return 0; + return !!(readl(priv->base + GPIO_IN_OUT_REG(dev, gpio)) >> GPIO_IN); } @@ -83,6 +99,10 @@ static int msm_gpio_get_function(struct udevice *dev, unsigned int gpio) { struct msm_gpio_bank *priv = dev_get_priv(dev); + /* Always NOP for special pins, assume they're in the correct state */ + if (qcom_is_special_pin(priv->pin_data, gpio)) + return 0; + if (readl(priv->base + GPIO_CONFIG_REG(dev, gpio)) & GPIO_OE_ENABLE) return GPIOF_OUTPUT; |