diff options
author | Amit Singh Tomar <amittomer25@gmail.com> | 2020-04-19 19:28:30 +0530 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2020-04-24 16:40:09 -0400 |
commit | 8b520ac15300ed8ae146979554757d8702c35e67 (patch) | |
tree | 6bc52ada21135af4ee3717e8100f15528030208e /drivers/clk | |
parent | 5bc4c0bccc360692b5d140b1da5235d7ea56325f (diff) | |
download | u-boot-8b520ac15300ed8ae146979554757d8702c35e67.zip u-boot-8b520ac15300ed8ae146979554757d8702c35e67.tar.gz u-boot-8b520ac15300ed8ae146979554757d8702c35e67.tar.bz2 |
clk: actions: Add common clock driver
This patch converts S900 clock driver to something common that can
be used for other SoCs, for instance S700(few of clk registers are same).
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
Diffstat (limited to 'drivers/clk')
-rw-r--r-- | drivers/clk/owl/Kconfig | 8 | ||||
-rw-r--r-- | drivers/clk/owl/Makefile | 2 | ||||
-rw-r--r-- | drivers/clk/owl/clk_owl.c (renamed from drivers/clk/owl/clk_s900.c) | 72 | ||||
-rw-r--r-- | drivers/clk/owl/clk_owl.h | 64 |
4 files changed, 112 insertions, 34 deletions
diff --git a/drivers/clk/owl/Kconfig b/drivers/clk/owl/Kconfig index 661f198..c6afef9 100644 --- a/drivers/clk/owl/Kconfig +++ b/drivers/clk/owl/Kconfig @@ -3,10 +3,6 @@ config CLK_OWL depends on CLK && ARCH_OWL help Enable support for clock managemet unit present in Actions Semi - OWL SoCs. + Owl series S900/S700 SoCs. + -config CLK_S900 - bool "Actions Semi S900 clock driver" - depends on CLK_OWL && ARM64 - help - Enable support for the clocks in Actions Semi S900 SoC. diff --git a/drivers/clk/owl/Makefile b/drivers/clk/owl/Makefile index 63ab573..5218b6b 100644 --- a/drivers/clk/owl/Makefile +++ b/drivers/clk/owl/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0+ -obj-$(CONFIG_CLK_S900) += clk_s900.o +obj-$(CONFIG_CLK_OWL) += clk_owl.o diff --git a/drivers/clk/owl/clk_s900.c b/drivers/clk/owl/clk_owl.c index d60f199..5607b2b 100644 --- a/drivers/clk/owl/clk_s900.c +++ b/drivers/clk/owl/clk_owl.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Actions Semi S900 clock driver + * Common clock driver for Actions Semi SoCs. * * Copyright (C) 2015 Actions Semi Co., Ltd. * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> @@ -8,20 +8,25 @@ #include <common.h> #include <dm.h> -#include <asm/arch-owl/clk_s900.h> -#include <asm/arch-owl/regs_s900.h> +#include "clk_owl.h" #include <asm/io.h> - +#if defined(CONFIG_MACH_S900) +#include <asm/arch-owl/regs_s900.h> #include <dt-bindings/clock/actions,s900-cmu.h> +#elif defined(CONFIG_MACH_S700) +#include <asm/arch-owl/regs_s700.h> +#include <dt-bindings/clock/actions,s700-cmu.h> +#endif void owl_clk_init(struct owl_clk_priv *priv) { u32 bus_clk = 0, core_pll, dev_pll; +#if defined(CONFIG_MACH_S900) /* Enable ASSIST_PLL */ setbits_le32(priv->base + CMU_ASSISTPLL, BIT(0)); - udelay(PLL_STABILITY_WAIT_US); +#endif /* Source HOSC to DEV_CLK */ clrbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK); @@ -58,31 +63,30 @@ void owl_clk_init(struct owl_clk_priv *priv) udelay(PLL_STABILITY_WAIT_US); } -void owl_uart_clk_enable(struct owl_clk_priv *priv) -{ - /* Source HOSC for UART5 interface */ - clrbits_le32(priv->base + CMU_UART5CLK, CMU_UARTCLK_SRC_DEVPLL); - - /* Enable UART5 interface clock */ - setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5); -} - -void owl_uart_clk_disable(struct owl_clk_priv *priv) -{ - /* Disable UART5 interface clock */ - clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5); -} - int owl_clk_enable(struct clk *clk) { struct owl_clk_priv *priv = dev_get_priv(clk->dev); + enum owl_soc model = dev_get_driver_data(clk->dev); switch (clk->id) { case CLK_UART5: - owl_uart_clk_enable(priv); + if (model != S900) + return -EINVAL; + /* Source HOSC for UART5 interface */ + clrbits_le32(priv->base + CMU_UART5CLK, CMU_UARTCLK_SRC_DEVPLL); + /* Enable UART5 interface clock */ + setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5); + break; + case CLK_UART3: + if (model != S700) + return -EINVAL; + /* Source HOSC for UART3 interface */ + clrbits_le32(priv->base + CMU_UART3CLK, CMU_UARTCLK_SRC_DEVPLL); + /* Enable UART3 interface clock */ + setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART3); break; default: - return 0; + return -EINVAL; } return 0; @@ -91,13 +95,23 @@ int owl_clk_enable(struct clk *clk) int owl_clk_disable(struct clk *clk) { struct owl_clk_priv *priv = dev_get_priv(clk->dev); + enum owl_soc model = dev_get_driver_data(clk->dev); switch (clk->id) { case CLK_UART5: - owl_uart_clk_disable(priv); + if (model != S900) + return -EINVAL; + /* Disable UART5 interface clock */ + clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5); + break; + case CLK_UART3: + if (model != S700) + return -EINVAL; + /* Disable UART3 interface clock */ + clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART3); break; default: - return 0; + return -EINVAL; } return 0; @@ -117,18 +131,22 @@ static int owl_clk_probe(struct udevice *dev) return 0; } -static struct clk_ops owl_clk_ops = { +static const struct clk_ops owl_clk_ops = { .enable = owl_clk_enable, .disable = owl_clk_disable, }; static const struct udevice_id owl_clk_ids[] = { - { .compatible = "actions,s900-cmu" }, +#if defined(CONFIG_MACH_S900) + { .compatible = "actions,s900-cmu", .data = S900 }, +#elif defined(CONFIG_MACH_S700) + { .compatible = "actions,s700-cmu", .data = S700 }, +#endif { } }; U_BOOT_DRIVER(clk_owl) = { - .name = "clk_s900", + .name = "clk_owl", .id = UCLASS_CLK, .of_match = owl_clk_ids, .ops = &owl_clk_ops, diff --git a/drivers/clk/owl/clk_owl.h b/drivers/clk/owl/clk_owl.h new file mode 100644 index 0000000..b8d3362 --- /dev/null +++ b/drivers/clk/owl/clk_owl.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Actions Semi SoCs Clock Definitions + * + * Copyright (C) 2015 Actions Semi Co., Ltd. + * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + * + */ + +#ifndef _OWL_CLK_H_ +#define _OWL_CLK_H_ + +#include <clk-uclass.h> + +enum owl_soc { + S700, + S900, +}; + +struct owl_clk_priv { + phys_addr_t base; +}; + +/* BUSCLK register definitions */ +#define CMU_PDBGDIV_8 7 +#define CMU_PDBGDIV_SHIFT 26 +#define CMU_PDBGDIV_DIV (CMU_PDBGDIV_8 << CMU_PDBGDIV_SHIFT) +#define CMU_PERDIV_8 7 +#define CMU_PERDIV_SHIFT 20 +#define CMU_PERDIV_DIV (CMU_PERDIV_8 << CMU_PERDIV_SHIFT) +#define CMU_NOCDIV_2 1 +#define CMU_NOCDIV_SHIFT 19 +#define CMU_NOCDIV_DIV (CMU_NOCDIV_2 << CMU_NOCDIV_SHIFT) +#define CMU_DMMCLK_SRC_APLL 2 +#define CMU_DMMCLK_SRC_SHIFT 10 +#define CMU_DMMCLK_SRC (CMU_DMMCLK_SRC_APLL << CMU_DMMCLK_SRC_SHIFT) +#define CMU_APBCLK_DIV BIT(8) +#define CMU_NOCCLK_SRC BIT(7) +#define CMU_AHBCLK_DIV BIT(4) +#define CMU_CORECLK_MASK 3 +#define CMU_CORECLK_CPLL BIT(1) +#define CMU_CORECLK_HOSC BIT(0) + +/* COREPLL register definitions */ +#define CMU_COREPLL_EN BIT(9) +#define CMU_COREPLL_HOSC_EN BIT(8) +#define CMU_COREPLL_OUT (1104 / 24) + +/* DEVPLL register definitions */ +#define CMU_DEVPLL_CLK BIT(12) +#define CMU_DEVPLL_EN BIT(8) +#define CMU_DEVPLL_OUT (660 / 6) + +/* UARTCLK register definitions */ +#define CMU_UARTCLK_SRC_DEVPLL BIT(16) + +#define PLL_STABILITY_WAIT_US 50 + +#define CMU_DEVCLKEN1_UART5 BIT(21) +#define CMU_DEVCLKEN1_UART3 BIT(11) + +#define CMU_DEVCLKEN1_ETH_S700 BIT(23) + +#endif |