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| author | Jagan Teki <jagan@edgeble.ai> | 2024-01-17 13:21:47 +0530 |
|---|---|---|
| committer | Anatolij Gustschin <agust@denx.de> | 2024-04-21 09:07:00 +0200 |
| commit | f7f4789814188cae77c3610228ffd9661a5fae9a (patch) | |
| tree | ea1fd1ef64e0ae133825adf208b3e319c59f5f97 /drivers/clk/rockchip | |
| parent | 92edae779f8c94a49d2f3e215b1ca0adf1241d53 (diff) | |
| download | u-boot-f7f4789814188cae77c3610228ffd9661a5fae9a.zip u-boot-f7f4789814188cae77c3610228ffd9661a5fae9a.tar.gz u-boot-f7f4789814188cae77c3610228ffd9661a5fae9a.tar.bz2 | |
clk: rk3328: Add get hdmiphy clock
Add support to get the hdmiphy clock for RK3328 PCLK_HDMIPHY.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Diffstat (limited to 'drivers/clk/rockchip')
| -rw-r--r-- | drivers/clk/rockchip/clk_rk3328.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c index df6076e..87075ec 100644 --- a/drivers/clk/rockchip/clk_rk3328.c +++ b/drivers/clk/rockchip/clk_rk3328.c @@ -178,6 +178,10 @@ enum { CLK_I2C3_DIV_CON_SHIFT = 8, CLK_I2C2_PLL_SEL_SHIFT = 7, CLK_I2C2_DIV_CON_SHIFT = 0, + + /* CLKSEL_CON40 */ + CLK_HDMIPHY_DIV_CON_SHIFT = 3, + CLK_HDMIPHY_DIV_CON_MASK = 0x7 << CLK_HDMIPHY_DIV_CON_SHIFT, }; #define VCO_MAX_KHZ (3200 * (MHz / KHz)) @@ -660,6 +664,16 @@ static ulong rk3328_vop_set_clk(struct rk3328_clk_priv *priv, } #endif +static ulong rk3328_hdmiphy_get_clk(struct rk3328_cru *cru) +{ + u32 div, con; + + con = readl(&cru->clksel_con[40]); + div = (con & CLK_HDMIPHY_DIV_CON_MASK) >> CLK_HDMIPHY_DIV_CON_SHIFT; + + return DIV_TO_RATE(GPLL_HZ, div); +} + static ulong rk3328_clk_get_rate(struct clk *clk) { struct rk3328_clk_priv *priv = dev_get_priv(clk->dev); @@ -689,6 +703,9 @@ static ulong rk3328_clk_get_rate(struct clk *clk) case SCLK_SPI: rate = rk3328_spi_get_clk(priv->cru); break; + case PCLK_HDMIPHY: + rate = rk3328_hdmiphy_get_clk(priv->cru); + break; default: return -ENOENT; } |