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| author | Jagan Teki <jagan@amarulasolutions.com> | 2019-07-16 17:27:36 +0530 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2019-07-21 00:00:25 +0800 |
| commit | f556d75aeda352d10d8b502056d5e22c79b063f0 (patch) | |
| tree | 5be3e2f4c2fa54898d70f43c0183b9dbadc9aa78 /drivers/clk/rockchip | |
| parent | 09565686372c8113f67662bbe0376d90c5796a1b (diff) | |
| download | u-boot-f556d75aeda352d10d8b502056d5e22c79b063f0.zip u-boot-f556d75aeda352d10d8b502056d5e22c79b063f0.tar.gz u-boot-f556d75aeda352d10d8b502056d5e22c79b063f0.tar.bz2 | |
clk: rockchip: rk3399: Set 400MHz ddr clock
Add support for setting 400MHz ddr clock.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Diffstat (limited to 'drivers/clk/rockchip')
| -rw-r--r-- | drivers/clk/rockchip/clk_rk3399.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 2c00166..d9950c1 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -839,6 +839,10 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru, dpll_cfg = (struct pll_div) {.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1}; break; + case 400 * MHz: + dpll_cfg = (struct pll_div) + {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1}; + break; case 666 * MHz: dpll_cfg = (struct pll_div) {.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1}; |