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| author | Elaine Zhang <zhangqing@rock-chips.com> | 2023-10-12 18:18:12 +0800 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2023-10-23 18:21:55 +0800 |
| commit | e4916e2c66801c2dad95dc553841f126ee2a81f9 (patch) | |
| tree | 76a89a18838a4d5c275540b68c04704a138841c4 /drivers/clk/rockchip | |
| parent | cdf21a8696a4ce6cb3103b175665fdc458b04d57 (diff) | |
| download | u-boot-e4916e2c66801c2dad95dc553841f126ee2a81f9.zip u-boot-e4916e2c66801c2dad95dc553841f126ee2a81f9.tar.gz u-boot-e4916e2c66801c2dad95dc553841f126ee2a81f9.tar.bz2 | |
clk: rockchip: rk3588: Avoid re-setting the pll rate of dclk_vop's parent
Optimize setting process.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'drivers/clk/rockchip')
| -rw-r--r-- | drivers/clk/rockchip/clk_rk3588.c | 24 |
1 files changed, 17 insertions, 7 deletions
diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c index 7ba037a..a995dd5 100644 --- a/drivers/clk/rockchip/clk_rk3588.c +++ b/drivers/clk/rockchip/clk_rk3588.c @@ -1130,13 +1130,23 @@ static ulong rk3588_dclk_vop_set_clk(struct rk3588_clk_priv *priv, } if (sel == DCLK_VOP_SRC_SEL_V0PLL) { - div = DIV_ROUND_UP(RK3588_VOP_PLL_LIMIT_FREQ, rate); - rk_clrsetreg(&cru->clksel_con[conid], - mask, - DCLK_VOP_SRC_SEL_V0PLL << sel_shift | - ((div - 1) << div_shift)); - rockchip_pll_set_rate(&rk3588_pll_clks[V0PLL], - priv->cru, V0PLL, div * rate); + pll_rate = rockchip_pll_get_rate(&rk3588_pll_clks[V0PLL], + priv->cru, V0PLL); + if (pll_rate >= RK3588_VOP_PLL_LIMIT_FREQ && pll_rate % rate == 0) { + div = DIV_ROUND_UP(pll_rate, rate); + rk_clrsetreg(&cru->clksel_con[conid], + mask, + DCLK_VOP_SRC_SEL_V0PLL << sel_shift | + ((div - 1) << div_shift)); + } else { + div = DIV_ROUND_UP(RK3588_VOP_PLL_LIMIT_FREQ, rate); + rk_clrsetreg(&cru->clksel_con[conid], + mask, + DCLK_VOP_SRC_SEL_V0PLL << sel_shift | + ((div - 1) << div_shift)); + rockchip_pll_set_rate(&rk3588_pll_clks[V0PLL], + priv->cru, V0PLL, div * rate); + } } else { for (i = 0; i <= DCLK_VOP_SRC_SEL_AUPLL; i++) { switch (i) { |