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authorJonas Karlman <jonas@kwiboo.se>2023-04-18 16:46:42 +0000
committerKever Yang <kever.yang@rock-chips.com>2023-04-21 15:55:29 +0800
commitbdbfd589745f1a7042144a222fa1e741066cc839 (patch)
treeec44ba23db3042d41686208cb6623d8ddee63a0d /drivers/clk/rockchip
parentb564aa27405f79271dfbe35b7ec5041ea46bf1d1 (diff)
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clk: rockchip: rk3588: Add limited TMCLK_EMMC clock support
The device tree sdhci node reference the TMCLK_EMMC clock, add limited support this clock to rk3588 cru driver. Fixes probe of sdhci driver. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'drivers/clk/rockchip')
-rw-r--r--drivers/clk/rockchip/clk_rk3588.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c
index 41e31b6..d0cc19b 100644
--- a/drivers/clk/rockchip/clk_rk3588.c
+++ b/drivers/clk/rockchip/clk_rk3588.c
@@ -1553,6 +1553,7 @@ static ulong rk3588_clk_get_rate(struct clk *clk)
case DCLK_DECOM:
rate = rk3588_mmc_get_clk(priv, clk->id);
break;
+ case TMCLK_EMMC:
case TCLK_WDT0:
rate = OSC_HZ;
break;
@@ -1702,6 +1703,7 @@ static ulong rk3588_clk_set_rate(struct clk *clk, ulong rate)
case DCLK_DECOM:
ret = rk3588_mmc_set_clk(priv, clk->id, rate);
break;
+ case TMCLK_EMMC:
case TCLK_WDT0:
ret = OSC_HZ;
break;