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| author | Kever Yang <kever.yang@rock-chips.com> | 2017-07-27 12:54:02 +0800 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | 2017-08-13 17:15:09 +0200 |
| commit | 217273cd441fe3d00a1bdad143dcb656854963f9 (patch) | |
| tree | 84b0975bed28db6f6f01bcf59d7d42cd23261e7d /drivers/clk/rockchip/clk_rv1108.c | |
| parent | 3a94d75d0e2a3b2519de51dfa1f369d976d9cccc (diff) | |
| download | u-boot-217273cd441fe3d00a1bdad143dcb656854963f9.zip u-boot-217273cd441fe3d00a1bdad143dcb656854963f9.tar.gz u-boot-217273cd441fe3d00a1bdad143dcb656854963f9.tar.bz2 | |
rockchip: clk: remove RATE_TO_DIV
Use DIV_ROUND_UP instead RATE_TO_DIV for all Rockchip SoC
clock driver.
Add or fix the div-field overflow check at the same time.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Diffstat (limited to 'drivers/clk/rockchip/clk_rv1108.c')
| -rw-r--r-- | drivers/clk/rockchip/clk_rv1108.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/drivers/clk/rockchip/clk_rv1108.c b/drivers/clk/rockchip/clk_rv1108.c index 818293d..cf966bb 100644 --- a/drivers/clk/rockchip/clk_rv1108.c +++ b/drivers/clk/rockchip/clk_rv1108.c @@ -25,9 +25,6 @@ enum { OUTPUT_MIN_HZ = 24 * 1000000, }; -#define RATE_TO_DIV(input_rate, output_rate) \ - ((input_rate) / (output_rate) - 1); - #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ |