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author | Hai Pham <hai.pham.ud@renesas.com> | 2020-08-11 10:46:34 +0700 |
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committer | Marek Vasut <marek.vasut+renesas@gmail.com> | 2021-06-24 20:22:17 +0200 |
commit | b092f96290539d98ebd2e9c159de8035a8142842 (patch) | |
tree | 31b3de3e37aa3115a71e06ee274fafddbbef4280 /drivers/clk/renesas/renesas-cpg-mssr.c | |
parent | 44c78aa7ac0f4b22491350278f0dd77585416248 (diff) | |
download | u-boot-b092f96290539d98ebd2e9c159de8035a8142842.zip u-boot-b092f96290539d98ebd2e9c159de8035a8142842.tar.gz u-boot-b092f96290539d98ebd2e9c159de8035a8142842.tar.bz2 |
clk: renesas: Add R8A779A0 clock tables
Add clock tables for R8A779A0 V3U SoC from Linux 5.12,
commit 9f4ad9e425a1 ("Linux 5.12")
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
--
Marek: - Add .reset_modemr_offset
- Sync tables from Linux 5.12
- Rebase on latest u-boot
Diffstat (limited to 'drivers/clk/renesas/renesas-cpg-mssr.c')
-rw-r--r-- | drivers/clk/renesas/renesas-cpg-mssr.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c index b1cf7f5..e0895d2 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -127,6 +127,10 @@ int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info) clrsetbits_le32(base + info->control_regs[i], info->mstp_table[i].sdis, info->mstp_table[i].sen); + + if (info->reg_layout == CLK_REG_LAYOUT_RCAR_V3U) + continue; + clrsetbits_le32(base + RMSTPCR(i), info->mstp_table[i].rdis, info->mstp_table[i].ren); |