From b092f96290539d98ebd2e9c159de8035a8142842 Mon Sep 17 00:00:00 2001 From: Hai Pham Date: Tue, 11 Aug 2020 10:46:34 +0700 Subject: clk: renesas: Add R8A779A0 clock tables Add clock tables for R8A779A0 V3U SoC from Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") Signed-off-by: Hai Pham Signed-off-by: Marek Vasut -- Marek: - Add .reset_modemr_offset - Sync tables from Linux 5.12 - Rebase on latest u-boot --- drivers/clk/renesas/renesas-cpg-mssr.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/clk/renesas/renesas-cpg-mssr.c') diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c index b1cf7f5..e0895d2 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -127,6 +127,10 @@ int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info) clrsetbits_le32(base + info->control_regs[i], info->mstp_table[i].sdis, info->mstp_table[i].sen); + + if (info->reg_layout == CLK_REG_LAYOUT_RCAR_V3U) + continue; + clrsetbits_le32(base + RMSTPCR(i), info->mstp_table[i].rdis, info->mstp_table[i].ren); -- cgit v1.1