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author | Simon Glass <sjg@chromium.org> | 2020-02-06 09:54:53 -0700 |
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committer | Bin Meng <bmeng.cn@gmail.com> | 2020-02-07 22:41:24 +0800 |
commit | b4d00b256e3c784de4a33a40f4cd28a94ee2a80c (patch) | |
tree | 9b343b145b5bcf6471c3efa513ca8c9314b430e4 /drivers/clk/intel/clk_intel.c | |
parent | fdec36f248c0508ab5d001ad65c38f413638b4a2 (diff) | |
download | u-boot-b4d00b256e3c784de4a33a40f4cd28a94ee2a80c.zip u-boot-b4d00b256e3c784de4a33a40f4cd28a94ee2a80c.tar.gz u-boot-b4d00b256e3c784de4a33a40f4cd28a94ee2a80c.tar.bz2 |
x86: Add a clock driver for Intel devices
So far we have avoided adding a clock driver for Intel devices. But the
Designware I2C driver needs a different clock (133MHz) on Intel devices
than on others (166MHz). Add a simple driver that provides this
information.
This driver can be expanded later as needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'drivers/clk/intel/clk_intel.c')
-rw-r--r-- | drivers/clk/intel/clk_intel.c | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/drivers/clk/intel/clk_intel.c b/drivers/clk/intel/clk_intel.c new file mode 100644 index 0000000..d2e1549 --- /dev/null +++ b/drivers/clk/intel/clk_intel.c @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 Google LLC + * Written by Simon Glass <sjg@chromium.org> + */ + +#include <common.h> +#include <dm.h> +#include <clk-uclass.h> +#include <dt-bindings/clock/intel-clock.h> + +static ulong intel_clk_get_rate(struct clk *clk) +{ + ulong rate; + + switch (clk->id) { + case CLK_I2C: + /* Hard-coded to 133MHz on current platforms */ + return 133333333; + default: + return -ENODEV; + } + + return rate; +} + +static struct clk_ops intel_clk_ops = { + .get_rate = intel_clk_get_rate, +}; + +static const struct udevice_id intel_clk_ids[] = { + { .compatible = "intel,apl-clk" }, + { } +}; + +U_BOOT_DRIVER(clk_intel) = { + .name = "clk_intel", + .id = UCLASS_CLK, + .of_match = intel_clk_ids, + .ops = &intel_clk_ops, +}; |