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| author | Patrick Delaunay <patrick.delaunay@foss.st.com> | 2021-10-11 09:52:50 +0200 |
|---|---|---|
| committer | Patrice Chotard <patrice.chotard@foss.st.com> | 2021-11-10 17:07:31 +0100 |
| commit | f42045b2e75036330741c3fd3a1b5ca64867aaa0 (patch) | |
| tree | a227d4c2c942ff3cf531fd919cd2ec5df93ee203 /drivers/clk/clk_stm32mp1.c | |
| parent | 17aeb589fa9ddb70acaef069732746c4d8fb4021 (diff) | |
| download | u-boot-f42045b2e75036330741c3fd3a1b5ca64867aaa0.zip u-boot-f42045b2e75036330741c3fd3a1b5ca64867aaa0.tar.gz u-boot-f42045b2e75036330741c3fd3a1b5ca64867aaa0.tar.bz2 | |
stm32mp15: replace CONFIG_TFABOOT when it is possible
In some part of STM32MP15 support the CONFIG_TFABOOT can be replaced
by other config: CONFIG_ARMV7_PSCI and CONFIG_ARM_SMCCC.
This patch also simplifies the code in cpu.c, stm32mp1_ram.c and
clk_stml32mp1.c as execution of U-Boot in sysram (boot without SPL and
without TFA) is not supported: the associated initialization code is
present only in SPL.
This cleanup patch is a preliminary step to support SPL load of OP-TEE
in secure world, with SPL in secure world and U-Boot in no-secure world.
Reported-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Diffstat (limited to 'drivers/clk/clk_stm32mp1.c')
| -rw-r--r-- | drivers/clk/clk_stm32mp1.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c index 114192b..83ab6b7 100644 --- a/drivers/clk/clk_stm32mp1.c +++ b/drivers/clk/clk_stm32mp1.c @@ -27,12 +27,10 @@ DECLARE_GLOBAL_DATA_PTR; -#ifndef CONFIG_TFABOOT -#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SPL_BUILD) /* activate clock tree initialization in the driver */ #define STM32MP1_CLOCK_TREE_INIT #endif -#endif #define MAX_HSI_HZ 64000000 |