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authorTom Rini <trini@konsulko.com>2019-05-13 07:13:03 -0400
committerTom Rini <trini@konsulko.com>2019-05-13 07:13:03 -0400
commitd2d8f73da4b648ad21b1afb481f0bcd035ebe029 (patch)
tree9f42385dcb5d164577b972664fcf63b557a50503 /doc
parent592254b9b8bde7c1844d956fe3ba3dd78f5df054 (diff)
parent1b898ffc040b5977a07af755b8ba3aa151914800 (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-socfpga
- A10 FPGA programming support, Gen5 livetree conversion
Diffstat (limited to 'doc')
-rw-r--r--doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt26
1 files changed, 25 insertions, 1 deletions
diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
index 2fd8e7a..da210bf 100644
--- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
+++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
@@ -7,8 +7,31 @@ Required properties:
- The second index is for writing FPGA configuration data.
- resets : Phandle and reset specifier for the device's reset.
- clocks : Clocks used by the device.
+- altr,bitstream : Fit image file name for both FPGA peripheral bitstream,
+ FPGA core bitstream and full bitstream.
-Example:
+ Full bitstream, consist of peripheral bitstream and core
+ bitstream.
+
+ FPGA peripheral bitstream is used to initialize FPGA IOs,
+ PLL, IO48 and DDR. This bitstream is required to get DDR up
+ running.
+
+ FPGA core bitstream contains FPGA design which is used to
+ program FPGA CRAM and ERAM.
+
+Example: Bundles both peripheral bitstream and core bitstream into FIT image
+ called fit_spl_fpga.itb. This FIT image can be created through running
+ this command: tools/mkimage
+ -E -p 400
+ -f board/altera/arria10-socdk/fit_spl_fpga.its
+ fit_spl_fpga.itb
+
+ For details of describing structure and contents of the FIT image,
+ please refer board/altera/arria10-socdk/fit_spl_fpga.its
+
+- Examples for booting with full release or booting with early IO release, then
+ follow by entering early user mode:
fpga_mgr: fpga-mgr@ffd03000 {
compatible = "altr,socfpga-a10-fpga-mgr";
@@ -16,4 +39,5 @@ Example:
0xffcfe400 0x20>;
clocks = <&l4_mp_clk>;
resets = <&rst FPGAMGR_RESET>;
+ altr,bitstream = "fit_spl_fpga.itb";
};