diff options
| author | Adrian Fiergolski <adrian.fiergolski@fastree3d.com> | 2022-07-22 17:16:14 +0300 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2022-07-26 09:34:21 +0200 |
| commit | b524f8fb1e94a8e649ba06a7cb87e6dcaa96ebc3 (patch) | |
| tree | 11c1dfb7b63801bf0686162c7a079fd8ab0e668b /doc | |
| parent | a3a1afb747d4d71c3dd5ba01b2796cebd65c65cd (diff) | |
| download | u-boot-b524f8fb1e94a8e649ba06a7cb87e6dcaa96ebc3.zip u-boot-b524f8fb1e94a8e649ba06a7cb87e6dcaa96ebc3.tar.gz u-boot-b524f8fb1e94a8e649ba06a7cb87e6dcaa96ebc3.tar.bz2 | |
fpga: zynqmp: support loading encrypted bitfiles
Add supporting new compatible string "u-boot,zynqmp-fpga-enc" to
handle loading encrypted bitfiles.
This feature requires encrypted FSBL, as according to UG1085:
"The CSU automatically locks out the AES key, stored in either BBRAM
or eFUSEs, as a key source to the AES engine if the FSBL is not
encrypted. This prevents using the BBRAM or eFUSE as the key source
to the AES engine during run-time applications."
Signed-off-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com>
Co-developed-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Tested-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com>
Link: https://lore.kernel.org/r/20220722141614.297383-14-oleksandr.suvorov@foundries.io
Signed-off-by: Michal Simek <michal.simek@amd.com>
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/uImage.FIT/source_file_format.txt | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/doc/uImage.FIT/source_file_format.txt b/doc/uImage.FIT/source_file_format.txt index 461e2af..6870111 100644 --- a/doc/uImage.FIT/source_file_format.txt +++ b/doc/uImage.FIT/source_file_format.txt @@ -188,6 +188,8 @@ the '/images' node should have the following layout: "u-boot,fpga-legacy" - the generic fpga loading routine. "u-boot,zynqmp-fpga-ddrauth" - signed non-encrypted FPGA bitstream for Xilinx Zynq UltraScale+ (ZymqMP) device. + "u-boot,zynqmp-fpga-enc" - encrypted FPGA bitstream for Xilinx Zynq + UltraScale+ (ZynqMP) device. Optional nodes: - hash-1 : Each hash sub-node represents separate hash or checksum |