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author | Stefan Roese <sr@denx.de> | 2007-06-25 15:57:39 +0200 |
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committer | Stefan Roese <sr@denx.de> | 2007-06-25 15:57:39 +0200 |
commit | 466fff1a7bb5fe764a06450626f6098219f446b8 (patch) | |
tree | ea3d101e2103afb8d6f16c78a8809cef1c095a46 /doc | |
parent | 6f35c53166213c24a5a0e2390ed861136ff73870 (diff) | |
download | u-boot-466fff1a7bb5fe764a06450626f6098219f446b8.zip u-boot-466fff1a7bb5fe764a06450626f6098219f446b8.tar.gz u-boot-466fff1a7bb5fe764a06450626f6098219f446b8.tar.bz2 |
ppc4xx: Add pci_pre_init() for 405 boards
This patch removes the CFG_PCI_PRE_INIT option completely, since
it's not needed anymore with the patch from Matthias Fuchs with
the "weak" pci_pre_init() implementation.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'doc')
-rw-r--r-- | doc/README.ppc440 | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/doc/README.ppc440 b/doc/README.ppc440 index 08f34f5..2e04aba 100644 --- a/doc/README.ppc440 +++ b/doc/README.ppc440 @@ -146,12 +146,13 @@ that maps in a single PCI I/O space and PCI memory space. The I/O space begins at PCI I/O address 0 and the PCI memory space is 256 MB starting at PCI address CFG_PCI_TARGBASE. After the pci_controller structure is initialized, the cpu-specific code will -call the routine pci_pre_init() if the CFG_PCI_PRE_INIT flag is -defined. This routine is implemented by board-specific code & is where -the board can over-ride/extend the default pci_controller structure -settings and do other pre-initialization tasks. If pci_pre_init() -returns a value of zero, PCI initialization is aborted; otherwise the -controller structure is registered and initialization continues. +call the routine pci_pre_init(). This routine is implemented by +board-specific code & is where the board can over-ride/extend the +default pci_controller structure settings and exspecially provide +a routine to map the PCI interrupts and do other pre-initialization +tasks. If pci_pre_init() returns a value of zero, PCI initialization +is aborted; otherwise the controller structure is registered and +initialization continues. The default 440GP PCI target configuration is minimal -- it assumes that the strapping registers are set as necessary. Since the strapping bits |