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| author | Tom Rini <trini@konsulko.com> | 2022-11-16 13:10:41 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-12-05 16:06:08 -0500 |
| commit | 65cc0e2a65d2c9f107b2f42db6396d9ade6c5ad8 (patch) | |
| tree | e1b9902c5257875fc5fe8243e1e759594f90beed /doc/README.mpc85xx | |
| parent | a322afc9f9b69dd52a9bc72937cd5adc18ea55c7 (diff) | |
| download | u-boot-65cc0e2a65d2c9f107b2f42db6396d9ade6c5ad8.zip u-boot-65cc0e2a65d2c9f107b2f42db6396d9ade6c5ad8.tar.gz u-boot-65cc0e2a65d2c9f107b2f42db6396d9ade6c5ad8.tar.bz2 | |
global: Move remaining CONFIG_SYS_* to CFG_SYS_*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do
not easily transition to Kconfig. In many cases they likely should come
from the device tree instead. Move these out of CONFIG namespace and in
to CFG namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'doc/README.mpc85xx')
| -rw-r--r-- | doc/README.mpc85xx | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/doc/README.mpc85xx b/doc/README.mpc85xx index 3c6ebbd..bafffe6 100644 --- a/doc/README.mpc85xx +++ b/doc/README.mpc85xx @@ -59,13 +59,13 @@ A) defined(CONFIG_SYS_RAMBOOT) i.e. SD, SPI, NAND RAMBOOT & NAND_SPL boot 3) TLB entry for the stack during AS1 Location : Lable "create_init_ram_area" TLB Entry : 14 - EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR + EPN -->RPN : CFG_SYS_INIT_RAM_ADDR --> CFG_SYS_INIT_RAM_ADDR Properties : 16K, AS1, IPROT 4) TLB entry for CCSRBAR during AS1 execution Location : cpu_init_early_f TLB Entry : 13 - EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR + EPN -->RPN : CFG_SYS_CCSRBAR --> CFG_SYS_CCSRBAR Properties : 1M, AS1, I, G 5) Invalidate unproctected TLB Entries @@ -84,7 +84,7 @@ A) defined(CONFIG_SYS_RAMBOOT) i.e. SD, SPI, NAND RAMBOOT & NAND_SPL boot 8) Update Flash's TLB entry Location : Board_init_r TLB entry : Search from TLB entries - EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS + EPN -->RPN : CFG_SYS_FLASH_BASE --> CFG_SYS_FLASH_BASE_PHYS Properties : Board specific size, AS0, I, G, IPROT @@ -94,7 +94,7 @@ B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot Location : Label "_start" TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB #if defined(CONFIG_NXP_ESBC) - EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW + EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CFG_SYS_PBI_FLASH_WINDOW Properties : 1M, AS1, I, G, IPROT #else EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000 @@ -105,7 +105,7 @@ B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot Location : Label "create_init_ram_area" TLB Entry : 15 #if defined(CONFIG_NXP_ESBC) - EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW + EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CFG_SYS_PBI_FLASH_WINDOW Properties : 1M, AS1, I, G, IPROT #else EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000 @@ -115,13 +115,13 @@ B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot 3) TLB entry for the stack during AS1 Location : Lable "create_init_ram_area" TLB Entry : 14 - EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR + EPN -->RPN : CFG_SYS_INIT_RAM_ADDR --> CFG_SYS_INIT_RAM_ADDR Properties : 16K, AS1, IPROT 4) TLB entry for CCSRBAR during AS1 execution Location : cpu_init_early_f TLB Entry : 13 - EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR + EPN -->RPN : CFG_SYS_CCSRBAR --> CFG_SYS_CCSRBAR Properties : 1M, AS1, I, G 5) TLB entry for Errata workaround CONFIG_SYS_FSL_ERRATUM_IFC_A003399 @@ -162,5 +162,5 @@ B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot 12) Update Flash's TLB entry Location : Board_init_r TLB entry : Search from TLB entries - EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS + EPN -->RPN : CFG_SYS_FLASH_BASE --> CFG_SYS_FLASH_BASE_PHYS Properties : Board specific size, AS0, I, G, IPROT |