Initial support for MPC8641 HPCN board.

13 files changed, 4699 insertions, 0 deletions

diff --git a/cpu/mpc86xx/Makefile b/cpu/mpc86xx/Makefile
new file mode 100644
index 0000000..0dd099d
--- /dev/null
+++ b/cpu/mpc86xx/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2002,2003 Motorola Inc.
+# Xianghua Xiao,X.Xiao@motorola.com
+#
+# (C) Copyright 2004 Freescale Semiconductor. (MC86xx Port)
+# Jeff Brown (Jeffrey@freescale.com)
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(CPU).a
+
+START	= start.o #resetvec.o
+ASOBJS  = cache.o 
+COBJS	= traps.o cpu.o cpu_init.o speed.o interrupts.o \
+	  pci.o i2c.o spd_sdram.o 
+OBJS	= $(COBJS)
+
+all:	.depend $(START) $(ASOBJS) $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) crv $@ $(ASOBJS) $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(START:.o=.S) $(ASOBJS:.o=.S) $(COBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(START:.o=.S) $(ASOBJS:.o=.S) $(COBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/cpu/mpc86xx/cache.S b/cpu/mpc86xx/cache.S
new file mode 100644
index 0000000..75186b1
--- /dev/null
+++ b/cpu/mpc86xx/cache.S
@@ -0,0 +1,368 @@
+#include <config.h>
+#include <mpc86xx.h>
+#include <version.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#ifndef CACHE_LINE_SIZE
+# define CACHE_LINE_SIZE L1_CACHE_BYTES
+#endif
+
+#if CACHE_LINE_SIZE == 128
+#define LG_CACHE_LINE_SIZE 7
+#elif CACHE_LINE_SIZE == 32
+#define LG_CACHE_LINE_SIZE 5
+#elif CACHE_LINE_SIZE == 16
+#define LG_CACHE_LINE_SIZE 4
+#elif CACHE_LINE_SIZE == 8
+#define LG_CACHE_LINE_SIZE 3
+#else
+# error "Invalid cache line size!"
+#endif
+
+/*
+ * Most of this code is taken from 74xx_7xx/cache.S
+ * and then cleaned up a bit
+ */
+	
+/*
+ * Invalidate L1 instruction cache.
+ */
+_GLOBAL(invalidate_l1_instruction_cache)
+	/* use invalidate-all bit in HID0 */
+	mfspr	r3,HID0
+	ori	r3,r3,HID0_ICFI
+	mtspr	HID0,r3
+	isync
+	blr
+
+/*
+ * Invalidate L1 data cache.
+ */
+_GLOBAL(invalidate_l1_data_cache)
+	mfspr	r3,HID0
+	ori	r3,r3,HID0_DCFI
+	mtspr	HID0,r3
+	isync
+	blr
+
+/*
+ * Flush data cache.
+ */
+_GLOBAL(flush_data_cache)
+	lis	r3,0
+	lis	r5,CACHE_LINE_SIZE
+flush:
+	cmp	0,1,r3,r5
+	bge	done
+	lwz	r5,0(r3)
+	lis	r5,CACHE_LINE_SIZE
+	addi	r3,r3,0x4
+	b	flush
+done:
+	blr
+/*
+ * Write any modified data cache blocks out to memory
+ * and invalidate the corresponding instruction cache blocks.
+ * This is a no-op on the 601.
+ *
+ * flush_icache_range(unsigned long start, unsigned long stop)
+ */
+_GLOBAL(flush_icache_range)
+	li	r5,CACHE_LINE_SIZE-1
+	andc	r3,r3,r5
+	subf	r4,r3,r4
+	add	r4,r4,r5
+	srwi.	r4,r4,LG_CACHE_LINE_SIZE
+	beqlr
+	mtctr	r4
+	mr	r6,r3
+1:	dcbst	0,r3
+	addi	r3,r3,CACHE_LINE_SIZE
+	bdnz	1b
+	sync				/* wait for dcbst's to get to ram */
+	mtctr	r4
+2:	icbi	0,r6
+	addi	r6,r6,CACHE_LINE_SIZE
+	bdnz	2b
+	sync				/* additional sync needed on g4 */
+	isync
+	blr
+/*
+ * Write any modified data cache blocks out to memory.
+ * Does not invalidate the corresponding cache lines (especially for
+ * any corresponding instruction cache).
+ *
+ * clean_dcache_range(unsigned long start, unsigned long stop)
+ */
+_GLOBAL(clean_dcache_range)
+	li	r5,CACHE_LINE_SIZE-1
+	andc	r3,r3,r5	/* align r3 down to cache line */
+	subf	r4,r3,r4	/* r4 = offset of stop from start of cache line */
+	add	r4,r4,r5	/* r4 += cache_line_size-1 */
+	srwi.	r4,r4,LG_CACHE_LINE_SIZE  /* r4 = number of cache lines to flush */
+	beqlr				  /* if r4 == 0 return */
+	mtctr	r4			  /* ctr = r4 */
+
+	sync
+1:	dcbst	0,r3
+	addi	r3,r3,CACHE_LINE_SIZE
+	bdnz	1b
+	sync				/* wait for dcbst's to get to ram */
+	blr
+
+/*
+ * Write any modified data cache blocks out to memory
+ * and invalidate the corresponding instruction cache blocks.
+ *
+ * flush_dcache_range(unsigned long start, unsigned long stop)
+ */
+_GLOBAL(flush_dcache_range)
+	li	r5,CACHE_LINE_SIZE-1
+	andc	r3,r3,r5
+	subf	r4,r3,r4
+	add	r4,r4,r5
+	srwi.	r4,r4,LG_CACHE_LINE_SIZE
+	beqlr
+	mtctr	r4
+
+	sync
+1:	dcbf	0,r3
+	addi	r3,r3,CACHE_LINE_SIZE
+	bdnz	1b
+	sync				/* wait for dcbf's to get to ram */
+	blr
+
+/*
+ * Like above, but invalidate the D-cache.  This is used by the 8xx
+ * to invalidate the cache so the PPC core doesn't get stale data
+ * from the CPM (no cache snooping here :-).
+ *
+ * invalidate_dcache_range(unsigned long start, unsigned long stop)
+ */
+_GLOBAL(invalidate_dcache_range)
+	li	r5,CACHE_LINE_SIZE-1
+	andc	r3,r3,r5
+	subf	r4,r3,r4
+	add	r4,r4,r5
+	srwi.	r4,r4,LG_CACHE_LINE_SIZE
+	beqlr
+	mtctr	r4
+
+	sync
+1:	dcbi	0,r3
+	addi	r3,r3,CACHE_LINE_SIZE
+	bdnz	1b
+	sync				/* wait for dcbi's to get to ram */
+	blr
+
+/*
+ * Flush a particular page from the data cache to RAM.
+ * Note: this is necessary because the instruction cache does *not*
+ * snoop from the data cache.
+ *
+ *	void __flush_page_to_ram(void *page)
+ */
+_GLOBAL(__flush_page_to_ram)
+	rlwinm	r3,r3,0,0,19		/* Get page base address */
+	li	r4,4096/CACHE_LINE_SIZE	/* Number of lines in a page */
+	mtctr	r4
+	mr	r6,r3
+0:	dcbst	0,r3			/* Write line to ram */
+	addi	r3,r3,CACHE_LINE_SIZE
+	bdnz	0b
+	sync
+	mtctr	r4
+1:	icbi	0,r6
+	addi	r6,r6,CACHE_LINE_SIZE
+	bdnz	1b
+	sync
+	isync
+	blr
+
+/*
+ * Flush a particular page from the instruction cache.
+ * Note: this is necessary because the instruction cache does *not*
+ * snoop from the data cache.
+ *
+ *	void __flush_icache_page(void *page)
+ */
+_GLOBAL(__flush_icache_page)
+	li	r4,4096/CACHE_LINE_SIZE	/* Number of lines in a page */
+	mtctr	r4
+1:	icbi	0,r3
+	addi	r3,r3,CACHE_LINE_SIZE
+	bdnz	1b
+	sync
+	isync
+	blr
+
+/*
+ * Clear a page using the dcbz instruction, which doesn't cause any
+ * memory traffic (except to write out any cache lines which get
+ * displaced).  This only works on cacheable memory.
+ */
+_GLOBAL(clear_page)
+	li	r0,4096/CACHE_LINE_SIZE
+	mtctr	r0
+1:	dcbz	0,r3
+	addi	r3,r3,CACHE_LINE_SIZE
+	bdnz	1b
+	blr
+
+/*
+ * Enable L1 Instruction cache
+ */
+_GLOBAL(icache_enable)
+	mfspr	r3, HID0
+	li	r5, HID0_ICFI|HID0_ILOCK
+	andc	r3, r3, r5
+	ori	r3, r3, HID0_ICE
+	ori	r5, r3, HID0_ICFI
+	mtspr	HID0, r5
+	mtspr	HID0, r3
+	isync
+	blr
+
+/*
+ * Disable L1 Instruction cache
+ */
+_GLOBAL(icache_disable)
+	mfspr	r3, HID0
+	li	r5, 0
+	ori	r5, r5, HID0_ICE
+	andc	r3, r3, r5
+	mtspr	HID0, r3
+	isync
+	blr
+
+/*
+ * Is instruction cache enabled?
+ */
+_GLOBAL(icache_status)
+	mfspr	r3, HID0
+	andi.	r3, r3, HID0_ICE
+	blr
+
+
+_GLOBAL(l1dcache_enable)
+	mfspr	r3, HID0
+	li	r5, HID0_DCFI|HID0_DLOCK
+	andc	r3, r3, r5
+	mtspr	HID0, r3		/* no invalidate, unlock */
+	ori	r3, r3, HID0_DCE
+	ori	r5, r3, HID0_DCFI
+	mtspr	HID0, r5		/* enable + invalidate */
+	mtspr	HID0, r3		/* enable */
+	sync
+	blr
+
+/*
+ * Enable data cache(s) - L1 and optionally L2
+ * Calls l2cache_enable. LR saved in r5
+ */
+_GLOBAL(dcache_enable)
+	mfspr	r3, HID0
+	li	r5, HID0_DCFI|HID0_DLOCK
+	andc	r3, r3, r5
+	mtspr	HID0, r3		/* no invalidate, unlock */
+	ori	r3, r3, HID0_DCE
+	ori	r5, r3, HID0_DCFI
+	mtspr	HID0, r5		/* enable + invalidate */
+	mtspr	HID0, r3		/* enable */
+	sync
+#ifdef CFG_L2
+	mflr	r5
+	bl	l2cache_enable		/* uses r3 and r4 */
+	sync
+	mtlr	r5
+#endif
+	blr
+
+
+/*
+ * Disable data cache(s) - L1 and optionally L2
+ * Calls flush_data_cache and l2cache_disable_no_flush.
+ * LR saved in r4
+ */
+_GLOBAL(dcache_disable)
+	mflr	r4			/* save link register */
+	bl	flush_data_cache	/* uses r3 and r5 */
+	sync
+	mfspr	r3, HID0
+	li	r5, HID0_DCFI|HID0_DLOCK
+	andc	r3, r3, r5
+	mtspr	HID0, r3		/* no invalidate, unlock */
+	li	r5, HID0_DCE|HID0_DCFI
+	andc	r3, r3, r5		/* no enable, no invalidate */
+	mtspr	HID0, r3
+	sync
+#ifdef CFG_L2
+	bl	l2cache_disable_no_flush /* uses r3 */
+#endif
+	mtlr	r4			/* restore link register */
+	blr
+
+/*
+ * Is data cache enabled?
+ */
+_GLOBAL(dcache_status)
+	mfspr	r3, HID0
+	andi.	r3, r3, HID0_DCE
+	blr
+
+/*
+ * Invalidate L2 cache using L2I and polling L2IP
+ */
+_GLOBAL(l2cache_invalidate)
+	sync
+	oris	r3, r3, L2CR_L2I@h
+	sync
+	mtspr	l2cr, r3
+	sync
+invl2:
+	mfspr	r3, l2cr
+	andi.	r3, r3, L2CR_L2IP
+	bne	invl2
+	/* turn off the global invalidate bit */
+	mfspr	r3, l2cr
+	rlwinm	r3, r3, 0, 11, 9
+	sync
+	mtspr	l2cr, r3
+	sync
+	blr
+
+/*
+ * Enable L2 cache
+ * Calls l2cache_invalidate. LR is saved in r4
+ */
+_GLOBAL(l2cache_enable)
+	mflr	r4			/* save link register */
+	bl	l2cache_invalidate	/* uses r3 */
+	sync
+	lis	r3, L2_ENABLE@h
+	ori	r3, r3, L2_ENABLE@l
+	mtspr	l2cr, r3
+	isync
+	mtlr	r4			/* restore link register */
+	blr
+
+/*
+ * Disable L2 cache
+ * Calls flush_data_cache. LR is saved in r4
+ */
+_GLOBAL(l2cache_disable)
+	mflr	r4			/* save link register */
+	bl	flush_data_cache	/* uses r3 and r5 */
+	sync
+	mtlr	r4			/* restore link register */
+l2cache_disable_no_flush:		/* provide way to disable L2 w/o flushing */
+	lis	r3, L2_INIT@h
+	ori	r3, r3, L2_INIT@l
+	mtspr	l2cr, r3
+	isync
+	blr
diff --git a/cpu/mpc86xx/config.mk b/cpu/mpc86xx/config.mk
new file mode 100644
index 0000000..4ef7ace
--- /dev/null
+++ b/cpu/mpc86xx/config.mk
@@ -0,0 +1,26 @@
+#
+# (C) Copyright 2004 Freescale Semiconductor.
+# Jeff Brown <jeffrey@freescale.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
+
+PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx -ffixed-r2 -ffixed-r29 -mstring
\ No newline at end of file
diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c
new file mode 100644
index 0000000..b0fe8ab
--- /dev/null
+++ b/cpu/mpc86xx/cpu.c
@@ -0,0 +1,669 @@
+/*
+ * Copyright 2004 Freescale Semiconductor
+ * Jeff Brown (jeffrey@freescale.com)
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <command.h>
+#include <asm/cache.h>
+#include <mpc86xx.h>
+
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+#endif
+
+
+// SS: For debug only, remove after use
+
+static __inline__ unsigned long get_dbat3u (void)
+{
+   unsigned long dbat3u;
+   asm volatile("mfspr %0, 542" : "=r" (dbat3u) :);
+   return dbat3u;
+}
+
+static __inline__ unsigned long get_dbat3l (void)
+{
+   unsigned long dbat3l;
+   asm volatile("mfspr %0, 543" : "=r" (dbat3l) :);
+   return dbat3l;
+}
+
+static __inline__ unsigned long get_msr (void)
+{
+   unsigned long msr;
+   asm volatile("mfmsr %0" : "=r" (msr) :);
+   return msr;
+}
+
+extern unsigned long get_board_sys_clk(ulong dummy);
+
+int checkcpu (void)
+{
+	sys_info_t sysinfo;
+	uint pvr, svr;
+	uint ver;
+	uint major, minor;
+	uint lcrr;		/* local bus clock ratio register */
+	uint clkdiv;		/* clock divider portion of lcrr */
+	
+	puts("Freescale PowerPC\n");
+
+	pvr = get_pvr();
+	ver = PVR_VER(pvr);
+	major = PVR_MAJ(pvr);
+	minor = PVR_MIN(pvr);
+
+	puts ("CPU:\n");
+
+	printf("    Core: ");
+	
+	switch (ver) {
+	case PVR_VER(PVR_86xx):
+	    puts("E600");
+	    break;
+	default:
+	    puts("Unknown");
+	    break;
+	}
+	printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
+
+	svr = get_svr();
+	ver = SVR_VER(svr);
+	major = SVR_MAJ(svr);
+	minor = SVR_MIN(svr);
+
+	puts("    System: ");
+	switch (ver) {	
+	case SVR_8641:
+	        puts("8641");
+	        break;
+	case SVR_8641D:
+		puts("8641D");
+		break;
+	default:
+		puts("Unknown");
+		break;
+	}
+	printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
+
+	get_sys_info(&sysinfo);
+
+	puts("    Clocks: ");
+	printf("CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
+	printf("MPX:%4lu MHz, ", sysinfo.freqSystemBus / 1000000);
+	printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000);
+        	
+#if defined(CFG_LBC_LCRR)
+	lcrr = CFG_LBC_LCRR;
+#else
+	{
+	    volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	    volatile ccsr_lbc_t *lbc= &immap->im_lbc;
+
+	    lcrr = lbc->lcrr;
+	}
+#endif
+	clkdiv = lcrr & 0x0f;
+	if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
+		printf("LBC:%4lu MHz\n",
+		       sysinfo.freqSystemBus / 1000000 / clkdiv);
+	} else {
+		printf("    LBC: unknown (lcrr: 0x%08x)\n", lcrr);
+	}
+
+        printf("    L2: ");
+        if (get_l2cr() & 0x80000000)
+           printf("Enabled\n");
+        else
+           printf("Disabled\n");
+        
+	return (0);
+}
+
+
+/* -------------------------------------------------------------------- */
+
+static inline void
+soft_restart(unsigned long addr)
+{
+
+#ifndef CONFIG_MPC8641HPCN
+   
+	/* SRR0 has system reset vector, SRR1 has default MSR value */
+	/* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
+
+	__asm__ __volatile__ ("mtspr	26, %0"		:: "r" (addr));
+	__asm__ __volatile__ ("li	4, (1 << 6)"	::: "r4");
+	__asm__ __volatile__ ("mtspr	27, 4");
+	__asm__ __volatile__ ("rfi");
+
+#else /* CONFIG_MPC8641HPCN */
+        out8(PIXIS_BASE+PIXIS_RST,0);
+#endif /* !CONFIG_MPC8641HPCN */
+	while(1);	/* not reached */
+}
+
+
+
+#ifdef CONFIG_MPC8641HPCN
+
+int set_px_sysclk(ulong sysclk)
+{
+         u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux,tmp;
+
+         /* Per table 27, page 58 of MPC8641HPCN spec*/
+         switch(sysclk)
+         {
+            case 33:
+               sysclk_s = 0x04;
+               sysclk_r = 0x04;
+               sysclk_v = 0x07;
+               sysclk_aux = 0x00;
+               break;
+            case 40:
+               sysclk_s = 0x01;
+               sysclk_r = 0x1F;
+               sysclk_v = 0x20;
+               sysclk_aux = 0x01;
+               break;
+            case 50:
+               sysclk_s = 0x01;
+               sysclk_r = 0x1F;
+               sysclk_v = 0x2A;
+               sysclk_aux = 0x02;
+               break;
+            case 66:
+               sysclk_s = 0x01;
+               sysclk_r = 0x04;
+               sysclk_v = 0x04;
+               sysclk_aux = 0x03;
+               break;
+            case 83:
+               sysclk_s = 0x01;
+               sysclk_r = 0x1F;
+               sysclk_v = 0x4B;
+               sysclk_aux = 0x04;
+               break;
+            case 100:
+               sysclk_s = 0x01;
+               sysclk_r = 0x1F;
+               sysclk_v = 0x5C;
+               sysclk_aux = 0x05;
+               break;
+            case 134:
+               sysclk_s = 0x06;
+               sysclk_r = 0x1F;
+               sysclk_v = 0x3B;
+              sysclk_aux = 0x06; 
+               break;
+            case 166:
+               sysclk_s = 0x06;
+               sysclk_r = 0x1F;
+               sysclk_v = 0x4B;
+               sysclk_aux = 0x07;
+               break;
+            default:
+               printf("Unsupported SYSCLK frequency.\n");
+               return 0;
+         }
+         
+         vclkh = (sysclk_s << 5) | sysclk_r ;
+         vclkl = sysclk_v;
+         out8(PIXIS_BASE+PIXIS_VCLKH,vclkh);
+         out8(PIXIS_BASE+PIXIS_VCLKL,vclkl);
+
+         out8(PIXIS_BASE+PIXIS_AUX,sysclk_aux);
+         
+         return 1;
+}
+
+int set_px_mpxpll(ulong mpxpll)
+{
+         u8 tmp;
+         u8 val;
+         switch(mpxpll)
+         {
+            case 2:
+            case 4:
+            case 6:
+            case 8:
+            case 10:
+            case 12:
+            case 14:
+            case 16:
+               val = (u8)mpxpll;
+               break;
+            default:
+               printf("Unsupported MPXPLL ratio.\n");
+               return 0;
+         }
+
+         tmp = in8(PIXIS_BASE+PIXIS_VSPEED1);
+         tmp = (tmp & 0xF0) | (val & 0x0F);
+         out8(PIXIS_BASE+PIXIS_VSPEED1,tmp);
+         
+         return 1;
+}
+
+int set_px_corepll(ulong corepll)
+{
+         u8 tmp;
+         u8 val;
+        
+         switch((int)corepll)
+         {
+            case 20:
+               val = 0x08;
+               break;
+            case 25:
+               val = 0x0C;
+               break;
+            case 30:
+               val = 0x10;
+               break;
+            case 35:
+               val = 0x1C;
+               break;
+            case 40:
+               val = 0x14;
+               break;
+            case 45:
+               val = 0x0E;
+               break;
+            default:
+               printf("Unsupported COREPLL ratio.\n");
+               return 0;
+         }
+         
+         tmp = in8(PIXIS_BASE+PIXIS_VSPEED0);
+         tmp = (tmp & 0xE0) | (val & 0x1F);
+         out8(PIXIS_BASE+PIXIS_VSPEED0,tmp);
+         
+         return 1;
+}
+
+void read_from_px_regs(int set)
+{
+         u8 tmp, mask = 0x1C;
+         tmp = in8(PIXIS_BASE+PIXIS_VCFGEN0);
+         if (set)
+            tmp = tmp | mask;
+         else
+            tmp = tmp & ~mask;
+         out8(PIXIS_BASE+PIXIS_VCFGEN0,tmp);                        
+}
+
+void read_from_px_regs_altbank(int set)
+{
+         u8 tmp, mask = 0x04;
+         tmp = in8(PIXIS_BASE+PIXIS_VCFGEN1);
+         if (set)
+            tmp = tmp | mask;
+         else
+            tmp = tmp & ~mask;
+         out8(PIXIS_BASE+PIXIS_VCFGEN1,tmp);   
+}
+
+void set_altbank(void)
+{
+         u8 tmp;
+         tmp = in8(PIXIS_BASE+PIXIS_VBOOT);
+         tmp ^= 0x40;
+         out8(PIXIS_BASE+PIXIS_VBOOT,tmp);
+ }
+
+
+void set_px_go(void)
+{
+         u8 tmp;
+         tmp = in8(PIXIS_BASE+PIXIS_VCTL);
+         tmp = tmp & 0x1E;
+         out8(PIXIS_BASE+PIXIS_VCTL,tmp);
+         tmp = in8(PIXIS_BASE+PIXIS_VCTL);
+         tmp = tmp | 0x01;
+         out8(PIXIS_BASE+PIXIS_VCTL,tmp); 
+}
+
+void set_px_go_with_watchdog(void)
+{
+         u8 tmp;
+         tmp = in8(PIXIS_BASE+PIXIS_VCTL);
+         tmp = tmp & 0x1E;
+         out8(PIXIS_BASE+PIXIS_VCTL,tmp);
+         tmp = in8(PIXIS_BASE+PIXIS_VCTL);
+         tmp = tmp | 0x09;
+         out8(PIXIS_BASE+PIXIS_VCTL,tmp); 
+}
+
+/* This function takes the non-integral cpu:mpx pll ratio
+ * and converts it to an integer that can be used to assign
+ * FPGA register values.
+ * input: strptr i.e. argv[2]
+*/
+
+ulong strfractoint(uchar *strptr)
+{
+   int i,j,retval,intarr_len=0, decarr_len=0, mulconst, no_dec=0;
+   ulong intval =0, decval=0;
+   uchar intarr[3], decarr[3];
+
+   /* Assign the integer part to intarr[]
+    * If there is no decimal point i.e.
+    * if the ratio is an integral value
+    * simply create the intarr.
+   */
+   i=0;
+   while(strptr[i] != 46)
+   {
+      if(strptr[i] == 0)
+      {
+         no_dec = 1;
+         break;    /* Break from loop once the end of string is reached */
+      }
+      
+      intarr[i] = strptr[i];
+      i++;
+   }
+   
+   intarr_len = i; /* Assign length of integer part to intarr_len*/
+   intarr[i] = '\0'; /* */
+
+   if(no_dec)
+   {
+      mulconst=10; /* Currently needed only for single digit corepll ratios */
+      decval = 0;
+   }
+   else
+   {
+      j=0;
+      i++; /* Skipping the decimal point */
+      while ((strptr[i] > 47) && (strptr[i] < 58))
+      {
+         decarr[j] = strptr[i];
+         i++;
+         j++;
+      }
+      
+      decarr_len = j;
+      decarr[j] = '\0';
+      
+      mulconst=1;
+      for(i=0; i<decarr_len;i++)
+         mulconst = mulconst*10;
+      decval = simple_strtoul(decarr,NULL,10);      
+   }
+
+   intval = simple_strtoul(intarr,NULL,10);
+   intval = intval*mulconst;
+
+   retval = intval+decval;
+
+   return retval;
+
+}
+   
+
+#endif //CONFIG_MPC8641HPCN
+
+
+/* no generic way to do board reset. simply call soft_reset. */
+void
+do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+        char cmd;
+        ulong addr, val;
+        ulong corepll;
+        
+                
+
+#ifdef CFG_RESET_ADDRESS
+	addr = CFG_RESET_ADDRESS;
+#else
+	/*
+	 * note: when CFG_MONITOR_BASE points to a RAM address,
+	 * CFG_MONITOR_BASE - sizeof (ulong) is usually a valid
+	 * address. Better pick an address known to be invalid on your
+	 * system and assign it to CFG_RESET_ADDRESS.
+	 */
+	addr = CFG_MONITOR_BASE - sizeof (ulong);
+#endif
+
+#ifndef CONFIG_MPC8641HPCN
+
+       /* flush and disable I/D cache */
+	__asm__ __volatile__ ("mfspr	3, 1008"	::: "r3");
+	__asm__ __volatile__ ("ori	5, 5, 0xcc00"	::: "r5");
+	__asm__ __volatile__ ("ori	4, 3, 0xc00"	::: "r4");
+	__asm__ __volatile__ ("andc	5, 3, 5"	::: "r5");
+	__asm__ __volatile__ ("sync");
+	__asm__ __volatile__ ("mtspr	1008, 4");
+	__asm__ __volatile__ ("isync");
+	__asm__ __volatile__ ("sync");
+	__asm__ __volatile__ ("mtspr	1008, 5");
+	__asm__ __volatile__ ("isync");
+	__asm__ __volatile__ ("sync");
+
+        soft_restart(addr);
+
+#else /* CONFIG_MPC8641HPCN */
+        
+        if(argc > 1)
+        {
+           cmd = argv[1][1];
+           switch(cmd)
+           {
+              case 'f':    /* reset with frequency changed */
+
+                 if (argc < 5)
+                    goto my_usage;
+                 
+                 read_from_px_regs(0);
+                 
+                 val = set_px_sysclk(simple_strtoul(argv[2],NULL,10));
+                 
+                 corepll = strfractoint(argv[3]);
+                 val = val + set_px_corepll(corepll);
+                 val = val + set_px_mpxpll(simple_strtoul(argv[4],NULL,10));
+                 if(val == 3)
+                 {
+                    printf("Setting registers VCFGEN0 and VCTL\n");
+                    read_from_px_regs(1);
+                    printf("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n");
+                    set_px_go();
+                 }
+                 else
+                    goto my_usage;
+                 
+                 while(1); /* Not reached */
+                 
+              case 'l':
+                 if(argv[2][1] == 'f')
+                 {
+                    read_from_px_regs(0);
+                    read_from_px_regs_altbank(0);
+                    /* reset with frequency changed */
+                    val = set_px_sysclk(simple_strtoul(argv[3],NULL,10));
+                    
+                    corepll = strfractoint(argv[4]);
+                    val = val + set_px_corepll(corepll);
+                    val = val + set_px_mpxpll(simple_strtoul(argv[5],NULL,10));
+                    if(val == 3)
+                    {
+                       printf("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
+                       set_altbank();
+                       read_from_px_regs(1);
+                       read_from_px_regs_altbank(1);
+                       printf("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n");
+                       set_px_go_with_watchdog();
+                       
+                    }
+                    else
+                       goto my_usage;
+                 
+                    while(1); /* Not reached */
+                 }
+                 else /* Reset from next bank without changing frequencies */
+                 {
+                    read_from_px_regs(0);
+                    read_from_px_regs_altbank(0);
+                    if(argc > 2)
+                       goto my_usage;
+                    printf("Setting registers VCFGEN1, VBOOT, and VCTL\n");
+                    set_altbank();
+                    read_from_px_regs_altbank(1);
+                    printf("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n");
+                    set_px_go_with_watchdog();
+                    while(1); /* Not reached */
+                 }
+
+              default:
+                 goto my_usage;
+           }
+my_usage:
+           printf("\nUsage: reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n");
+           printf("       reset altbank [cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>]\n");
+           printf("For example:   reset cf 40 2.5 10\n");
+           printf("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n");
+           return;
+        }
+        else
+           out8(PIXIS_BASE+PIXIS_RST,0);
+           
+#endif /* !CONFIG_MPC8641HPCN */
+        
+	while(1);	/* not reached */
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Get timebase clock frequency
+ */
+unsigned long get_tbclk(void)
+{
+	sys_info_t  sys_info;
+
+	get_sys_info(&sys_info);
+	return ((sys_info.freqSystemBus + 3L) / 4L);
+
+}
+
+/* ------------------------------------------------------------------------- */
+
+#if defined(CONFIG_WATCHDOG)
+void
+watchdog_reset(void)
+{
+
+}
+#endif	/* CONFIG_WATCHDOG */
+
+/* ------------------------------------------------------------------------- */
+
+#if defined(CONFIG_DDR_ECC)
+void dma_init(void) {
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_dma_t *dma = &immap->im_dma;
+
+	dma->satr0 = 0x00040000;
+	dma->datr0 = 0x00040000;
+	asm("sync; isync");
+	return;
+}
+
+uint dma_check(void) {
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_dma_t *dma = &immap->im_dma;
+	volatile uint status = dma->sr0;
+
+	/* While the channel is busy, spin */
+	while((status & 4) == 4) {
+		status = dma->sr0;
+	}
+
+	if (status != 0) {
+		printf ("DMA Error: status = %x\n", status);
+	}
+	return status;
+}
+
+int dma_xfer(void *dest, uint count, void *src) {
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_dma_t *dma = &immap->im_dma;
+
+	dma->dar0 = (uint) dest;
+	dma->sar0 = (uint) src;
+	dma->bcr0 = count;
+	dma->mr0 = 0xf000004;
+	asm("sync;isync");
+	dma->mr0 = 0xf000005;
+	asm("sync;isync");
+	return dma_check();
+}
+#endif	/* CONFIG_DDR_ECC */
+
+
+#ifdef CONFIG_OF_FLAT_TREE
+void ft_cpu_setup(void *blob, bd_t *bd)
+{
+	u32 *p;
+	ulong clock;
+	int len;
+  
+	clock = bd->bi_busfreq;
+	p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
+	if (p != NULL)
+		*p = cpu_to_be32(clock);
+
+	p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
+	if (p != NULL)
+		*p = cpu_to_be32(clock);
+
+	p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
+	if (p != NULL)
+		*p = cpu_to_be32(clock);
+
+#if defined(CONFIG_MPC86XX_TSEC1)
+	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/address", &len);
+	memcpy(p, bd->bi_enetaddr, 6);
+#endif
+ 
+#if defined(CONFIG_MPC86XX_TSEC2)
+	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/address", &len);
+	memcpy(p, bd->bi_enet1addr, 6);
+#endif
+
+#if defined(CONFIG_MPC86XX_TSEC3)
+	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/address", &len);
+	memcpy(p, bd->bi_enet2addr, 6);
+#endif
+
+#if defined(CONFIG_MPC86XX_TSEC4)
+	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/address", &len);
+	 memcpy(p, bd->bi_enet3addr, 6);
+#endif
+
+}
+#endif
diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c
new file mode 100644
index 0000000..582ac6b
--- /dev/null
+++ b/cpu/mpc86xx/cpu_init.c
@@ -0,0 +1,134 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Jeff Brown (jeffrey@freescale.com)
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * cpu_init.c - low level cpu init
+ */
+
+#include <common.h>
+#include <mpc86xx.h>
+
+/*
+ * Breathe some life into the CPU...
+ *
+ * Set up the memory map
+ * initialize a bunch of registers
+ */
+
+void cpu_init_f (void)
+{
+        DECLARE_GLOBAL_DATA_PTR;
+	volatile immap_t    *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_lbc_t *memctl = &immap->im_lbc;
+        //u8 val;
+        
+        /* Pointer is writable since we allocated a register for it */
+	gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
+
+	/* Clear initial global data */
+	memset ((void *) gd, 0, sizeof (gd_t));
+
+	/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
+	 * addresses - these have to be modified later when FLASH size
+	 * has been determined
+	 */
+
+#if defined(CFG_OR0_REMAP)
+	memctl->or0 = CFG_OR0_REMAP;
+#endif
+#if defined(CFG_OR1_REMAP)
+	memctl->or1 = CFG_OR1_REMAP;
+#endif
+
+	/* now restrict to preliminary range */
+#if defined(CFG_BR0_PRELIM) && defined(CFG_OR0_PRELIM)
+	memctl->br0 = CFG_BR0_PRELIM;
+	memctl->or0 = CFG_OR0_PRELIM;
+#endif
+
+#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
+	memctl->or1 = CFG_OR1_PRELIM;
+	memctl->br1 = CFG_BR1_PRELIM;
+#endif
+
+        //#if !defined(CONFIG_MPC86xx)
+#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
+	memctl->or2 = CFG_OR2_PRELIM;
+	memctl->br2 = CFG_BR2_PRELIM;
+#endif
+        //#endif
+	
+#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
+	memctl->or3 = CFG_OR3_PRELIM;
+	memctl->br3 = CFG_BR3_PRELIM;
+#endif
+	
+#if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM)
+	memctl->or4 = CFG_OR4_PRELIM;
+	memctl->br4 = CFG_BR4_PRELIM;
+#endif
+	
+#if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM)
+	memctl->or5 = CFG_OR5_PRELIM;
+	memctl->br5 = CFG_BR5_PRELIM;
+#endif
+
+#if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM)
+	memctl->or6 = CFG_OR6_PRELIM;
+	memctl->br6 = CFG_BR6_PRELIM;
+#endif
+
+#if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM)
+	memctl->or7 = CFG_OR7_PRELIM;
+	memctl->br7 = CFG_BR7_PRELIM;
+#endif
+
+	/* enable the timebase bit in HID0 */
+	set_hid0(get_hid0() | 0x4000000);
+
+        /* enable SYNCBE | ABE bits in  HID1 */
+        set_hid1(get_hid1() | 0x00000C00);
+
+        /* Since the bats have been set up at this point and
+         * the local bus registers have been initialized, we
+         * turn on the WDEN bit in PIXIS_VCTL
+         */
+/*         val = in8(PIXIS_BASE+PIXIS_VCTL); */
+        /* Set the WDEN */
+/*         val |= 0x08; */
+/*         out8(PIXIS_BASE+PIXIS_VCTL,val);  */
+}
+
+/*
+ * initialize higher level parts of CPU like timers
+ */
+int cpu_init_r (void)
+{
+	return (0);
+}
+
+
+
+
+
diff --git a/cpu/mpc86xx/i2c.c b/cpu/mpc86xx/i2c.c
new file mode 100644
index 0000000..c5d4642
--- /dev/null
+++ b/cpu/mpc86xx/i2c.c
@@ -0,0 +1,273 @@
+/*
+ * (C) Copyright 2003,Motorola Inc.
+ * Xianghua Xiao <x.xiao@motorola.com>
+ * Adapted for Motorola 85xx chip.
+ *
+ * (C) Copyright 2003
+ * Gleb Natapov <gnatapov@mrv.com>
+ * Some bits are taken from linux driver writen by adrian@humboldt.co.uk
+ *
+ * Modified for MPC86xx by Jeff Brown (jeffrey@freescale.com)
+ *
+ * Hardware I2C driver for MPC107 PCI bridge.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_HARD_I2C
+#include <i2c.h>
+
+#define TIMEOUT (CFG_HZ/4)
+
+#define I2C_Addr ((u8 *)(CFG_CCSRBAR + 0x3100))
+
+#define I2CADR  &I2C_Addr[0]
+#define I2CFDR  &I2C_Addr[4]
+#define I2CCCR  &I2C_Addr[8]
+#define I2CCSR  &I2C_Addr[12]
+#define I2CCDR  &I2C_Addr[16]
+#define I2CDFSRR &I2C_Addr[20]
+
+#define I2C_READ  1
+#define I2C_WRITE 0
+
+void
+i2c_init(int speed, int slaveadd)
+{
+	/* stop I2C controller */
+	writeb(0x0, I2CCCR);
+
+	/* set clock */
+	writeb(0x3f, I2CFDR);
+
+	/* set default filter */
+	writeb(0x10,I2CDFSRR);
+
+	/* write slave address */
+	writeb(slaveadd, I2CADR);
+
+	/* clear status register */
+	writeb(0x0, I2CCSR);
+
+	/* start I2C controller */
+	writeb(MPC86xx_I2CCR_MEN, I2CCCR);
+}
+
+static __inline__ int
+i2c_wait4bus (void)
+{
+	ulong timeval = get_timer (0);
+
+        //        debug("I2C: Wait for bus\n");
+	while (readb(I2CCSR) & MPC86xx_I2CSR_MBB) {
+		if (get_timer (timeval) > TIMEOUT) {
+			return -1;
+		}
+	}
+
+  return 0;
+}
+
+static __inline__ int
+i2c_wait (int write)
+{
+	u32 csr;
+	ulong timeval = get_timer (0);
+
+	do {
+		csr = readb(I2CCSR);
+
+		if (!(csr & MPC86xx_I2CSR_MIF))
+			continue;
+
+		writeb(0x0, I2CCSR);
+
+		if (csr & MPC86xx_I2CSR_MAL) {
+			debug("i2c_wait: MAL\n");
+			return -1;
+		}
+
+		if (!(csr & MPC86xx_I2CSR_MCF))	{
+			debug("i2c_wait: unfinished\n");
+			return -1;
+		}
+
+		if (write == I2C_WRITE && (csr & MPC86xx_I2CSR_RXAK)) {
+			debug("i2c_wait: No RXACK\n");
+			return -1;
+		}
+
+		return 0;
+	} while (get_timer (timeval) < TIMEOUT);
+
+	debug("i2c_wait: timed out\n");
+	return -1;
+}
+
+static __inline__ int
+i2c_write_addr (u8 dev, u8 dir, int rsta)
+{
+   //        debug("I2C: Write Addr\n");
+	writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA | MPC86xx_I2CCR_MTX |
+	       (rsta?MPC86xx_I2CCR_RSTA:0),
+	       I2CCCR);
+
+	writeb((dev << 1) | dir, I2CCDR);
+
+	if (i2c_wait (I2C_WRITE) < 0)
+		return 0;
+
+	return 1;
+}
+
+static __inline__ int
+__i2c_write (u8 *data, int length)
+{
+	int i;
+        //        debug("I2C: __i2c_write\n");
+	writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA | MPC86xx_I2CCR_MTX,
+	       I2CCCR);
+
+	for (i=0; i < length; i++) {
+		writeb(data[i], I2CCDR);
+
+		if (i2c_wait (I2C_WRITE) < 0)
+			break;
+	}
+
+	return i;
+}
+
+static __inline__ int
+__i2c_read (u8 *data, int length)
+{
+	int i;
+
+	writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA |
+	       ((length == 1) ? MPC86xx_I2CCR_TXAK : 0),
+	       I2CCCR);
+
+	/* dummy read */
+	readb(I2CCDR);
+        //        debug("length = %d\n", length);
+
+	for (i=0; i < length; i++) {
+		if (i2c_wait (I2C_READ) < 0)
+			break;
+
+		/* Generate ack on last next to last byte */
+		if (i == length - 2)
+			writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA |
+			       MPC86xx_I2CCR_TXAK,
+			       I2CCCR);
+
+		/* Generate stop on last byte */
+		if (i == length - 1)
+			writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_TXAK, I2CCCR);
+
+                //      debug("I2CCR = 0x%08x\n", readb(I2CCCR));
+		data[i] = readb(I2CCDR);
+                //                debug("data[i] = 0x%08x\n", data[i]);
+	}
+        //        debug("Returning i = %d\n", i);
+	return i;
+}
+
+int
+i2c_read (u8 dev, uint addr, int alen, u8 *data, int length)
+{
+	int i = 0;
+	u8 *a = (u8*)&addr;
+
+	if (i2c_wait4bus () < 0)
+		goto exit;
+
+	if (i2c_write_addr (dev, I2C_WRITE, 0) == 0)
+		goto exit;
+
+	if (__i2c_write (&a[4 - alen], alen) != alen)
+		goto exit;
+
+	if (i2c_write_addr (dev, I2C_READ, 1) == 0)
+		goto exit;
+
+	i = __i2c_read (data, length);
+
+ exit:
+	writeb(MPC86xx_I2CCR_MEN, I2CCCR);
+
+	return !(i == length);
+}
+
+int
+i2c_write (u8 dev, uint addr, int alen, u8 *data, int length)
+{
+	int i = 0;
+	u8 *a = (u8*)&addr;
+
+	if (i2c_wait4bus () < 0)
+		goto exit;
+
+	if (i2c_write_addr (dev, I2C_WRITE, 0) == 0)
+		goto exit;
+
+	if (__i2c_write (&a[4 - alen], alen) != alen)
+		goto exit;
+
+	i = __i2c_write (data, length);
+
+ exit:
+	writeb(MPC86xx_I2CCR_MEN, I2CCCR);
+
+	return !(i == length);
+}
+
+int i2c_probe (uchar chip)
+{
+	int tmp;
+
+	/*
+	 * Try to read the first location of the chip.  The underlying
+	 * driver doesn't appear to support sending just the chip address
+	 * and looking for an <ACK> back.
+	 */
+	udelay(10000);
+
+	return i2c_read (chip, 0, 1, (char *)&tmp, 1);
+}
+
+uchar i2c_reg_read (uchar i2c_addr, uchar reg)
+{
+	char buf[1];
+
+	i2c_read (i2c_addr, reg, 1, buf, 1);
+
+	return (buf[0]);
+}
+
+void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val)
+{
+	i2c_write (i2c_addr, reg, 1, &val, 1);
+}
+
+#endif /* CONFIG_HARD_I2C */
diff --git a/cpu/mpc86xx/interrupts.c b/cpu/mpc86xx/interrupts.c
new file mode 100644
index 0000000..759a30f
--- /dev/null
+++ b/cpu/mpc86xx/interrupts.c
@@ -0,0 +1,225 @@
+/*
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 (440 port)
+ * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com
+ *
+ * (C) Copyright 2003 Motorola Inc. (MPC85xx port)
+ * Xianghua Xiao (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2004 Freescale Semiconductor. (MPC86xx Port)
+ * Jeff Brown (Jeffrey@freescale.com)
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc86xx.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <ppc_asm.tmpl>
+
+unsigned long decrementer_count;		/* count value for 1e6/HZ microseconds */
+
+
+unsigned long timestamp;
+
+static __inline__ unsigned long get_msr (void)
+{
+	unsigned long msr;
+
+	asm volatile ("mfmsr %0":"=r" (msr):);
+
+	return msr;
+}
+
+static __inline__ void set_msr (unsigned long msr)
+{
+	asm volatile ("mtmsr %0"::"r" (msr));
+}
+
+static __inline__ unsigned long get_dec (void)
+{
+	unsigned long val;
+
+	asm volatile ("mfdec %0":"=r" (val):);
+
+	return val;
+}
+
+
+static __inline__ void set_dec (unsigned long val)
+{
+	if (val)
+		asm volatile ("mtdec %0"::"r" (val));
+}
+
+/* interrupt is not supported yet */
+int interrupt_init_cpu (unsigned *decrementer_count)
+{
+   return (0);
+}
+
+
+int interrupt_init (void)
+{
+	int ret;
+
+	/* call cpu specific function from $(CPU)/interrupts.c */
+	ret = interrupt_init_cpu (&decrementer_count);
+
+	if (ret)
+		return ret;
+
+        decrementer_count = get_tbclk()/CFG_HZ;
+        debug("interrupt init: tbclk() = %d MHz, decrementer_count = %d\n", (get_tbclk()/1000000), decrementer_count);
+        
+        set_dec (decrementer_count);
+
+	set_msr (get_msr () | MSR_EE);
+
+        debug("MSR = 0x%08lx, Decrementer reg = 0x%08lx\n", get_msr(), get_dec());
+        
+	return (0);
+}
+
+
+void enable_interrupts (void)
+{
+	set_msr (get_msr () | MSR_EE);
+}
+
+/* returns flag if MSR_EE was set before */
+int disable_interrupts (void)
+{
+	ulong msr = get_msr ();
+
+	set_msr (msr & ~MSR_EE);
+	return ((msr & MSR_EE) != 0);
+}
+
+
+void increment_timestamp(void)
+{
+   timestamp++;
+}
+
+/*
+ * timer_interrupt - gets called when the decrementer overflows,
+ * with interrupts disabled.
+ * Trivial implementation - no need to be really accurate.
+ */
+void
+timer_interrupt_cpu (struct pt_regs *regs)
+{
+	/* nothing to do here */
+	return;
+}
+
+
+void timer_interrupt (struct pt_regs *regs)
+{
+   /* call cpu specific function from $(CPU)/interrupts.c */
+   timer_interrupt_cpu (regs);
+        
+   timestamp++;
+
+   ppcDcbf(&timestamp);
+   
+   /* Restore Decrementer Count */
+   set_dec (decrementer_count);
+        
+#if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG)
+	if ((timestamp % (CFG_WATCHDOG_FREQ)) == 0)
+		WATCHDOG_RESET ();
+#endif    /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */
+
+#ifdef CONFIG_STATUS_LED
+	status_led_tick (timestamp);
+#endif /* CONFIG_STATUS_LED */
+
+#ifdef CONFIG_SHOW_ACTIVITY
+	board_show_activity (timestamp);
+#endif /* CONFIG_SHOW_ACTIVITY */
+
+
+}
+
+void reset_timer (void)
+{
+   	timestamp = 0;
+}
+
+ulong get_timer (ulong base)
+{  
+ 	return (timestamp - base);
+}
+
+void set_timer (ulong t)
+{
+   timestamp = t;
+}
+
+/*
+ * Install and free a interrupt handler. Not implemented yet.
+ */
+
+void
+irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
+{
+	return;
+}
+
+void
+irq_free_handler(int vec)
+{
+	return;
+}
+
+
+
+/*******************************************************************************
+ *
+ * irqinfo - print information about PCI devices,not implemented.
+ *
+ */
+int
+do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	printf ("\nInterrupt-unsupported:\n");
+
+	return 0;
+}
+
+/*
+ * Handle external interrupts
+ */
+void
+external_interrupt(struct pt_regs *regs)
+{
+	puts("external_interrupt (oops!)\n");
+}
+
+
+
+
+
+
diff --git a/cpu/mpc86xx/pci.c b/cpu/mpc86xx/pci.c
new file mode 100644
index 0000000..9cf5f7c
--- /dev/null
+++ b/cpu/mpc86xx/pci.c
@@ -0,0 +1,196 @@
+/*
+ * Copyright 2005 Freescale Semiconductor.
+ * Ed Swarthout (ed.swarthout@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * PEX Configuration space access support for MPC85xx PEX Bridge
+ */
+#include <common.h>
+#include <pci.h>
+
+
+#if defined(CONFIG_PCI)
+
+void
+pci_mpc86xx_init(struct pci_controller *hose)
+{
+	volatile immap_t    *immap = (immap_t *)CFG_CCSRBAR;
+	volatile ccsr_pex_t *pex1 = &immap->im_pex1;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+	uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17;
+	uint pex1_host =   (host1_agent == 2) || (host1_agent == 3);
+
+	u16 reg16, reg16_1, reg16_2, reg16_3;
+	u32 reg32, i;
+
+        ulong addr, data;
+
+        
+        uint pex1_agent =  (host1_agent == 0) || (host1_agent == 1);
+        uint devdisr = gur->devdisr;
+        uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16;
+        
+        if ((io_sel==2 || io_sel==3 || io_sel==5 || io_sel==6 || io_sel==7 || io_sel==0xF ) && !(devdisr & MPC86xx_DEVDISR_PCIEX1)){
+                printf ("PCI-EXPRESS 1: Configured as %s \n",
+                        pex1_agent ? "Agent" : "Host");
+                printf ("               Scanning PCI bus");
+                debug("0x%08x=0x%08x ", &pex1->pme_msg_det,pex1->pme_msg_det);
+                if (pex1->pme_msg_det) {
+                        pex1->pme_msg_det = 0xffffffff;
+                        debug (" with errors.  Clearing.  Now 0x%08x",pex1->pme_msg_det);
+                }
+                debug ("\n");
+        }
+        
+        
+	hose->first_busno = 0;
+	hose->last_busno = 0x7f;
+
+	pci_set_region(hose->regions + 0,
+		       CFG_PCI1_MEM_BASE,
+		       CFG_PCI1_MEM_PHYS,
+		       CFG_PCI1_MEM_SIZE,
+		       PCI_REGION_MEM);
+
+	pci_set_region(hose->regions + 1,
+		       CFG_PCI1_IO_BASE,
+		       CFG_PCI1_IO_PHYS,
+		       CFG_PCI1_IO_SIZE,
+		       PCI_REGION_IO);
+
+	hose->region_count = 2;
+
+	pci_setup_indirect(hose,
+			   (CFG_IMMR+0x8000),
+			   (CFG_IMMR+0x8004));
+
+	/*
+	 * Hose scan.
+	 */
+	pci_register_hose(hose);
+
+        //#define MPC8548_REV1_PEX12_ERRATA
+#ifdef MPC8548_REV1_PEX12_ERRATA
+	/* can only read/write 4 bytes */
+	pci_read_config_dword (PCI_BDF(0,0,0), PCI_VENDOR_ID, &reg32);
+	printf("pex_mpc85xx_init: pex cr %2x %8x\n",PCI_VENDOR_ID, reg32);
+
+	pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg32);
+	reg32 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+	pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg32);
+#else
+	pci_read_config_word (PCI_BDF(0,0,0), PCI_VENDOR_ID, &reg16);
+	debug("pex_mpc86xx_init: read %2x %4x\n",PCI_VENDOR_ID, reg16);
+	pci_read_config_word (PCI_BDF(0,0,0), PCI_DEVICE_ID, &reg16);
+	debug("pex_mpc86xx_init: read %2x %4x\n",PCI_DEVICE_ID, reg16);
+
+	pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
+	reg16 |= PCI_COMMAND_SERR |  PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+	pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
+
+        pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
+	debug("pex_mpc86xx_init: read %2x %4x\n",PCI_COMMAND, reg16);
+
+        
+#endif
+
+	/*
+	 * Clear non-reserved bits in status register.
+	 */
+	//	pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
+	//	pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
+
+	pex1->powbar1  = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
+	pex1->powar1   = 0x8004401c;	/* 512M MEM space */
+	pex1->potar1   = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
+	pex1->potear1  = 0x00000000;
+
+        pex1->powbar2  = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
+	pex1->powar2   = 0x80088017;	/* 16M IO space */
+	pex1->potar2   = 0x00000000;
+	pex1->potear2  = 0x00000000;
+
+
+	if (!pex1->piwar1) {
+		pex1->pitar1 = 0x00000000;
+		pex1->piwbar1 = (0x80000000 >> 12 ) & 0x000fffff;
+		pex1->piwar1 = 0xa0f5501e;	/* Enable, Prefetch, Local Mem,
+						 * Snoop R/W, 2G */
+	}
+
+	pex1->pitar2 = 0x00000000;
+        pex1->piwbar2 = (0xe2000000 >> 12 ) & 0x000fffff;
+        pex1->piwar2 = 0xa0f5501e;	/* Enable, Prefetch, Local Mem,
+                                           
+
+        
+/* 	if (pex1_host) { */
+/* #ifdef MPC8548_REV1_PEX12_ERRATA */
+/* 		pci_write_config_dword (PCI_BDF(0,0,0), 0x18, 0x00ff0100); */
+/* #else */
+
+
+
+                *(u32 *)(0xf8008000)= 0x80000000;
+                debug("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004));
+
+
+                pci_write_config_byte(PCI_BDF(0,0,0), PCI_PRIMARY_BUS,0x20);
+                pci_write_config_byte(PCI_BDF(0,0,0), PCI_SECONDARY_BUS,0x00);
+		pci_write_config_byte(PCI_BDF(0,0,0), PCI_SUBORDINATE_BUS,0x1F);
+/* #endif */
+
+
+                *(u32 *)(0xf8008000)= 0x80200000;
+                debug("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004));
+
+                *(u32 *)(0xf8008000)= 0x80200000;
+                debug("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004));
+
+                *(u32 *)(0xf8008000)= 0x80200000;
+                debug("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004));
+
+
+                
+		hose->last_busno = pci_hose_scan(hose);
+                hose->last_busno = 0x21;
+		debug("pex_mpc86xx_init: last_busno %x\n",hose->last_busno);
+                debug("pex_mpc86xx init: current_busno %x\n ",hose->current_busno);
+
+
+                printf("....PCI scan & enumeration done\n");
+
+/*                 *(u32 *)(0xf8008000)= 0x80000000 | (0x12 << 11); */
+/*                 printf("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004)); */
+                
+/* 		if (hose->last_busno < 1) { */
+/* 			hose->last_busno=1;  /\*Hack*\/ */
+/*                 } else { */
+/*                    hose->last_busno = 0; */
+/*                 } */
+/*}*/
+/*         pci_read_config_dword (PCI_BDF(1,0,0), 0x18, &reg32); */
+/*         printf("pex_mpc86xx_init: pex cr %2x %8x\n",0x18, reg32); */
+
+
+}
+#endif /* CONFIG_PCI */
diff --git a/cpu/mpc86xx/resetvec.S b/cpu/mpc86xx/resetvec.S
new file mode 100644
index 0000000..9a552f6
--- /dev/null
+++ b/cpu/mpc86xx/resetvec.S
@@ -0,0 +1,2 @@
+	.section .resetvec,"ax"
+	b _start
diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c
new file mode 100644
index 0000000..9c07f20
--- /dev/null
+++ b/cpu/mpc86xx/spd_sdram.c
@@ -0,0 +1,1017 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * (C) Copyright 2003 Motorola Inc.
+ * Xianghua Xiao (X.Xiao@motorola.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <i2c.h>
+#include <spd.h>
+#include <asm/mmu.h>
+
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void dma_init(void);
+extern uint dma_check(void);
+extern int dma_xfer(void *dest, uint count, void *src);
+#endif
+
+#ifdef CONFIG_SPD_EEPROM
+
+#ifndef	CFG_READ_SPD
+#define CFG_READ_SPD	i2c_read
+#endif
+
+/*
+ * Convert picoseconds into clock cycles (rounding up if needed).
+ */
+
+int
+picos_to_clk(int picos)
+{
+	int clks;
+
+	clks = picos / (2000000000 / (get_bus_freq(0) / 1000));
+	if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) {
+		clks++;
+	}
+
+	return clks;
+}
+
+
+/*
+ * Calculate the Density of each Physical Rank.
+ * Returned size is in bytes.
+ *
+ * Study these table from Byte 31 of JEDEC SPD Spec.
+ *
+ *		DDR I	DDR II
+ *	Bit	Size	Size
+ *	---	-----	------
+ *	7 high	512MB	512MB
+ *	6	256MB	256MB
+ *	5	128MB	128MB
+ *	4	 64MB	 16GB
+ *	3	 32MB	  8GB
+ *	2	 16MB	  4GB
+ *	1	  2GB	  2GB
+ *	0 low	  1GB	  1GB
+ *
+ * Reorder Table to be linear by stripping the bottom
+ * 2 or 5 bits off and shifting them up to the top.
+ */
+
+unsigned int
+compute_banksize(unsigned int mem_type, unsigned char row_dens)
+{
+	unsigned int bsize;
+
+	if (mem_type == SPD_MEMTYPE_DDR) {
+		/* Bottom 2 bits up to the top. */
+		bsize = ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
+		debug("DDR: DDR I rank density = 0x%08x\n", bsize);
+	} else {
+		/* Bottom 5 bits up to the top. */
+		bsize = ((row_dens >> 5) | ((row_dens & 31) << 3)) << 27;
+		debug("DDR: DDR II rank density = 0x%08x\n", bsize);
+	}
+	return bsize;
+}
+
+
+/*
+ * Convert a two-nibble BCD value into a cycle time.
+ * While the spec calls for nano-seconds, picos are returned.
+ *
+ * This implements the tables for bytes 9, 23 and 25 for both
+ * DDR I and II.  No allowance for distinguishing the invalid
+ * fields absent for DDR I yet present in DDR II is made.
+ * (That is, cycle times of .25, .33, .66 and .75 ns are
+ * allowed for both DDR II and I.)
+ */
+
+unsigned int
+convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val)
+{
+	/*
+	 * Table look up the lower nibble, allow DDR I & II.
+	 */
+	unsigned int tenths_ps[16] = {
+		0,
+		100,
+		200,
+		300,
+		400,
+		500,
+		600,
+		700,
+		800,
+		900,
+		250,
+		330,	/* FIXME: Is 333 better/valid? */
+		660,	/* FIXME: Is 667 better/valid? */
+		750,
+		0,	/* undefined */
+		0	/* undefined */
+	};
+
+	unsigned int whole_ns = (spd_val & 0xF0) >> 4;
+	unsigned int tenth_ns = spd_val & 0x0F;
+	unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns];
+
+	return ps;
+}
+
+
+long int
+spd_sdram(void)
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+	spd_eeprom_t spd;
+	unsigned int n_ranks;
+	unsigned int rank_density;
+	unsigned int odt_rd_cfg, odt_wr_cfg;
+	unsigned int odt_cfg, mode_odt_enable;
+	unsigned int dqs_cfg;
+	unsigned char twr_clk, twtr_clk, twr_auto_clk;
+	unsigned int tCKmin_ps, tCKmax_ps;
+	unsigned int max_data_rate, effective_data_rate;
+	unsigned int busfreq;
+	unsigned sdram_cfg_1;
+	unsigned int memsize;
+	unsigned char caslat, caslat_ctrl;
+	unsigned int trfc, trfc_clk, trfc_low, trfc_high;
+	unsigned int trcd_clk;
+	unsigned int trtp_clk;
+	unsigned char cke_min_clk;
+	unsigned char add_lat;
+	unsigned char wr_lat;
+	unsigned char wr_data_delay;
+	unsigned char four_act;
+	unsigned char cpo;
+	unsigned char burst_len;
+	unsigned int mode_caslat;
+	unsigned char sdram_type;
+	unsigned char d_init;
+
+
+        unsigned int law_size;
+        volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
+        
+	/*
+	 * Read SPD information.
+	 */
+
+	CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) &spd, sizeof(spd));
+
+	/*
+	 * Check for supported memory module types.
+	 */
+	if (spd.mem_type != SPD_MEMTYPE_DDR &&
+	    spd.mem_type != SPD_MEMTYPE_DDR2) {
+		printf("Unable to locate DDR I or DDR II module.\n"
+		       "    Fundamental memory type is 0x%0x\n",
+		       spd.mem_type);
+		return 0;
+	}
+
+	/*
+	 * These test gloss over DDR I and II differences in interpretation
+	 * of bytes 3 and 4, but irrelevantly.  Multiple asymmetric banks
+	 * are not supported on DDR I; and not encoded on DDR II.
+	 *
+	 * Also note that the 8548 controller can support:
+	 *    12 <= nrow <= 16
+	 * and
+	 *     8 <= ncol <= 11 (still, for DDR)
+	 *     6 <= ncol <=  9 (for FCRAM)
+	 */
+	if (spd.nrow_addr < 12 || spd.nrow_addr > 14) {
+		printf("DDR: Unsupported number of Row Addr lines: %d.\n",
+		       spd.nrow_addr);
+		return 0;
+	}
+	if (spd.ncol_addr < 8 || spd.ncol_addr > 11) {
+		printf("DDR: Unsupported number of Column Addr lines: %d.\n",
+		       spd.ncol_addr);
+		return 0;
+	}
+
+	/*
+	 * Determine the number of physical banks controlled by
+	 * different Chip Select signals.  This is not quite the
+	 * same as the number of DIMM modules on the board.  Feh.
+	 */
+	if (spd.mem_type == SPD_MEMTYPE_DDR) {
+		n_ranks = spd.nrows;
+	} else {
+		n_ranks = (spd.nrows & 0x7) + 1;
+	}
+
+	debug("DDR: number of ranks = %d\n", n_ranks);
+
+	if (n_ranks > 2) {
+		printf("DDR: Only 2 chip selects are supported: %d\n",
+		       n_ranks);
+		return 0;
+	}
+
+	/*
+	 * Adjust DDR II IO voltage biasing.  It just makes it work.
+	 */
+	if (spd.mem_type == SPD_MEMTYPE_DDR2) {
+		gur->ddrioovcr = (0
+				  | 0x80000000		/* Enable */
+				  | 0x10000000		/* VSEL to 1.8V */
+				  );
+	}
+
+	/*
+	 * Determine the size of each Rank in bytes.
+	 */
+	rank_density = compute_banksize(spd.mem_type, spd.row_dens);
+
+
+	/*
+	 * Eg: Bounds: 0x0000_0000 to 0x0f000_0000	first 256 Meg
+	 */
+	ddr1->cs0_bnds = (rank_density >> 24) - 1;
+
+	/*
+	 * ODT configuration recommendation from DDR Controller Chapter.
+	 */
+	odt_rd_cfg = 0;			/* Never assert ODT */
+	odt_wr_cfg = 0;			/* Never assert ODT */
+	if (spd.mem_type == SPD_MEMTYPE_DDR2) {
+		odt_wr_cfg = 1;		/* Assert ODT on writes to CS0 */
+	}
+
+	ddr1->cs0_config = ( 1 << 31
+			    | (odt_rd_cfg << 20)
+			    | (odt_wr_cfg << 16)
+			    | (spd.nrow_addr - 12) << 8
+			    | (spd.ncol_addr - 8) );
+	debug("\n");
+	debug("DDR: cs0_bnds   = 0x%08x\n", ddr1->cs0_bnds);
+	debug("DDR: cs0_config = 0x%08x\n", ddr1->cs0_config);
+
+	if (n_ranks == 2) {
+		/*
+		 * Eg: Bounds: 0x0f00_0000 to 0x1e0000_0000, second 256 Meg
+		 */
+		ddr1->cs1_bnds = ( (rank_density >> 8)
+				  | ((rank_density >> (24 - 1)) - 1) );
+		ddr1->cs1_config = ( 1<<31
+				    | (odt_rd_cfg << 20)
+				    | (odt_wr_cfg << 16)
+				    | (spd.nrow_addr - 12) << 8
+				    | (spd.ncol_addr - 8) );
+		debug("DDR: cs1_bnds   = 0x%08x\n", ddr1->cs1_bnds);
+		debug("DDR: cs1_config = 0x%08x\n", ddr1->cs1_config);
+	}
+
+
+	/*
+	 * Find the largest CAS by locating the highest 1 bit
+	 * in the spd.cas_lat field.  Translate it to a DDR
+	 * controller field value:
+	 *
+	 *	CAS Lat	DDR I	DDR II	Ctrl
+	 *	Clocks	SPD Bit	SPD Bit	Value
+	 *	-------	-------	-------	-----
+	 *	1.0	0		0001
+	 *	1.5	1		0010
+	 *	2.0	2	2	0011
+	 *	2.5	3		0100
+	 *	3.0	4	3	0101
+	 *	3.5	5		0110
+	 *	4.0		4	0111
+	 *	4.5			1000
+	 *	5.0		5	1001
+	 */
+	caslat = __ilog2(spd.cas_lat);
+	if ((spd.mem_type == SPD_MEMTYPE_DDR)
+	    && (caslat > 5)) {
+		printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat);
+		return 0;
+
+	} else if (spd.mem_type == SPD_MEMTYPE_DDR2
+		   && (caslat < 2 || caslat > 5)) {
+		printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n",
+		       spd.cas_lat);
+		return 0;
+	}
+	debug("DDR: caslat SPD bit is %d\n", caslat);
+
+	/*
+	 * Calculate the Maximum Data Rate based on the Minimum Cycle time.
+	 * The SPD clk_cycle field (tCKmin) is measured in tenths of
+	 * nanoseconds and represented as BCD.
+	 */
+	tCKmin_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle);
+	debug("DDR: tCKmin = %d ps\n", tCKmin_ps);
+
+	/*
+	 * Double-data rate, scaled 1000 to picoseconds, and back down to MHz.
+	 */
+	max_data_rate = 2 * 1000 * 1000 / tCKmin_ps;
+	debug("DDR: Module max data rate = %d Mhz\n", max_data_rate);
+
+
+	/*
+	 * Adjust the CAS Latency to allow for bus speeds that
+	 * are slower than the DDR module.
+	 */
+	busfreq = get_bus_freq(0) / 1000000;	/* MHz */
+
+	effective_data_rate = max_data_rate;
+	if (busfreq < 90) {
+		/* DDR rate out-of-range */
+		puts("DDR: platform frequency is not fit for DDR rate\n");
+		return 0;
+
+	} else if (90 <= busfreq && busfreq < 230 && max_data_rate >= 230) {
+		/*
+		 * busfreq 90~230 range, treated as DDR 200.
+		 */
+		effective_data_rate = 200;
+		if (spd.clk_cycle3 == 0xa0)	/* 10 ns */
+			caslat -= 2;
+		else if (spd.clk_cycle2 == 0xa0)
+			caslat--;
+
+	} else if (230 <= busfreq && busfreq < 280 && max_data_rate >= 280) {
+		/*
+		 * busfreq 230~280 range, treated as DDR 266.
+		 */
+		effective_data_rate = 266;
+		if (spd.clk_cycle3 == 0x75)	/* 7.5 ns */
+			caslat -= 2;
+		else if (spd.clk_cycle2 == 0x75)
+			caslat--;
+
+	} else if (280 <= busfreq && busfreq < 350 && max_data_rate >= 350) {
+		/*
+		 * busfreq 280~350 range, treated as DDR 333.
+		 */
+		effective_data_rate = 333;
+		if (spd.clk_cycle3 == 0x60)	/* 6.0 ns */
+			caslat -= 2;
+		else if (spd.clk_cycle2 == 0x60)
+			caslat--;
+
+	} else if (350 <= busfreq && busfreq < 460 && max_data_rate >= 460) {
+		/*
+		 * busfreq 350~460 range, treated as DDR 400.
+		 */
+		effective_data_rate = 400;
+		if (spd.clk_cycle3 == 0x50)	/* 5.0 ns */
+			caslat -= 2;
+		else if (spd.clk_cycle2 == 0x50)
+			caslat--;
+
+	} else if (460 <= busfreq && busfreq < 560 && max_data_rate >= 560) {
+		/*
+		 * busfreq 460~560 range, treated as DDR 533.
+		 */
+		effective_data_rate = 533;
+		if (spd.clk_cycle3 == 0x3D)	/* 3.75 ns */
+			caslat -= 2;
+		else if (spd.clk_cycle2 == 0x3D)
+			caslat--;
+
+	} else if (560 <= busfreq && busfreq < 700 && max_data_rate >= 700) {
+		/*
+		 * busfreq 560~700 range, treated as DDR 667.
+		 */
+		effective_data_rate = 667;
+		if (spd.clk_cycle3 == 0x30)	/* 3.0 ns */
+			caslat -= 2;
+		else if (spd.clk_cycle2 == 0x30)
+			caslat--;
+
+	} else if (700 <= busfreq) {
+		/*
+		 * DDR rate out-of-range
+		 */
+		printf("DDR: Bus freq %d MHz is not fit for DDR rate %d MHz\n",
+		     busfreq, max_data_rate);
+		return 0;
+	}
+
+
+	/*
+	 * Convert caslat clocks to DDR controller value.
+	 * Force caslat_ctrl to be DDR Controller field-sized.
+	 */
+	if (spd.mem_type == SPD_MEMTYPE_DDR) {
+		caslat_ctrl = (caslat + 1) & 0x07;
+	} else {
+		caslat_ctrl =  (2 * caslat - 1) & 0x0f;
+	}
+
+	debug("DDR: effective data rate is %d MHz\n", effective_data_rate);
+	debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n",
+	      caslat, caslat_ctrl);
+
+	/*
+	 * Timing Config 0.
+	 * Avoid writing for DDR I.  The new PQ38 DDR controller
+	 * dreams up non-zero default values to be backwards compatible.
+	 */
+	if (spd.mem_type == SPD_MEMTYPE_DDR2) {
+		unsigned char taxpd_clk = 8;		/* By the book. */
+		unsigned char tmrd_clk = 2;		/* By the book. */
+		unsigned char act_pd_exit = 2;		/* Empirical? */
+		unsigned char pre_pd_exit = 6;		/* Empirical? */
+
+		ddr1->timing_cfg_0 = (0
+			| ((act_pd_exit & 0x7) << 20)	/* ACT_PD_EXIT */
+			| ((pre_pd_exit & 0x7) << 16)	/* PRE_PD_EXIT */
+			| ((taxpd_clk & 0xf) << 8)	/* ODT_PD_EXIT */
+			| ((tmrd_clk & 0xf) << 0)	/* MRS_CYC */
+			);
+		debug("DDR: timing_cfg_0 = 0x%08x\n", ddr1->timing_cfg_0);
+
+	} else {
+	}
+
+
+	/*
+	 * Some Timing Config 1 values now.
+	 * Sneak Extended Refresh Recovery in here too.
+	 */
+
+	/*
+	 * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD,
+	 * use conservative value.
+	 * For DDR II, they are bytes 36 and 37, in quarter nanos.
+	 */
+
+	if (spd.mem_type == SPD_MEMTYPE_DDR) {
+		twr_clk = 3;	/* Clocks */
+		twtr_clk = 1;	/* Clocks */
+	} else {
+		twr_clk = picos_to_clk(spd.twr * 250);
+		twtr_clk = picos_to_clk(spd.twtr * 250);
+	}
+
+	/*
+	 * Calculate Trfc, in picos.
+	 * DDR I:  Byte 42 straight up in ns.
+	 * DDR II: Byte 40 and 42 swizzled some, in ns.
+	 */
+	if (spd.mem_type == SPD_MEMTYPE_DDR) {
+		trfc = spd.trfc * 1000;		/* up to ps */
+	} else {
+		unsigned int byte40_table_ps[8] = {
+			0,
+			250,
+			330,
+			500,
+			660,
+			750,
+			0,
+			0
+		};
+
+		trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000
+			+ byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7];
+	}
+	trfc_clk = picos_to_clk(trfc);
+
+	/*
+	 * Trcd, Byte 29, from quarter nanos to ps and clocks.
+	 */
+	trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7;
+
+	/*
+	 * Convert trfc_clk to DDR controller fields.  DDR I should
+	 * fit in the REFREC field (16-19) of TIMING_CFG_1, but the
+	 * 8548 controller has an extended REFREC field of three bits.
+	 * The controller automatically adds 8 clocks to this value,
+	 * so preadjust it down 8 first before splitting it up.
+	 */
+	trfc_low = (trfc_clk - 8) & 0xf;
+	trfc_high = ((trfc_clk - 8) >> 4) & 0x3;
+
+	/*
+	 * Sneak in some Extended Refresh Recovery.
+	 */
+	ddr1->ext_refrec = (trfc_high << 16);
+	debug("DDR: ext_refrec = 0x%08x\n", ddr1->ext_refrec);
+
+	ddr1->timing_cfg_1 =
+	    (0
+	     | ((picos_to_clk(spd.trp * 250) & 0x07) << 28)	/* PRETOACT */
+	     | ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24)	/* ACTTOPRE */
+	     | (trcd_clk << 20)					/* ACTTORW */
+	     | (caslat_ctrl << 16)				/* CASLAT */
+	     | (trfc_low << 12)					/* REFEC */
+	     | ((twr_clk & 0x07) << 8)				/* WRRREC */
+	     | ((picos_to_clk(spd.trrd * 250) & 0x07) << 4)	/* ACTTOACT */
+	     | ((twtr_clk & 0x07) << 0)				/* WRTORD */
+	     );
+
+	debug("DDR: timing_cfg_1  = 0x%08x\n", ddr1->timing_cfg_1);
+
+
+	/*
+	 * Timing_Config_2
+	 * Was: 0x00000800;
+	 */
+
+	/*
+	 * Additive Latency
+	 * For DDR I, 0.
+	 * For DDR II, with ODT enabled, use "a value" less than ACTTORW,
+	 * which comes from Trcd, and also note that:
+	 *	add_lat + caslat must be >= 4
+	 */
+	add_lat = 0;
+	if (spd.mem_type == SPD_MEMTYPE_DDR2
+	    && (odt_wr_cfg || odt_rd_cfg)
+	    && (caslat < 4)) {
+		add_lat = 4 - caslat;
+		if (add_lat > trcd_clk) {
+			add_lat = trcd_clk - 1;
+		}
+	}
+
+	/*
+	 * Write Data Delay
+	 * Historically 0x2 == 4/8 clock delay.
+	 * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266.
+	 */
+	wr_data_delay = 3;
+
+	/*
+	 * Write Latency
+	 * Read to Precharge
+	 * Minimum CKE Pulse Width.
+	 * Four Activate Window
+	 */
+	if (spd.mem_type == SPD_MEMTYPE_DDR) {
+		/*
+		 * This is a lie.  It should really be 1, but if it is
+		 * set to 1, bits overlap into the old controller's
+		 * otherwise unused ACSM field.  If we leave it 0, then
+		 * the HW will magically treat it as 1 for DDR 1.  Oh Yea.
+		 */
+		wr_lat = 0;
+
+		trtp_clk = 2;		/* By the book. */
+		cke_min_clk = 1;	/* By the book. */
+		four_act = 1;		/* By the book. */
+
+	} else {
+		wr_lat = caslat - 1;
+
+		/* Convert SPD value from quarter nanos to picos. */
+		trtp_clk = picos_to_clk(spd.trtp * 250);
+
+		cke_min_clk = 3;	/* By the book. */
+		four_act = picos_to_clk(37500);	/* By the book. 1k pages? */
+	}
+
+	/*
+	 * Empirically set ~MCAS-to-preamble override for DDR 2.
+	 * Your milage will vary.
+	 */
+	cpo = 0;
+	if (spd.mem_type == SPD_MEMTYPE_DDR2) {
+		if (effective_data_rate == 266 || effective_data_rate == 333) {
+			cpo = 0x7;		/* READ_LAT + 5/4 */
+		} else if (effective_data_rate == 400) {
+			cpo = 0x9;		/* READ_LAT + 7/4 */
+		} else {
+			/* Pure speculation */
+			cpo = 0xb;
+		}
+	}
+
+	ddr1->timing_cfg_2 = (0
+		| ((add_lat & 0x7) << 28)		/* ADD_LAT */
+		| ((cpo & 0x1f) << 23)			/* CPO */ 
+		| ((wr_lat & 0x7) << 19)		/* WR_LAT */
+		| ((trtp_clk & 0x7) << 13)		/* RD_TO_PRE */
+		| ((wr_data_delay & 0x7) << 10)		/* WR_DATA_DELAY */
+		| ((cke_min_clk & 0x7) << 6)		/* CKE_PLS */
+		| ((four_act & 0x1f) << 0)		/* FOUR_ACT */
+		);
+
+	debug("DDR: timing_cfg_2 = 0x%08x\n", ddr1->timing_cfg_2);
+
+
+	/*
+	 * Determine the Mode Register Set.
+	 *
+	 * This is nominally part specific, but it appears to be
+	 * consistent for all DDR I devices, and for all DDR II devices.
+	 *
+	 *     caslat must be programmed
+	 *     burst length is always 4
+	 *     burst type is sequential
+	 *
+	 * For DDR I:
+	 *     operating mode is "normal"
+	 *
+	 * For DDR II:
+	 *     other stuff
+	 */
+
+	mode_caslat = 0;
+
+	/*
+	 * Table lookup from DDR I or II Device Operation Specs.
+	 */
+	if (spd.mem_type == SPD_MEMTYPE_DDR) {
+		if (1 <= caslat && caslat <= 4) {
+			unsigned char mode_caslat_table[4] = {
+				0x5,	/* 1.5 clocks */
+				0x2,	/* 2.0 clocks */
+				0x6,	/* 2.5 clocks */
+				0x3	/* 3.0 clocks */
+			};
+			mode_caslat = mode_caslat_table[caslat - 1];
+		} else {
+			puts("DDR I: Only CAS Latencies of 1.5, 2.0, "
+			     "2.5 and 3.0 clocks are supported.\n");
+			return 0;
+		}
+
+	} else {
+		if (2 <= caslat && caslat <= 5) {
+			mode_caslat = caslat;
+		} else {
+			puts("DDR II: Only CAS Latencies of 2.0, 3.0, "
+			     "4.0 and 5.0 clocks are supported.\n");
+			return 0;
+		}
+	}
+
+	/*
+	 * Encoded Burst Lenght of 4.
+	 */
+	burst_len = 2;			/* Fiat. */
+
+	if (spd.mem_type == SPD_MEMTYPE_DDR) {
+		twr_auto_clk = 0;	/* Historical */
+	} else {
+		/*
+		 * Determine tCK max in picos.  Grab tWR and convert to picos.
+		 * Auto-precharge write recovery is:
+		 *	WR = roundup(tWR_ns/tCKmax_ns).
+		 *
+		 * Ponder: Is twr_auto_clk different than twr_clk?
+		 */
+		tCKmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd.tckmax);
+		twr_auto_clk = (spd.twr * 250 + tCKmax_ps - 1) / tCKmax_ps;
+	}
+
+
+	/*
+	 * Mode Reg in bits 16 ~ 31,
+	 * Extended Mode Reg 1 in bits 0 ~ 15.
+	 */
+	mode_odt_enable = 0x0;			/* Default disabled */
+	if (odt_wr_cfg || odt_rd_cfg) {
+		/*
+		 * Bits 6 and 2 in Extended MRS(1)
+		 * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules.
+		 * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module.
+		 */
+		mode_odt_enable = 0x40;		/* 150 Ohm */
+	}
+
+	ddr1->sdram_mode_1 =
+		(0
+		 | (add_lat << (16 + 3))	/* Additive Latency in EMRS1 */
+		 | (mode_odt_enable << 16)	/* ODT Enable in EMRS1 */
+		 | (twr_auto_clk << 9)		/* Write Recovery Autopre */
+		 | (mode_caslat << 4)		/* caslat */
+		 | (burst_len << 0)		/* Burst length */
+		 );
+
+	debug("DDR: sdram_mode   = 0x%08x\n", ddr1->sdram_mode_1);
+
+
+	/*
+	 * Clear EMRS2 and EMRS3.
+	 */
+	ddr1->sdram_mode_2 = 0;
+	debug("DDR: sdram_mode_2 = 0x%08x\n", ddr1->sdram_mode_2);
+
+
+	/*
+	 * Determine Refresh Rate.  Ignore self refresh bit on DDR I.
+	 * Table from SPD Spec, Byte 12, converted to picoseconds and
+	 * filled in with "default" normal values.
+	 */
+	{
+		unsigned int refresh_clk;
+		unsigned int refresh_time_ns[8] = {
+			15625000,	/* 0 Normal    1.00x */
+			3900000,	/* 1 Reduced    .25x */
+			7800000,	/* 2 Extended   .50x */
+			31300000,	/* 3 Extended  2.00x */
+			62500000,	/* 4 Extended  4.00x */
+			125000000,	/* 5 Extended  8.00x */
+			15625000,	/* 6 Normal    1.00x  filler */
+			15625000,	/* 7 Normal    1.00x  filler */
+		};
+
+		refresh_clk = picos_to_clk(refresh_time_ns[spd.refresh & 0x7]);
+
+		/*
+		 * Set BSTOPRE to 0x100 for page mode
+		 * If auto-charge is used, set BSTOPRE = 0
+		 */
+		ddr1->sdram_interval =
+			(0
+			 | (refresh_clk & 0x3fff) << 16
+			 | 0x100
+			 );
+		debug("DDR: sdram_interval = 0x%08x\n", ddr1->sdram_interval);
+	}
+
+	/*
+	 * Is this an ECC DDR chip?
+	 * But don't mess with it if the DDR controller will init mem.
+	 */
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	if (spd.config == 0x02) {
+		ddr1->err_disable = 0x0000000d;
+		ddr1->err_sbe = 0x00ff0000;
+	}
+	debug("DDR: err_disable = 0x%08x\n", ddr1->err_disable);
+	debug("DDR: err_sbe = 0x%08x\n", ddr1->err_sbe);
+#endif
+
+	asm("sync;isync");
+	udelay(500);
+
+	/*
+	 * SDRAM Cfg 2
+	 */
+
+	/*
+	 * When ODT is enabled, Chap 9 suggests asserting ODT to
+	 * internal IOs only during reads.
+	 */
+	odt_cfg = 0;
+	if (odt_rd_cfg | odt_wr_cfg) {
+		odt_cfg = 0x2;		/* ODT to IOs during reads */
+	}
+
+	/*
+	 * Try to use differential DQS with DDR II.
+	 */
+	if (spd.mem_type == SPD_MEMTYPE_DDR) {
+		dqs_cfg = 0;		/* No Differential DQS for DDR I */
+	} else {
+		dqs_cfg = 0x1;		/* Differential DQS for DDR II */
+	}
+
+#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	/*
+	 * Use the DDR controller to auto initialize memory.
+	 */
+	d_init = 1;
+	ddr1->sdram_data_init = CONFIG_MEM_INIT_VALUE;
+	debug("DDR: ddr_data_init = 0x%08x\n", ddr1->sdram_data_init);
+#else
+	/*
+	 * Memory will be initialized via DMA, or not at all.
+	 */
+	d_init = 0;	
+#endif
+
+	ddr1->sdram_cfg_2 = (0
+			    | (dqs_cfg << 26)	/* Differential DQS */
+			    | (odt_cfg << 21)	/* ODT */
+			    | (d_init << 4)	/* D_INIT auto init DDR */
+			    );
+
+	debug("DDR: sdram_cfg_2  = 0x%08x\n", ddr1->sdram_cfg_2);
+
+
+#ifdef MPC86xx_DDR_SDRAM_CLK_CNTL
+	{
+		unsigned char clk_adjust;
+
+		/*
+		 * Setup the clock control.
+		 * SDRAM_CLK_CNTL[0] = Source synchronous enable == 1
+		 * SDRAM_CLK_CNTL[5-7] = Clock Adjust
+		 *	0110	3/4 cycle late
+		 *	0111	7/8 cycle late
+		 */
+		if (spd.mem_type == SPD_MEMTYPE_DDR) {
+			clk_adjust = 0x6;
+		} else {
+			clk_adjust = 0x7;
+		}
+
+		ddr1->sdram_clk_cntl = (0
+			       | 0x80000000
+			       | (clk_adjust << 23)
+			       );
+		debug("DDR: sdram_clk_cntl = 0x%08x\n", ddr1->sdram_clk_cntl);
+	}
+#endif
+
+	/*
+	 * Figure out the settings for the sdram_cfg register.
+	 * Build up the entire register in 'sdram_cfg' before writing
+	 * since the write into the register will actually enable the
+	 * memory controller; all settings must be done before enabling.
+	 *
+	 * sdram_cfg[0]   = 1 (ddr sdram logic enable)
+	 * sdram_cfg[1]   = 1 (self-refresh-enable)
+	 * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM)
+	 *			010 DDR 1 SDRAM
+	 *			011 DDR 2 SDRAM
+	 */
+	sdram_type = (spd.mem_type == SPD_MEMTYPE_DDR) ? 2 : 3;
+	sdram_cfg_1 = (0
+		     | (1 << 31)			/* Enable */
+		     | (1 << 30)			/* Self refresh */
+		     | (sdram_type << 24)		/* SDRAM type */
+		     );
+
+	/*
+	 * sdram_cfg[3] = RD_EN - registered DIMM enable
+	 *   A value of 0x26 indicates micron registered DIMMS (micron.com)
+	 */
+	if (spd.mem_type == SPD_MEMTYPE_DDR && spd.mod_attr == 0x26) {
+		sdram_cfg_1 |= 0x10000000;		/* RD_EN */
+	}
+
+#if defined(CONFIG_DDR_ECC)
+	/*
+	 * If the user wanted ECC (enabled via sdram_cfg[2])
+	 */
+	if (spd.config == 0x02) {
+		sdram_cfg_1 |= 0x20000000;		/* ECC_EN */
+	}
+#endif
+
+	/*
+	 * REV1 uses 1T timing.
+	 * REV2 may use 1T or 2T as configured by the user.
+	 */
+	{
+		uint pvr = get_pvr();
+
+		if (pvr != PVR_85xx_REV1) {
+#if defined(CONFIG_DDR_2T_TIMING)
+			/*
+			 * Enable 2T timing by setting sdram_cfg[16].
+			 */
+			sdram_cfg_1 |= 0x8000;		/* 2T_EN */
+#endif
+		}
+	}
+
+	/*
+	 * 200 painful micro-seconds must elapse between
+	 * the DDR clock setup and the DDR config enable.
+	 */
+	udelay(200);
+
+	/*
+	 * Go!
+	 */
+	ddr1->sdram_cfg_1 = sdram_cfg_1;
+
+	asm("sync;isync");
+	udelay(500);
+
+	debug("DDR: sdram_cfg   = 0x%08x\n", ddr1->sdram_cfg_1);
+
+
+#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+        debug("DDR: memory initializing\n");
+        /*
+	 * Poll until memory is initialized.
+	 * 512 Meg at 400 might hit this 200 times or so.
+	 */
+	while ((ddr1->sdram_cfg_2 & (d_init << 4)) != 0) {
+		udelay(1000);
+	}
+        debug("DDR: memory initialized\n");
+#endif
+
+
+	/*
+	 * Figure out memory size in Megabytes.
+	 */
+	memsize = n_ranks * rank_density / 0x100000;
+
+
+        /*
+	 * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23.  Fnord.
+	 */
+	law_size = 19 + __ilog2(memsize);
+
+	/*
+	 * Set up LAWBAR for all of DDR.
+	 */
+	mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
+	mcm->lawar1 = (LAWAR_EN
+		       | LAWAR_TRGT_IF_DDR
+		       | (LAWAR_SIZE & law_size));
+	debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1);
+	debug("DDR: LARAR1=0x%08x\n", mcm->lawar1);
+        
+        
+	return memsize * 1024 * 1024;
+}
+
+#endif /* CONFIG_SPD_EEPROM */
+
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+
+/*
+ * Initialize all of memory for ECC, then enable errors.
+ */
+
+void
+ddr_enable_ecc(unsigned int dram_size)
+{
+	uint *p = 0;
+	uint i = 0;
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_ddr_t *ddr1= &immap->im_ddr1;
+
+	dma_init();
+
+	for (*p = 0; p < (uint *)(8 * 1024); p++) {
+		if (((unsigned int)p & 0x1f) == 0) {
+			ppcDcbz((unsigned long) p);
+		}
+		*p = (unsigned int)CONFIG_MEM_INIT_VALUE;
+		if (((unsigned int)p & 0x1c) == 0x1c) {
+			ppcDcbf((unsigned long) p);
+		}
+	}
+
+	/* 8K */
+	dma_xfer((uint *)0x2000, 0x2000, (uint *)0);
+	/* 16K */
+	dma_xfer((uint *)0x4000, 0x4000, (uint *)0);
+	/* 32K */
+	dma_xfer((uint *)0x8000, 0x8000, (uint *)0);
+	/* 64K */
+	dma_xfer((uint *)0x10000, 0x10000, (uint *)0);
+	/* 128k */
+	dma_xfer((uint *)0x20000, 0x20000, (uint *)0);
+	/* 256k */
+	dma_xfer((uint *)0x40000, 0x40000, (uint *)0);
+	/* 512k */
+	dma_xfer((uint *)0x80000, 0x80000, (uint *)0);
+	/* 1M */
+	dma_xfer((uint *)0x100000, 0x100000, (uint *)0);
+	/* 2M */
+	dma_xfer((uint *)0x200000, 0x200000, (uint *)0);
+	/* 4M */
+	dma_xfer((uint *)0x400000, 0x400000, (uint *)0);
+
+	for (i = 1; i < dram_size / 0x800000; i++) {
+		dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
+	}
+
+	/*
+	 * Enable errors for ECC.
+	 */
+	debug("DMA DDR: err_disable = 0x%08x\n", ddr1->err_disable);
+	ddr1->err_disable = 0x00000000;
+	asm("sync;isync;msync");
+	debug("DMA DDR: err_disable = 0x%08x\n", ddr1->err_disable);
+}
+
+#endif	/* CONFIG_DDR_ECC  && ! CONFIG_ECC_INIT_VIA_DDRCONTROLLER */
diff --git a/cpu/mpc86xx/speed.c b/cpu/mpc86xx/speed.c
new file mode 100644
index 0000000..0f5a638
--- /dev/null
+++ b/cpu/mpc86xx/speed.c
@@ -0,0 +1,248 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Jeff Brown (jeffrey@freescale.com)
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc86xx.h>
+#include <asm/processor.h>
+
+unsigned long get_board_sys_clk(ulong dummy);
+unsigned long get_sysclk_from_px_regs(void);
+
+
+/* --------------------------------------------------------------- */
+
+void get_sys_info (sys_info_t * sysInfo)
+{
+	volatile immap_t    *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+	uint plat_ratio, e600_ratio;
+
+       	plat_ratio = (gur->porpllsr) & 0x0000003e;
+	plat_ratio >>= 1;
+	
+	switch(plat_ratio) {
+        case 0x0:
+		sysInfo->freqSystemBus = 16 * CONFIG_SYS_CLK_FREQ;
+		break;
+	case 0x02:
+	case 0x03:
+	case 0x04:
+	case 0x05:
+	case 0x06:
+	case 0x08:
+	case 0x09:
+	case 0x0a:
+	case 0x0c:
+        case 0x10:
+                sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ;
+      	        break;
+	default:
+	        sysInfo->freqSystemBus = 0;
+		break;
+	}
+
+        //        printf("assigned system bus freq = %d for plat ratio 0x%08lx\n", sysInfo->freqSystemBus, plat_ratio);
+	e600_ratio = (gur->porpllsr) & 0x003f0000;
+	e600_ratio >>= 16;
+	switch(e600_ratio) {     
+	case 0x10:
+		sysInfo->freqProcessor = 2*sysInfo->freqSystemBus;
+		break;
+        case 0x19:                
+		sysInfo->freqProcessor = 5*sysInfo->freqSystemBus/2;
+		break;
+	case 0x20:
+		sysInfo->freqProcessor = 3*sysInfo->freqSystemBus;
+		break;
+        case 0x39:
+		sysInfo->freqProcessor = 7*sysInfo->freqSystemBus/2;
+		break;
+	case 0x28:
+		sysInfo->freqProcessor = 4*sysInfo->freqSystemBus;
+		break;
+	case 0x1d:
+		sysInfo->freqProcessor = 9*sysInfo->freqSystemBus/2;
+		break;
+       	default:
+	  /* JB - Emulator workaround until real cop is plugged in */
+	  sysInfo->freqProcessor = e600_ratio + sysInfo->freqSystemBus;
+	  //sysInfo->freqProcessor = 3*sysInfo->freqSystemBus;
+		break;
+	}
+        //        printf("assigned processor freq = %d for e600 ratio 0x%08lx\n", sysInfo->freqProcessor, e600_ratio);
+
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Measure CPU clock speed (core clock GCLK1, GCLK2)
+ *
+ * (Approx. GCLK frequency in Hz)
+ */
+
+int get_clocks (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	sys_info_t sys_info;
+
+	get_sys_info (&sys_info);
+	gd->cpu_clk = sys_info.freqProcessor;
+	gd->bus_clk = sys_info.freqSystemBus;
+	
+	if(gd->cpu_clk != 0) return (0);
+	else return (1);
+}
+
+/* ------------------------------------------------------------------------- */
+/********************************************
+ * get_bus_freq
+ * return system bus freq in Hz
+ *********************************************/
+ulong get_bus_freq (ulong dummy)
+{
+	ulong val;
+
+	sys_info_t sys_info;
+
+	get_sys_info (&sys_info);
+	val = sys_info.freqSystemBus;
+
+	return val;
+}
+
+unsigned long get_sysclk_from_px_regs()
+{
+   ulong val;
+   u8 vclkh,vclkl;
+   
+   vclkh = in8(PIXIS_BASE+PIXIS_VCLKH);
+   vclkl = in8(PIXIS_BASE+PIXIS_VCLKL);
+   
+   if((vclkh == 0x84) && (vclkl ==0x07))
+   {
+      val = 33000000;
+   }
+   if((vclkh == 0x3F) && (vclkl ==0x20))
+   {
+      val = 40000000;
+   }
+   if((vclkh == 0x3F) && (vclkl ==0x2A))
+   {
+      val = 50000000;
+   }
+   if((vclkh == 0x24) && (vclkl ==0x04))
+   {
+      val = 66000000;
+   }
+   if((vclkh == 0x3F) && (vclkl ==0x4B))
+   {
+      val = 83000000;
+   }
+   if((vclkh == 0x3F) && (vclkl ==0x5C))
+   {
+      val = 100000000;
+   }
+   if((vclkh == 0xDF) && (vclkl ==0x3B))
+   {
+      val = 134000000;
+   }
+   if((vclkh == 0xDF) && (vclkl ==0x4B))
+   {
+      val = 166000000;
+   }
+   
+   return val;
+}
+
+/******* From MPC8641HPCN Design Workbook ************
+ *
+ * get_board_sys_clk
+ * reads the FPGA on board for CONFIG_SYS_CLK_FREQ
+ *
+ ********************************************************/
+
+unsigned long get_board_sys_clk(ulong dummy)
+{
+   u8 i, go_bit, rd_clks;
+   ulong val;
+
+   go_bit = in8(PIXIS_BASE+PIXIS_VCTL);
+   go_bit &= 0x01;
+
+   rd_clks = in8(PIXIS_BASE+PIXIS_VCFGEN0);
+   rd_clks &= 0x1C;
+
+   /* Only if both go bit and the SCLK bit in VCFGEN0 are set
+    * should we be using the AUX register. Remember, we also set the
+    * GO bit to boot from the alternate bank on the on-board flash
+    */
+   
+   if(go_bit)
+   {
+      if(rd_clks == 0x1c)
+         i = in8(PIXIS_BASE+PIXIS_AUX);
+      else
+         i = in8(PIXIS_BASE+PIXIS_SPD);
+      //val = get_sysclk_from_px_regs();
+   }
+   else
+      i = in8(PIXIS_BASE+PIXIS_SPD);
+   
+   i &= 0x07;
+      
+   switch(i)
+   {
+      case 0:
+         val = 33000000;
+         break;
+      case 1:
+         val = 40000000;
+         break;
+      case 2:
+         val = 50000000;
+         break;
+      case 3:
+         val = 66000000;
+         break;
+      case 4:
+         val = 83000000;
+         break;
+      case 5:
+         val = 100000000;
+         break;
+      case 6:
+         val = 134000000;
+         break;
+      case 7:
+         val = 166000000;
+         break;
+   }
+   
+   return val;
+}
diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S
new file mode 100644
index 0000000..531bd0c
--- /dev/null
+++ b/cpu/mpc86xx/start.S
@@ -0,0 +1,1240 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Srikanth Srinivasan <srikanth.srinivaan@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*  U-Boot - Startup Code for 86xx PowerPC based Embedded Boards
+ *
+ *
+ *  The processor starts at 0xfff00100 and the code is executed
+ *  from flash. The code is organized to be at an other address
+ *  in memory, but as long we don't jump around before relocating.
+ *  board_init lies at a quite high address and when the cpu has
+ *  jumped there, everything is ok.
+ */
+#include <config.h>
+#include <mpc86xx.h>
+#include <version.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#ifndef  CONFIG_IDENT_STRING
+#define  CONFIG_IDENT_STRING ""
+#endif
+
+/* We don't want the  MMU yet.
+*/
+#undef	MSR_KERNEL
+/* Machine Check and Recoverable Interr. */
+#define MSR_KERNEL ( MSR_ME | MSR_RI )
+
+/*
+ * Set up GOT: Global Offset Table
+ *
+ * Use r14 to access the GOT
+ */
+	START_GOT
+	GOT_ENTRY(_GOT2_TABLE_)
+	GOT_ENTRY(_FIXUP_TABLE_)
+
+	GOT_ENTRY(_start)
+	GOT_ENTRY(_start_of_vectors)
+	GOT_ENTRY(_end_of_vectors)
+	GOT_ENTRY(transfer_to_handler)
+
+	GOT_ENTRY(__init_end)
+	GOT_ENTRY(_end)
+	GOT_ENTRY(__bss_start)
+	END_GOT
+
+/*
+ * r3 - 1st arg to board_init(): IMMP pointer
+ * r4 - 2nd arg to board_init(): boot flag
+ */
+	.text
+	.long	0x27051956		/* U-Boot Magic Number		*/
+	.globl	version_string
+version_string:
+	.ascii	U_BOOT_VERSION
+	.ascii	" (", __DATE__, " - ", __TIME__, ")"
+	.ascii	CONFIG_IDENT_STRING, "\0"
+
+	. = EXC_OFF_SYS_RESET
+	.globl	_start
+_start:
+	li	r21, BOOTFLAG_COLD	/* Normal Power-On: Boot from FLASH */
+	b	boot_cold
+	sync
+
+	. = EXC_OFF_SYS_RESET + 0x10
+
+	.globl	_start_warm
+_start_warm:
+	li	r21, BOOTFLAG_WARM	/* Software reboot		*/
+	b	boot_warm
+	sync
+
+	/* the boot code is located below the exception table */
+
+	.globl	_start_of_vectors
+_start_of_vectors:
+
+/* Machine check */
+	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
+
+/* Data Storage exception. */
+	STD_EXCEPTION(0x300, DataStorage, UnknownException)
+
+/* Instruction Storage exception. */
+	STD_EXCEPTION(0x400, InstStorage, UnknownException)
+
+/* External Interrupt exception. */
+	STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
+
+/* Alignment exception. */
+	. = 0x600
+Alignment:
+	EXCEPTION_PROLOG
+	mfspr	r4,DAR
+	stw	r4,_DAR(r21)
+	mfspr	r5,DSISR
+	stw	r5,_DSISR(r21)
+	addi	r3,r1,STACK_FRAME_OVERHEAD
+	li	r20,MSR_KERNEL
+	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
+	lwz	r6,GOT(transfer_to_handler)
+	mtlr	r6
+	blrl
+.L_Alignment:
+	.long	AlignmentException - _start + EXC_OFF_SYS_RESET
+	.long	int_return - _start + EXC_OFF_SYS_RESET
+
+/* Program check exception */
+	. = 0x700
+ProgramCheck:
+	EXCEPTION_PROLOG
+	addi	r3,r1,STACK_FRAME_OVERHEAD
+	li	r20,MSR_KERNEL
+	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
+	lwz	r6,GOT(transfer_to_handler)
+	mtlr	r6
+	blrl
+.L_ProgramCheck:
+	.long	ProgramCheckException - _start + EXC_OFF_SYS_RESET
+	.long	int_return - _start + EXC_OFF_SYS_RESET
+
+	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
+
+	/* I guess we could implement decrementer, and may have
+	 * to someday for timekeeping.
+	 */
+	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
+	STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
+	STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
+	STD_EXCEPTION(0xc00, SystemCall, UnknownException)
+	STD_EXCEPTION(0xd00, SingleStep, UnknownException)
+	STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
+	STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
+	STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
+	STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
+	STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
+	STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
+	STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
+	STD_EXCEPTION(0x1500, Reserved5, UnknownException)
+	STD_EXCEPTION(0x1600, Reserved6, UnknownException)
+	STD_EXCEPTION(0x1700, Reserved7, UnknownException)
+	STD_EXCEPTION(0x1800, Reserved8, UnknownException)
+	STD_EXCEPTION(0x1900, Reserved9, UnknownException)
+	STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
+	STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
+	STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
+	STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
+	STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
+	STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
+
+	.globl	_end_of_vectors
+_end_of_vectors:
+
+	. = 0x2000
+
+boot_cold:
+boot_warm:
+
+	/* if this is a multi-core system we need to check which cpu
+	 * this is, if it is not cpu 0 send the cpu to the linux reset 
+	 * vector */
+#if (CONFIG_NUM_CPUS > 1)
+	mfspr	r0, MSSCR0
+	andi.	r0, r0, 0x0020
+        rlwinm  r0,r0,27,31,31
+        mtspr	PIR, r0
+	beq	1f
+
+      	bl	secondary_cpu_setup
+#endif
+	
+	/* disable everything */
+1:	li	r0, 0
+	mtspr	HID0, r0
+	sync
+	mtmsr	0
+	bl	invalidate_bats
+	sync
+	
+#ifdef CFG_L2
+	/* init the L2 cache */
+	addis	r3, r0, L2_INIT@h
+	ori	r3, r3, L2_INIT@l
+	sync
+	mtspr	l2cr, r3	
+#ifdef CONFIG_ALTIVEC
+	dssall
+#endif
+	/* invalidate the L2 cache */
+	bl	l2cache_invalidate
+	sync
+#endif
+	
+	/*
+	 * Calculate absolute address in FLASH and jump there
+	 *------------------------------------------------------*/
+	lis	r3, CFG_MONITOR_BASE@h
+	ori	r3, r3, CFG_MONITOR_BASE@l
+	addi	r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
+	mtlr	r3
+	blr
+
+in_flash:
+	/* let the C-code set up the rest			*/
+	/*							*/
+	/* Be careful to keep code relocatable !		*/
+	/*------------------------------------------------------*/
+	/* perform low-level init */
+
+	/* enable extended addressing */
+	bl	enable_ext_addr
+	
+	/* setup the bats */
+	bl	setup_bats
+	sync
+
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+	/* setup ccsrbar */
+	bl	setup_ccsrbar
+#endif
+	
+	/* setup the law entries */
+	bl 	law_entry
+	sync
+
+	/* Don't use this feature due to bug in 8641D PD4 */
+	/* Disable ERD_DIS */
+	lis	r3, CFG_CCSRBAR@h
+	ori	r3, r3, 0x1008
+	lwz	r4, 0(r3)
+	oris	r4, r4, 0x4000
+	stw	r4, 0(r3)
+	sync
+
+#if (EMULATOR_RUN == 1)
+	/* On the emulator we want to adjust these ASAP */
+	/* otherwise things are sloooow */
+	/* Setup OR0 (LALE FIX)*/
+	lis	r3, CFG_CCSRBAR@h
+	ori	r3, r3, 0x5004
+	li	r4, 0x0FF3
+	stw	r4, 0(r3)
+	sync
+
+	/* Setup LCRR */
+	lis	r3, CFG_CCSRBAR@h
+	ori	r3, r3, 0x50D4
+	lis	r4, 0x8000
+	ori	r4, r4, 0x0002
+	stw	r4, 0(r3)
+	sync
+#endif
+#if 1	
+	/* make sure timer enabled in guts register too */
+	lis	r3, CFG_CCSRBAR@h
+	oris	r3,r3, 0xE
+	ori	r3,r3,0x0070  /*Jason from 3*/
+	lwz	r4, 0(r3)
+	lis	r5,0xFFFC     /*Jason from 0xffff*/
+	ori	r5,r5,0x5FFF
+	and	r4,r4,r5
+	stw	r4,0(r3)
+#endif	
+	/*
+	 * Cache must be enabled here for stack-in-cache trick.
+	 * This means we need to enable the BATS.
+	 * Cache should be turned on after BATs, since by default
+	 * everything is write-through.
+	 */
+
+	/* enable address translation */
+	bl	enable_addr_trans
+	sync
+
+	/* enable and invalidate the data cache */
+/*	bl	l1dcache_enable */
+        bl      dcache_enable 
+	sync
+
+#if 1
+	bl	icache_enable
+#endif
+	
+#ifdef CFG_INIT_RAM_LOCK
+	bl	lock_ram_in_cache
+	sync
+#endif
+
+	/* set up the stack pointer in our newly created
+	 * cache-ram (r1) */
+	lis	r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h
+	ori	r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l
+
+	li	r0, 0		/* Make room for stack frame header and	*/
+	stwu	r0, -4(r1)	/* clear final stack frame so that	*/
+	stwu	r0, -4(r1)	/* stack backtraces terminate cleanly	*/
+
+	GET_GOT			/* initialize GOT access	*/
+
+	/* run low-level CPU init code     (from Flash)	*/
+	bl	cpu_init_f
+	sync
+
+#ifdef  RUN_DIAG        
+
+        /* Sri:  Code to run the diagnostic automatically */
+
+        /* Load PX_AUX register address in r4 */
+        lis     r4, 0xf810
+        ori     r4, r4, 0x6
+        /* Load contents of PX_AUX in r3 bits 24 to 31*/
+        lbz     r3, 0(r4)
+
+        /* Mask and obtain the bit in r3 */
+        rlwinm. r3, r3, 0, 24, 24
+        /* If not zero, jump and continue with u-boot */
+        bne     diag_done
+
+        /* Load back contents of PX_AUX in r3 bits 24 to 31 */
+        lbz     r3, 0(r4)
+        /* Set the MSB of the register value */
+        ori     r3, r3, 0x80
+        /* Write value in r3 back to PX_AUX */
+        stb     r3, 0(r4)
+
+        /* Get the address to jump to in r3*/
+        lis     r3, CFG_DIAG_ADDR@h
+        ori     r3, r3, CFG_DIAG_ADDR@l
+
+        /* Load the LR with the branch address */
+        mtlr    r3
+
+        /* Branch to diagnostic */
+        blr
+        
+diag_done:      
+#endif        
+
+  /*      bl      l2cache_enable*/
+        mr	r3, r21
+
+	/* r3: BOOTFLAG */
+	/* run 1st part of board init code (from Flash)   */
+	bl	board_init_f
+	sync
+
+	/* NOTREACHED */
+
+	.globl	invalidate_bats
+invalidate_bats:
+	
+	/* invalidate BATs */
+	mtspr	IBAT0U, r0
+	mtspr	IBAT1U, r0
+	mtspr	IBAT2U, r0
+	mtspr	IBAT3U, r0
+	mtspr   IBAT4U, r0
+	mtspr   IBAT5U, r0
+	mtspr   IBAT6U, r0
+	mtspr   IBAT7U, r0
+
+	isync
+	mtspr	DBAT0U, r0
+	mtspr	DBAT1U, r0
+	mtspr	DBAT2U, r0
+	mtspr	DBAT3U, r0
+	mtspr   DBAT4U, r0
+	mtspr   DBAT5U, r0
+	mtspr   DBAT6U, r0
+	mtspr   DBAT7U, r0
+
+	isync
+	sync
+	blr
+	
+	
+	/* setup_bats - set them up to some initial state */
+	.globl	setup_bats
+setup_bats:
+	
+	addis	r0, r0, 0x0000
+
+	/* IBAT 0 */
+	addis	r4, r0, CFG_IBAT0L@h
+	ori	r4, r4, CFG_IBAT0L@l
+	addis	r3, r0, CFG_IBAT0U@h
+	ori	r3, r3, CFG_IBAT0U@l
+	mtspr	IBAT0L, r4
+	mtspr	IBAT0U, r3
+	isync
+
+	/* DBAT 0 */
+	addis	r4, r0, CFG_DBAT0L@h
+	ori	r4, r4, CFG_DBAT0L@l
+	addis	r3, r0, CFG_DBAT0U@h
+	ori	r3, r3, CFG_DBAT0U@l
+	mtspr	DBAT0L, r4
+	mtspr	DBAT0U, r3
+	isync
+
+	/* IBAT 1 */
+	addis	r4, r0, CFG_IBAT1L@h
+	ori	r4, r4, CFG_IBAT1L@l
+	addis	r3, r0, CFG_IBAT1U@h
+	ori	r3, r3, CFG_IBAT1U@l
+	mtspr	IBAT1L, r4
+	mtspr	IBAT1U, r3
+	isync
+
+	/* DBAT 1 */
+	addis	r4, r0, CFG_DBAT1L@h
+	ori	r4, r4, CFG_DBAT1L@l
+	addis	r3, r0, CFG_DBAT1U@h
+	ori	r3, r3, CFG_DBAT1U@l
+	mtspr	DBAT1L, r4
+	mtspr	DBAT1U, r3
+	isync
+
+	/* IBAT 2 */
+	addis	r4, r0, CFG_IBAT2L@h
+	ori	r4, r4, CFG_IBAT2L@l
+	addis	r3, r0, CFG_IBAT2U@h
+	ori	r3, r3, CFG_IBAT2U@l
+	mtspr	IBAT2L, r4
+	mtspr	IBAT2U, r3
+	isync
+
+	/* DBAT 2 */
+	addis	r4, r0, CFG_DBAT2L@h
+	ori	r4, r4, CFG_DBAT2L@l
+	addis	r3, r0, CFG_DBAT2U@h
+	ori	r3, r3, CFG_DBAT2U@l
+	mtspr	DBAT2L, r4
+	mtspr	DBAT2U, r3
+	isync
+
+	/* IBAT 3 */
+	addis	r4, r0, CFG_IBAT3L@h
+	ori	r4, r4, CFG_IBAT3L@l
+	addis	r3, r0, CFG_IBAT3U@h
+	ori	r3, r3, CFG_IBAT3U@l
+	mtspr	IBAT3L, r4
+	mtspr	IBAT3U, r3
+	isync
+
+	/* DBAT 3 */
+	addis	r4, r0, CFG_DBAT3L@h
+	ori	r4, r4, CFG_DBAT3L@l
+	addis	r3, r0, CFG_DBAT3U@h
+	ori	r3, r3, CFG_DBAT3U@l
+	mtspr	DBAT3L, r4
+	mtspr	DBAT3U, r3
+	isync
+
+	/* IBAT 4 */
+	addis   r4, r0, CFG_IBAT4L@h
+	ori     r4, r4, CFG_IBAT4L@l
+	addis   r3, r0, CFG_IBAT4U@h
+	ori     r3, r3, CFG_IBAT4U@l
+	mtspr   IBAT4L, r4
+	mtspr   IBAT4U, r3
+	isync
+
+	/* DBAT 4 */
+	addis   r4, r0, CFG_DBAT4L@h
+	ori     r4, r4, CFG_DBAT4L@l
+	addis   r3, r0, CFG_DBAT4U@h
+	ori     r3, r3, CFG_DBAT4U@l
+	mtspr   DBAT4L, r4
+	mtspr   DBAT4U, r3
+	isync
+
+	/* IBAT 5 */
+	addis   r4, r0, CFG_IBAT5L@h
+	ori     r4, r4, CFG_IBAT5L@l
+	addis   r3, r0, CFG_IBAT5U@h
+	ori     r3, r3, CFG_IBAT5U@l
+	mtspr   IBAT5L, r4
+	mtspr   IBAT5U, r3
+	isync
+
+	/* DBAT 5 */
+	addis   r4, r0, CFG_DBAT5L@h
+	ori     r4, r4, CFG_DBAT5L@l
+	addis   r3, r0, CFG_DBAT5U@h
+	ori     r3, r3, CFG_DBAT5U@l
+	mtspr   DBAT5L, r4
+	mtspr   DBAT5U, r3
+	isync
+
+	/* IBAT 6 */
+	addis   r4, r0, CFG_IBAT6L@h
+	ori     r4, r4, CFG_IBAT6L@l
+	addis   r3, r0, CFG_IBAT6U@h
+	ori     r3, r3, CFG_IBAT6U@l
+	mtspr   IBAT6L, r4
+	mtspr   IBAT6U, r3
+	isync
+
+	/* DBAT 6 */
+	addis   r4, r0, CFG_DBAT6L@h
+	ori     r4, r4, CFG_DBAT6L@l
+	addis   r3, r0, CFG_DBAT6U@h
+	ori     r3, r3, CFG_DBAT6U@l
+	mtspr   DBAT6L, r4
+	mtspr   DBAT6U, r3
+	isync
+
+	/* IBAT 7 */
+	addis   r4, r0, CFG_IBAT7L@h
+	ori     r4, r4, CFG_IBAT7L@l
+	addis   r3, r0, CFG_IBAT7U@h
+	ori     r3, r3, CFG_IBAT7U@l
+	mtspr   IBAT7L, r4
+	mtspr   IBAT7U, r3
+	isync
+
+	/* DBAT 7 */
+	addis   r4, r0, CFG_DBAT7L@h
+	ori     r4, r4, CFG_DBAT7L@l
+	addis   r3, r0, CFG_DBAT7U@h
+	ori     r3, r3, CFG_DBAT7U@l
+	mtspr   DBAT7L, r4
+	mtspr   DBAT7U, r3
+	isync
+
+1:	
+	addis	r3, 0, 0x0000
+	addis	r5, 0, 0x4    /* upper bound of 0x00040000 for 7400/750 */
+	isync
+
+tlblp:
+	tlbie	r3
+	sync
+	addi	r3, r3, 0x1000
+	cmp	0, 0, r3, r5
+	blt tlblp
+
+	blr
+
+	.globl enable_addr_trans
+enable_addr_trans:
+	/* enable address translation */
+	mfmsr	r5
+	ori	r5, r5, (MSR_IR | MSR_DR)
+	mtmsr	r5
+	isync
+	blr
+
+	.globl disable_addr_trans
+disable_addr_trans:
+	/* disable address translation */
+	mflr	r4
+	mfmsr	r3
+	andi.	r0, r3, (MSR_IR | MSR_DR)
+	beqlr
+	andc	r3, r3, r0
+	mtspr	SRR0, r4
+	mtspr	SRR1, r3
+	rfi
+
+/*
+ * This code finishes saving the registers to the exception frame
+ * and jumps to the appropriate handler for the exception.
+ * Register r21 is pointer into trap frame, r1 has new stack pointer.
+ */
+	.globl	transfer_to_handler
+transfer_to_handler:
+	stw	r22,_NIP(r21)
+	lis	r22,MSR_POW@h
+	andc	r23,r23,r22
+	stw	r23,_MSR(r21)
+	SAVE_GPR(7, r21)
+	SAVE_4GPRS(8, r21)
+	SAVE_8GPRS(12, r21)
+	SAVE_8GPRS(24, r21)
+	mflr	r23
+	andi.	r24,r23,0x3f00		/* get vector offset */
+	stw	r24,TRAP(r21)
+	li	r22,0
+	stw	r22,RESULT(r21)
+	mtspr	SPRG2,r22		/* r1 is now kernel sp */
+	lwz	r24,0(r23)		/* virtual address of handler */
+	lwz	r23,4(r23)		/* where to go when done */
+	mtspr	SRR0,r24
+	mtspr	SRR1,r20
+	mtlr	r23
+	SYNC
+	rfi				/* jump to handler, enable MMU */
+
+int_return:
+	mfmsr	r28		/* Disable interrupts */
+	li	r4,0
+	ori	r4,r4,MSR_EE
+	andc	r28,r28,r4
+	SYNC			/* Some chip revs need this... */
+	mtmsr	r28
+	SYNC
+	lwz	r2,_CTR(r1)
+	lwz	r0,_LINK(r1)
+	mtctr	r2
+	mtlr	r0
+	lwz	r2,_XER(r1)
+	lwz	r0,_CCR(r1)
+	mtspr	XER,r2
+	mtcrf	0xFF,r0
+	REST_10GPRS(3, r1)
+	REST_10GPRS(13, r1)
+	REST_8GPRS(23, r1)
+	REST_GPR(31, r1)
+	lwz	r2,_NIP(r1)	/* Restore environment */
+	lwz	r0,_MSR(r1)
+	mtspr	SRR0,r2
+	mtspr	SRR1,r0
+	lwz	r0,GPR0(r1)
+	lwz	r2,GPR2(r1)
+	lwz	r1,GPR1(r1)
+	SYNC
+	rfi
+
+	.globl	dc_read
+dc_read:
+	blr
+
+	.globl get_pvr
+get_pvr:
+	mfspr	r3, PVR
+	blr
+
+	.globl get_svr
+get_svr:
+	mfspr	r3, SVR
+	blr
+
+
+/*------------------------------------------------------------------------------- */
+/* Function:	 in8 */
+/* Description:	 Input 8 bits */
+/*------------------------------------------------------------------------------- */
+	.globl	in8
+in8:
+	lbz	r3,0x0000(r3)
+	blr
+
+/*------------------------------------------------------------------------------- */
+/* Function:	 out8 */
+/* Description:	 Output 8 bits */
+/*------------------------------------------------------------------------------- */
+	.globl	out8
+out8:
+	stb	r4,0x0000(r3)
+	blr
+
+/*------------------------------------------------------------------------------- */
+/* Function:	 out16 */
+/* Description:	 Output 16 bits */
+/*------------------------------------------------------------------------------- */
+	.globl	out16
+out16:
+	sth	r4,0x0000(r3)
+	blr
+
+/*------------------------------------------------------------------------------- */
+/* Function:	 out16r */
+/* Description:	 Byte reverse and output 16 bits */
+/*------------------------------------------------------------------------------- */
+	.globl	out16r
+out16r:
+	sthbrx	r4,r0,r3
+	blr
+
+/*------------------------------------------------------------------------------- */
+/* Function:	 out32 */
+/* Description:	 Output 32 bits */
+/*------------------------------------------------------------------------------- */
+	.globl	out32
+out32:
+	stw	r4,0x0000(r3)
+	blr
+
+/*------------------------------------------------------------------------------- */
+/* Function:	 out32r */
+/* Description:	 Byte reverse and output 32 bits */
+/*------------------------------------------------------------------------------- */
+	.globl	out32r
+out32r:
+	stwbrx	r4,r0,r3
+	blr
+
+/*------------------------------------------------------------------------------- */
+/* Function:	 in16 */
+/* Description:	 Input 16 bits */
+/*------------------------------------------------------------------------------- */
+	.globl	in16
+in16:
+	lhz	r3,0x0000(r3)
+	blr
+
+/*------------------------------------------------------------------------------- */
+/* Function:	 in16r */
+/* Description:	 Input 16 bits and byte reverse */
+/*------------------------------------------------------------------------------- */
+	.globl	in16r
+in16r:
+	lhbrx	r3,r0,r3
+	blr
+
+/*------------------------------------------------------------------------------- */
+/* Function:	 in32 */
+/* Description:	 Input 32 bits */
+/*------------------------------------------------------------------------------- */
+	.globl	in32
+in32:
+	lwz	3,0x0000(3)
+	blr
+
+/*------------------------------------------------------------------------------- */
+/* Function:	 in32r */
+/* Description:	 Input 32 bits and byte reverse */
+/*------------------------------------------------------------------------------- */
+	.globl	in32r
+in32r:
+	lwbrx	r3,r0,r3
+	blr
+
+/*------------------------------------------------------------------------------- */
+/* Function:	 ppcDcbf */
+/* Description:	 Data Cache block flush */
+/* Input:	 r3 = effective address */
+/* Output:	 none. */
+/*------------------------------------------------------------------------------- */
+	.globl	ppcDcbf
+ppcDcbf:
+	dcbf	r0,r3
+	blr
+
+/*------------------------------------------------------------------------------- */
+/* Function:	 ppcDcbi */
+/* Description:	 Data Cache block Invalidate */
+/* Input:	 r3 = effective address */
+/* Output:	 none. */
+/*------------------------------------------------------------------------------- */
+	.globl	ppcDcbi
+ppcDcbi:
+	dcbi	r0,r3
+	blr
+
+/*--------------------------------------------------------------------------
+ * Function:	 ppcDcbz
+ * Description:	 Data Cache block zero.
+ * Input:	 r3 = effective address
+ * Output:	 none.
+ *-------------------------------------------------------------------------- */
+
+	.globl	ppcDcbz
+ppcDcbz:
+	dcbz	r0,r3
+	blr
+
+/*------------------------------------------------------------------------------- */
+/* Function:	 ppcSync */
+/* Description:	 Processor Synchronize */
+/* Input:	 none. */
+/* Output:	 none. */
+/*------------------------------------------------------------------------------- */
+	.globl	ppcSync
+ppcSync:
+	sync
+	blr
+	
+/*-----------------------------------------------------------------------*/
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * r3 = dest
+ * r4 = src
+ * r5 = length in bytes
+ * r6 = cachelinesize
+ */
+	.globl	relocate_code
+relocate_code:
+
+        mr	r1,  r3		/* Set new stack pointer		*/
+	mr	r9,  r4		/* Save copy of Global Data pointer	*/
+	mr	r10, r5		/* Save copy of Destination Address	*/
+        
+	mr	r3,  r5				/* Destination Address	*/
+	lis	r4, CFG_MONITOR_BASE@h		/* Source      Address	*/
+	ori	r4, r4, CFG_MONITOR_BASE@l
+	lwz	r5, GOT(__init_end)
+	sub	r5, r5, r4
+	li	r6, CFG_CACHELINE_SIZE		/* Cache Line Size	*/
+
+	/*
+	 * Fix GOT pointer:
+	 *
+	 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
+	 *
+	 * Offset:
+	 */
+	sub	r15, r10, r4
+
+	/* First our own GOT */
+	add	r14, r14, r15
+	/* then the one used by the C code */
+	add	r30, r30, r15
+
+	/*
+	 * Now relocate code
+	 */
+#ifdef CONFIG_ECC
+	bl	board_relocate_rom
+	sync
+	mr	r3, r10				/* Destination Address	*/
+	lis	r4, CFG_MONITOR_BASE@h		/* Source      Address	*/
+	ori	r4, r4, CFG_MONITOR_BASE@l
+	lwz	r5, GOT(__init_end)
+	sub	r5, r5, r4
+	li	r6, CFG_CACHELINE_SIZE		/* Cache Line Size	*/
+#else
+	cmplw	cr1,r3,r4
+	addi	r0,r5,3
+	srwi.	r0,r0,2
+	beq	cr1,4f		/* In place copy is not necessary	*/
+	beq	7f		/* Protect against 0 count		*/
+	mtctr	r0
+	bge	cr1,2f
+
+	la	r8,-4(r4)
+	la	r7,-4(r3)
+1:	lwzu	r0,4(r8)
+	stwu	r0,4(r7)
+	bdnz	1b
+	b	4f
+
+2:	slwi	r0,r0,2
+	add	r8,r4,r0
+	add	r7,r3,r0
+3:	lwzu	r0,-4(r8)
+	stwu	r0,-4(r7)
+	bdnz	3b
+#endif
+/*
+ * Now flush the cache: note that we must start from a cache aligned
+ * address. Otherwise we might miss one cache line.
+ */
+4:	cmpwi	r6,0
+	add	r5,r3,r5
+	beq	7f		/* Always flush prefetch queue in any case */
+	subi	r0,r6,1
+	andc	r3,r3,r0
+	mr	r4,r3
+5:	dcbst	0,r4
+	add	r4,r4,r6
+	cmplw	r4,r5
+	blt	5b
+	sync			/* Wait for all dcbst to complete on bus */
+	mr	r4,r3
+6:	icbi	0,r4
+	add	r4,r4,r6
+	cmplw	r4,r5
+	blt	6b
+7:	sync			/* Wait for all icbi to complete on bus	*/
+	isync
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+	addi	r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
+	mtlr	r0
+	blr
+
+in_ram:
+#ifdef CONFIG_ECC
+	bl	board_init_ecc
+#endif
+	/*
+	 * Relocation Function, r14 point to got2+0x8000
+	 *
+	 * Adjust got2 pointers, no need to check for 0, this code
+	 * already puts a few entries in the table.
+	 */
+	li	r0,__got2_entries@sectoff@l
+	la	r3,GOT(_GOT2_TABLE_)
+	lwz	r11,GOT(_GOT2_TABLE_)
+	mtctr	r0
+	sub	r11,r3,r11
+	addi	r3,r3,-4
+1:	lwzu	r0,4(r3)
+	add	r0,r0,r11
+	stw	r0,0(r3)
+	bdnz	1b
+
+	/*
+	 * Now adjust the fixups and the pointers to the fixups
+	 * in case we need to move ourselves again.
+	 */
+2:	li	r0,__fixup_entries@sectoff@l
+	lwz	r3,GOT(_FIXUP_TABLE_)
+	cmpwi	r0,0
+	mtctr	r0
+	addi	r3,r3,-4
+	beq	4f
+3:	lwzu	r4,4(r3)
+	lwzux	r0,r4,r11
+	add	r0,r0,r11
+	stw	r10,0(r3)
+	stw	r0,0(r4)
+	bdnz	3b
+4:
+/* clear_bss: */
+	/*
+	 * Now clear BSS segment
+	 */
+	lwz	r3,GOT(__bss_start)
+	lwz	r4,GOT(_end)
+
+	cmplw	0, r3, r4
+	beq	6f
+
+	li	r0, 0
+5:
+	stw	r0, 0(r3)
+	addi	r3, r3, 4
+	cmplw	0, r3, r4
+	bne	5b
+6:
+	mr	r3, r10		/* Destination Address		*/
+	bl	after_reloc
+
+	/* not reached - end relocate_code */
+/*-----------------------------------------------------------------------*/
+
+	/*
+	 * Copy exception vector code to low memory
+	 *
+	 * r3: dest_addr
+	 * r7: source address, r8: end address, r9: target address
+	 */
+	.globl	trap_init
+trap_init:
+	lwz	r7, GOT(_start)
+	lwz	r8, GOT(_end_of_vectors)
+
+	li	r9, 0x100		/* reset vector always at 0x100 */
+
+	cmplw	0, r7, r8
+	bgelr				/* return if r7>=r8 - just in case */
+
+	mflr	r4			/* save link register		*/
+1:
+	lwz	r0, 0(r7)
+	stw	r0, 0(r9)
+	addi	r7, r7, 4
+	addi	r9, r9, 4
+	cmplw	0, r7, r8
+	bne	1b
+
+	/*
+	 * relocate `hdlr' and `int_return' entries
+	 */
+	li	r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
+	li	r8, Alignment - _start + EXC_OFF_SYS_RESET
+2:
+	bl	trap_reloc
+	addi	r7, r7, 0x100		/* next exception vector	*/
+	cmplw	0, r7, r8
+	blt	2b
+
+	li	r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
+	bl	trap_reloc
+
+	li	r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
+	bl	trap_reloc
+
+	li	r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
+	li	r8, SystemCall - _start + EXC_OFF_SYS_RESET
+3:
+	bl	trap_reloc
+	addi	r7, r7, 0x100		/* next exception vector	*/
+	cmplw	0, r7, r8
+	blt	3b
+
+	li	r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
+	li	r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
+4:
+	bl	trap_reloc
+	addi	r7, r7, 0x100		/* next exception vector	*/
+	cmplw	0, r7, r8
+	blt	4b
+
+	/* enable execptions from RAM vectors */
+	mfmsr	r7
+	li	r8,MSR_IP
+	andc	r7,r7,r8
+	mtmsr	r7
+
+	mtlr	r4			/* restore link register	*/
+	blr
+
+	/*
+	 * Function: relocate entries for one exception vector
+	 */
+trap_reloc:
+	lwz	r0, 0(r7)		/* hdlr ...			*/
+	add	r0, r0, r3		/*  ... += dest_addr		*/
+	stw	r0, 0(r7)
+
+	lwz	r0, 4(r7)		/* int_return ...		*/
+	add	r0, r0, r3		/*  ... += dest_addr		*/
+	stw	r0, 4(r7)
+
+	sync
+	isync
+
+	blr
+
+.globl enable_ext_addr
+enable_ext_addr:
+	mfspr	r0, HID0
+	lis     r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h
+	ori	r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l
+	mtspr   HID0, r0
+	sync
+	isync
+	blr
+
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+.globl setup_ccsrbar
+setup_ccsrbar:		
+	/* Special sequence needed to update CCSRBAR itself */
+	lis	r4, CFG_CCSRBAR_DEFAULT@h
+	ori	r4, r4, CFG_CCSRBAR_DEFAULT@l
+
+	lis   	r5, CFG_CCSRBAR@h
+	ori   	r5, r5, CFG_CCSRBAR@l
+	srwi	r6,r5,12
+	stw	r6, 0(r4)
+	isync
+
+	lis	r5, 0xffff
+	ori	r5,r5,0xf000
+	lwz	r5, 0(r5)
+	isync
+
+	lis	r3, CFG_CCSRBAR@h
+	lwz	r5, CFG_CCSRBAR@l(r3)
+	isync
+	
+	blr
+#endif
+			
+#ifdef CFG_INIT_RAM_LOCK
+lock_ram_in_cache:
+	/* Allocate Initial RAM in data cache.
+	 */
+	lis	r3, (CFG_INIT_RAM_ADDR & ~31)@h
+	ori	r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
+	li	r2, ((CFG_INIT_RAM_END & ~31) + \
+		     (CFG_INIT_RAM_ADDR & 31) + 31) / 32
+	mtctr	r2
+1:
+	dcbz	r0, r3
+	addi	r3, r3, 32
+	bdnz	1b
+#if 1
+/* Lock the data cache */
+	mfspr	r0, HID0
+	ori	r0, r0, 0x1000
+	sync
+	mtspr	HID0, r0
+	sync
+	blr
+#endif
+#if 0
+	/* Lock the first way of the data cache */
+	mfspr	r0, LDSTCR
+	ori	r0, r0, 0x0080
+#if defined(CONFIG_ALTIVEC)
+	dssall
+#endif
+	sync
+	mtspr	LDSTCR, r0
+	sync
+	isync
+	blr
+#endif
+	
+.globl unlock_ram_in_cache
+unlock_ram_in_cache:
+	/* invalidate the INIT_RAM section */
+	lis	r3, (CFG_INIT_RAM_ADDR & ~31)@h
+	ori	r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
+	li	r2, ((CFG_INIT_RAM_END & ~31) + \
+		     (CFG_INIT_RAM_ADDR & 31) + 31) / 32
+	mtctr	r2
+1:	icbi	r0, r3
+	addi	r3, r3, 32
+	bdnz	1b
+	sync			/* Wait for all icbi to complete on bus	*/
+	isync
+#if 1
+/* Unlock the data cache and invalidate it */
+	mfspr   r0, HID0
+	li      r3,0x1000
+	andc    r0,r0,r3
+	li	r3,0x0400
+	or	r0,r0,r3
+	sync
+	mtspr   HID0, r0
+	sync
+	blr
+#endif
+#if 0	
+	/* Unlock the first way of the data cache */
+	mfspr   r0, LDSTCR
+	li      r3,0x0080
+	andc    r0,r0,r3
+#ifdef CONFIG_ALTIVEC
+	dssall
+#endif
+	sync
+	mtspr   LDSTCR, r0
+	sync
+	isync
+	li	r3,0x0400
+	or	r0,r0,r3
+	sync
+	mtspr   HID0, r0
+	sync
+	blr
+#endif
+#endif
+
+/* If this is a multi-cpu system then we need to handle the
+ * 2nd cpu.  The assumption is that the 2nd cpu is being
+ * held in boot holdoff mode until the 1st cpu unlocks it
+ * from Linux.  We'll do some basic cpu init and then pass
+ * it to the Linux Reset Vector.
+ * Sri:  Much of this initialization is not required. Linux
+ * rewrites the bats, and the sprs and also enables the L1 cache.      
+ */
+#if (CONFIG_NUM_CPUS > 1)
+.globl secondary_cpu_setup
+secondary_cpu_setup:	
+	/* Do only core setup on all cores except cpu0 */
+	bl	invalidate_bats
+	sync
+	bl	enable_ext_addr
+	
+#ifdef CFG_L2
+	/* init the L2 cache */
+	addis	r3, r0, L2_INIT@h
+	ori	r3, r3, L2_INIT@l
+	sync
+	mtspr	l2cr, r3
+#ifdef CONFIG_ALTIVEC
+	dssall
+#endif
+	/* invalidate the L2 cache */
+	bl	l2cache_invalidate
+	sync
+#endif
+
+	/* setup the bats */
+	bl	setup_bats
+	sync
+	/* enable address translation */
+	bl	enable_addr_trans
+	sync
+
+	/* enable and invalidate the data cache */
+	bl	dcache_enable
+	sync
+
+        /* enable and invalidate the instruction cache*/
+        bl      icache_enable
+        sync
+        
+        /* Set up MSR and HID0, HID1*/        
+       	/* Enable interrupts */
+/*        mfmsr	r28	
+	 li	r4,0
+	ori	r4,r4,MSR_EE
+        or      r28,r28,r4
+        mtmsr   r28
+  */      
+
+        /* TBEN  in HID0 */
+	mfspr	r4, HID0
+        oris    r4, r4, 0x0400 
+        mtspr   HID0, r4
+        sync
+        isync
+        
+        /*SYNCBE|ABE in HID1*/
+        mfspr	r4, HID1
+        ori     r4, r4, 0x0C00 
+        mtspr   HID1, r4
+        sync
+        isync
+        
+        lis	r3, CONFIG_LINUX_RESET_VEC@h
+	ori	r3, r3, CONFIG_LINUX_RESET_VEC@l
+	mtlr    r3
+	blr
+	
+	/* Never Returns, Running in Linux Now */    
+#endif
+
diff --git a/cpu/mpc86xx/traps.c b/cpu/mpc86xx/traps.c
new file mode 100644
index 0000000..fdfc95d
--- /dev/null
+++ b/cpu/mpc86xx/traps.c
@@ -0,0 +1,253 @@
+/*
+ * linux/arch/ppc/kernel/traps.c
+ *
+ * Copyright (C) 1995-1996  Gary Thomas (gdt@linuxppc.org)
+ *
+ * Modified by Cort Dougan (cort@cs.nmt.edu)
+ * and Paul Mackerras (paulus@cs.anu.edu.au)
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This file handles the architecture-dependent parts of hardware exceptions
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+int (*debugger_exception_handler)(struct pt_regs *) = 0;
+#endif
+
+/* Returns 0 if exception not found and fixup otherwise.  */
+extern unsigned long search_exception_table(unsigned long);
+
+#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize)
+
+/*
+ * Trap & Exception support
+ */
+
+void
+print_backtrace(unsigned long *sp)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	int cnt = 0;
+	unsigned long i;
+
+	printf("Call backtrace: ");
+	while (sp) {
+		if ((uint)sp > END_OF_MEM)
+			break;
+
+		i = sp[1];
+		if (cnt++ % 7 == 0)
+			printf("\n");
+		printf("%08lX ", i);
+		if (cnt > 32) break;
+		sp = (unsigned long *)*sp;
+	}
+	printf("\n");
+}
+
+void
+show_regs(struct pt_regs * regs)
+{
+	int i;
+
+	printf("NIP: %08lX XER: %08lX LR: %08lX REGS:"
+	       " %p TRAP: %04lx DAR: %08lX\n",
+	       regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
+	printf("MSR: %08lx EE: %01x PR: %01x FP:"
+	       " %01x ME: %01x IR/DR: %01x%01x\n",
+	       regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0,
+	       regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0,
+	       regs->msr&MSR_IR ? 1 : 0,
+	       regs->msr&MSR_DR ? 1 : 0);
+
+	printf("\n");
+	for (i = 0;  i < 32;  i++) {
+		if ((i % 8) == 0)
+		{
+			printf("GPR%02d: ", i);
+		}
+
+		printf("%08lX ", regs->gpr[i]);
+		if ((i % 8) == 7)
+		{
+			printf("\n");
+		}
+	}
+}
+
+
+void
+_exception(int signr, struct pt_regs *regs)
+{
+	show_regs(regs);
+	print_backtrace((unsigned long *)regs->gpr[1]);
+	panic("Exception in kernel pc %lx signal %d",regs->nip,signr);
+}
+
+void
+MachineCheckException(struct pt_regs *regs)
+{
+	unsigned long fixup;
+
+	/* Probing PCI using config cycles cause this exception
+	 * when a device is not present.  Catch it and return to
+	 * the PCI exception handler.
+	 */
+	if ((fixup = search_exception_table(regs->nip)) != 0) {
+		regs->nip = fixup;
+		return;
+	}
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+		return;
+#endif
+
+	printf("Machine check in kernel mode.\n");
+	printf("Caused by (from msr): ");
+	printf("regs %p ",regs);
+	switch( regs->msr & 0x000F0000) {
+	case (0x80000000>>12):
+		printf("Machine check signal - probably due to mm fault\n"
+			"with mmu off\n");
+		break;
+	case (0x80000000>>13):
+		printf("Transfer error ack signal\n");
+		break;
+	case (0x80000000>>14):
+		printf("Data parity signal\n");
+		break;
+	case (0x80000000>>15):
+		printf("Address parity signal\n");
+		break;
+	default:
+		printf("Unknown values in msr\n");
+	}
+	show_regs(regs);
+	print_backtrace((unsigned long *)regs->gpr[1]);
+	panic("machine check");
+}
+
+void
+AlignmentException(struct pt_regs *regs)
+{
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+		return;
+#endif
+	show_regs(regs);
+	print_backtrace((unsigned long *)regs->gpr[1]);
+	panic("Alignment Exception");
+}
+
+void
+ProgramCheckException(struct pt_regs *regs)
+{
+	unsigned char *p = regs ? (unsigned char *)(regs->nip) : NULL;
+	int i, j;
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+		return;
+#endif
+	show_regs(regs);
+
+	p = (unsigned char *) ((unsigned long)p & 0xFFFFFFE0);
+	p -= 32;
+	for (i = 0; i < 256; i+=16) {
+		printf("%08x: ", (unsigned int)p+i);
+		for (j = 0; j < 16; j++) {
+			printf("%02x ", p[i+j]);
+		}
+		printf("\n");
+	}
+
+	print_backtrace((unsigned long *)regs->gpr[1]);
+	panic("Program Check Exception");
+}
+
+void
+SoftEmuException(struct pt_regs *regs)
+{
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+		return;
+#endif
+	show_regs(regs);
+	print_backtrace((unsigned long *)regs->gpr[1]);
+	panic("Software Emulation Exception");
+}
+
+
+void
+UnknownException(struct pt_regs *regs)
+{
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+		return;
+#endif
+	printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
+	       regs->nip, regs->msr, regs->trap);
+	_exception(0, regs);
+}
+
+/* Probe an address by reading.  If not present, return -1, otherwise
+ * return 0.
+ */
+int
+addr_probe(uint *addr)
+{
+#if 0
+	int	retval;
+
+	__asm__ __volatile__(			\
+		"1:	lwz %0,0(%1)\n"		\
+		"	eieio\n"		\
+		"	li %0,0\n"		\
+		"2:\n"				\
+		".section .fixup,\"ax\"\n"	\
+		"3:	li %0,-1\n"		\
+		"	b 2b\n"			\
+		".section __ex_table,\"a\"\n"	\
+		"	.align 2\n"		\
+		"	.long 1b,3b\n"		\
+		".text"				\
+		: "=r" (retval) : "r"(addr));
+
+	return (retval);
+#endif
+	return 0;
+}
+
+
+
+
+
+