diff options
| author | Simon Glass <sjg@chromium.org> | 2024-06-27 09:29:48 +0100 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2024-06-28 13:54:52 -0600 |
| commit | 37323aec519e5a6e677bb24b11ff141f69533da3 (patch) | |
| tree | 5fb6f9df34d49f586d1500793e888afc876dfd0f /configs | |
| parent | 024767e66dbe18971e4439b804de96f85462b3e4 (diff) | |
| download | u-boot-37323aec519e5a6e677bb24b11ff141f69533da3.zip u-boot-37323aec519e5a6e677bb24b11ff141f69533da3.tar.gz u-boot-37323aec519e5a6e677bb24b11ff141f69533da3.tar.bz2 | |
rockchip: bob: kevin: Disable dcache in SPL
This causes a hang, so disable it. Unfortunately the RAM-size fix does
not resolve the problem and I am unsure what is wrong. As soon as the
cache is enabled the board appears to hang.
Fixes: 6d8cdfd1536 ("rockchip: spl: Enable caches to speed up checksum validation")
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'configs')
| -rw-r--r-- | configs/chromebook_bob_defconfig | 1 | ||||
| -rw-r--r-- | configs/chromebook_kevin_defconfig | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index acfe393..b2ecfa6 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_TEXT_BASE=0x00200000 diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index 95fdb41..da748e4 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_TEXT_BASE=0x00200000 CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 |