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author | Lokesh Vutla <lokeshvutla@ti.com> | 2019-09-16 13:47:16 +0530 |
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committer | Tom Rini <trini@konsulko.com> | 2019-10-11 13:31:17 -0400 |
commit | 5ebe6c0cb74a93ae75a1dd37e92e3765511f788c (patch) | |
tree | 045ee1211c33a64963d2518791adcd793cfe1ba6 /cmd/ti/ddr3.c | |
parent | ed474ae00c7b2b51fc97b0580d2e52483a657acb (diff) | |
download | u-boot-5ebe6c0cb74a93ae75a1dd37e92e3765511f788c.zip u-boot-5ebe6c0cb74a93ae75a1dd37e92e3765511f788c.tar.gz u-boot-5ebe6c0cb74a93ae75a1dd37e92e3765511f788c.tar.bz2 |
cmd: ti: ddr3: Fix ecc address calculation
ecc_address_range registers contains the start address and end address
of the DDR address space. But the ddr cmd driver is assuming the register
contains the start address and size of the DDR address space. Because
of this some valid ecc addresses are errored out as invalid address.
Fix this calculation.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'cmd/ti/ddr3.c')
-rw-r--r-- | cmd/ti/ddr3.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/cmd/ti/ddr3.c b/cmd/ti/ddr3.c index b82cbe1..34f870a 100644 --- a/cmd/ti/ddr3.c +++ b/cmd/ti/ddr3.c @@ -242,8 +242,8 @@ static int is_addr_valid(u32 addr) if (ecc_ctrl & EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK) { start_addr = ((range & EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16) + CONFIG_SYS_SDRAM_BASE; - end_addr = start_addr + (range & EMIF_ECC_REG_ECC_END_ADDR_MASK) - + 0xFFFF; + end_addr = (range & EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0xFFFF + + CONFIG_SYS_SDRAM_BASE; if ((addr >= start_addr) && (addr <= end_addr)) /* addr within ecc address range 1 */ return 1; @@ -254,8 +254,8 @@ static int is_addr_valid(u32 addr) range = readl(&emif->emif_ecc_address_range_2); start_addr = ((range & EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16) + CONFIG_SYS_SDRAM_BASE; - end_addr = start_addr + (range & EMIF_ECC_REG_ECC_END_ADDR_MASK) - + 0xFFFF; + end_addr = (range & EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0xFFFF + + CONFIG_SYS_SDRAM_BASE; if ((addr >= start_addr) && (addr <= end_addr)) /* addr within ecc address range 2 */ return 1; |