arm: Remove platinum_picon board

This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it.

Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>

9 files changed, 0 insertions, 1168 deletions

diff --git a/board/barco/platinum/Kconfig b/board/barco/platinum/Kconfig
deleted file mode 100644
index cc0648c..0000000
--- a/board/barco/platinum/Kconfig
+++ /dev/null
@@ -1,31 +0,0 @@
-if TARGET_PLATINUM_PICON
-
-config SYS_CPU
-	default "armv7"
-
-config SYS_VENDOR
-	default "barco"
-
-config SYS_BOARD
-	default "platinum"
-
-config SYS_CONFIG_NAME
-	default "platinum_picon"
-
-endif
-
-if TARGET_PLATINUM_TITANIUM
-
-config SYS_CPU
-	default "armv7"
-
-config SYS_VENDOR
-	default "barco"
-
-config SYS_BOARD
-	default "platinum"
-
-config SYS_CONFIG_NAME
-	default "platinum_titanium"
-
-endif
diff --git a/board/barco/platinum/MAINTAINERS b/board/barco/platinum/MAINTAINERS
deleted file mode 100644
index a22584b..0000000
--- a/board/barco/platinum/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-PLATINUM BOARD
-M:	Stefan Roese <sr@denx.de>
-S:	Maintained
-F:	board/barco/platinum/
-F:	include/configs/platinum.h
-F:	configs/platinum_picon_defconfig
-F:	configs/platinum_titanium_defconfig
diff --git a/board/barco/platinum/Makefile b/board/barco/platinum/Makefile
deleted file mode 100644
index 1e1bf10..0000000
--- a/board/barco/platinum/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2014, Barco (www.barco.com)
-
-obj-y := platinum.o
-obj-$(CONFIG_TARGET_PLATINUM_PICON)     += platinum_picon.o
-obj-$(CONFIG_TARGET_PLATINUM_TITANIUM)  += platinum_titanium.o
-
-ifneq ($(CONFIG_SPL_BUILD),)
-obj-$(CONFIG_TARGET_PLATINUM_PICON) += spl_picon.o
-obj-$(CONFIG_TARGET_PLATINUM_TITANIUM) += spl_titanium.o
-endif
diff --git a/board/barco/platinum/platinum.c b/board/barco/platinum/platinum.c
deleted file mode 100644
index ec8d552..0000000
--- a/board/barco/platinum/platinum.c
+++ /dev/null
@@ -1,219 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2014, Barco (www.barco.com)
- * Copyright (C) 2014 Stefan Roese <sr@denx.de>
- */
-
-#include <common.h>
-#include <init.h>
-#include <mmc.h>
-#include <fsl_esdhc_imx.h>
-#include <miiphy.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-pins.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/boot_mode.h>
-
-#include "platinum.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-iomux_v3_cfg_t const usdhc3_pads[] = {
-	MX6_PAD_SD3_CLK__SD3_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_CMD__SD3_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT0__SD3_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT1__SD3_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT2__SD3_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT3__SD3_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT5__GPIO7_IO00	| MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
-};
-
-iomux_v3_cfg_t nfc_pads[] = {
-	MX6_PAD_NANDF_CLE__NAND_CLE		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_ALE__NAND_ALE		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_WP_B__NAND_WP_B		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_RB0__NAND_READY_B		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_CS0__NAND_CE0_B		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_CS1__NAND_CE1_B		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_CS2__NAND_CE2_B		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_CS3__NAND_CE3_B		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_SD4_CMD__NAND_RE_B		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_SD4_CLK__NAND_WE_B		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_D0__NAND_DATA00		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_D1__NAND_DATA01		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_D2__NAND_DATA02		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_D3__NAND_DATA03		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_D4__NAND_DATA04		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_D5__NAND_DATA05		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_D6__NAND_DATA06		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_D7__NAND_DATA07		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_SD4_DAT0__NAND_DQS		| MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-struct fsl_esdhc_cfg usdhc_cfg[] = {
-	{ USDHC3_BASE_ADDR },
-};
-
-void setup_gpmi_nand(void)
-{
-	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
-	/* config gpmi nand iomux */
-	imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
-
-	/* config gpmi and bch clock to 100 MHz */
-	clrsetbits_le32(&mxc_ccm->cs2cdr,
-			MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
-			MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
-			MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
-			MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
-			MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
-			MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
-
-	/* enable gpmi and bch clock gating */
-	setbits_le32(&mxc_ccm->CCGR4,
-		     MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
-		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
-		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
-		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
-		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
-
-	/* enable apbh clock gating */
-	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
-}
-
-int dram_init(void)
-{
-	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
-
-	return 0;
-}
-
-int board_ehci_hcd_init(int port)
-{
-	return 0;
-}
-
-int board_mmc_getcd(struct mmc *mmc)
-{
-	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-
-	if (cfg->esdhc_base == usdhc_cfg[0].esdhc_base) {
-		unsigned sd3_cd = IMX_GPIO_NR(7, 0);
-		gpio_direction_input(sd3_cd);
-		return !gpio_get_value(sd3_cd);
-	}
-
-	return 0;
-}
-
-int board_mmc_init(struct bd_info *bis)
-{
-	imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
-	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-
-	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
-}
-
-void board_init_gpio(void)
-{
-	platinum_init_gpio();
-}
-
-void board_init_gpmi_nand(void)
-{
-	setup_gpmi_nand();
-}
-
-void board_init_i2c(void)
-{
-	platinum_setup_i2c();
-}
-
-void board_init_spi(void)
-{
-	platinum_setup_spi();
-}
-
-void board_init_uart(void)
-{
-	platinum_setup_uart();
-}
-
-void board_init_usb(void)
-{
-	platinum_init_usb();
-}
-
-void board_init_finished(void)
-{
-	platinum_init_finished();
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
-	return platinum_phy_config(phydev);
-}
-
-int board_eth_init(struct bd_info *bis)
-{
-	return cpu_eth_init(bis);
-}
-
-int board_early_init_f(void)
-{
-	board_init_uart();
-
-	return 0;
-}
-
-int board_init(void)
-{
-	/* address of boot parameters */
-	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
-	board_init_spi();
-
-	board_init_i2c();
-
-	board_init_gpmi_nand();
-
-	board_init_gpio();
-
-	board_init_usb();
-
-	board_init_finished();
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	puts("Board: " CONFIG_PLATINUM_BOARD "\n");
-	return 0;
-}
-
-static const struct boot_mode board_boot_modes[] = {
-	/* NAND */
-	{ "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
-	/* 4 bit bus width */
-	{ "mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00) },
-	{ "mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00) },
-	{ NULL, 0 },
-};
-
-int misc_init_r(void)
-{
-	add_board_boot_modes(board_boot_modes);
-
-	return 0;
-}
diff --git a/board/barco/platinum/platinum.h b/board/barco/platinum/platinum.h
deleted file mode 100644
index 9988cae..0000000
--- a/board/barco/platinum/platinum.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2014 Stefan Roese <sr@denx.de>
- */
-
-#ifndef _PLATINUM_H_
-#define _PLATINUM_H_
-
-#include <miiphy.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/io.h>
-
-/* Defines */
-
-#define ECSPI1_PAD_CLK		(PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_DOWN | \
-				 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
-				 PAD_CTL_HYS)
-#define ECSPI2_PAD_CLK		(PAD_CTL_SRE_FAST | PAD_CTL_PUS_100K_DOWN | \
-				 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
-				 PAD_CTL_HYS)
-#define ECSPI_PAD_MOSI		(PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_DOWN | \
-				 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_120ohm | \
-				 PAD_CTL_HYS)
-#define ECSPI_PAD_MISO		(PAD_CTL_SRE_FAST | PAD_CTL_PUS_100K_DOWN | \
-				 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
-				 PAD_CTL_HYS)
-#define ECSPI_PAD_SS		(PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_UP | \
-				 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_120ohm | \
-				 PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL		(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
-				 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define I2C_PAD_CTRL		(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
-				 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
-				 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-#define I2C_PAD_CTRL_SCL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
-				 PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \
-				 PAD_CTL_ODE | PAD_CTL_SRE_SLOW)
-
-#define UART_PAD_CTRL		(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
-				 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | \
-				 PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL		(PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW | \
-				PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \
-				PAD_CTL_HYS)
-
-
-#define PC			MUX_PAD_CTRL(I2C_PAD_CTRL)
-#define PC_SCL			MUX_PAD_CTRL(I2C_PAD_CTRL_SCL)
-
-/* Prototypes */
-
-int platinum_setup_enet(void);
-int platinum_setup_i2c(void);
-int platinum_setup_spi(void);
-int platinum_setup_uart(void);
-int platinum_phy_config(struct phy_device *phydev);
-int platinum_init_gpio(void);
-int platinum_init_usb(void);
-int platinum_init_finished(void);
-
-static inline void ccgr_init(void)
-{
-	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
-	writel(0x00C03F3F, &ccm->CCGR0);
-	writel(0x0030FC03, &ccm->CCGR1);
-	writel(0x0FFFC000, &ccm->CCGR2);
-	writel(0x3FF00000, &ccm->CCGR3);
-	writel(0xFFFFF300, &ccm->CCGR4);	/* enable NAND/GPMI/BCH clks */
-	writel(0x0F0000C3, &ccm->CCGR5);
-	writel(0x000003FF, &ccm->CCGR6);
-}
-
-#endif /* _PLATINUM_H_ */
diff --git a/board/barco/platinum/platinum_picon.c b/board/barco/platinum/platinum_picon.c
deleted file mode 100644
index 3fc29f9..0000000
--- a/board/barco/platinum/platinum_picon.c
+++ /dev/null
@@ -1,244 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2014, Barco (www.barco.com)
- * Copyright (C) 2014 Stefan Roese <sr@denx.de>
- */
-
-#include <common.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-pins.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <linux/delay.h>
-
-#include "platinum.h"
-
-#define GPIO_IP_NCONFIG		IMX_GPIO_NR(5, 18)
-#define GPIO_HK_NCONFIG		IMX_GPIO_NR(7, 13)
-#define GPIO_LS_NCONFIG		IMX_GPIO_NR(5, 19)
-
-#define GPIO_I2C0_SEL0		IMX_GPIO_NR(5,  2)
-#define GPIO_I2C0_SEL1		IMX_GPIO_NR(1, 11)
-#define GPIO_I2C0_ENBN		IMX_GPIO_NR(1, 13)
-
-#define GPIO_I2C2_SEL0		IMX_GPIO_NR(1, 17)
-#define GPIO_I2C2_SEL1		IMX_GPIO_NR(1, 20)
-#define GPIO_I2C2_ENBN		IMX_GPIO_NR(1, 14)
-
-#define GPIO_USB_RESET		IMX_GPIO_NR(1,  5)
-
-iomux_v3_cfg_t const ecspi1_pads[] = {
-	MX6_PAD_EIM_D16__ECSPI1_SCLK		| MUX_PAD_CTRL(ECSPI1_PAD_CLK),
-	MX6_PAD_EIM_D17__ECSPI1_MISO		| MUX_PAD_CTRL(ECSPI_PAD_MISO),
-	MX6_PAD_EIM_D18__ECSPI1_MOSI		| MUX_PAD_CTRL(ECSPI_PAD_MOSI),
-	MX6_PAD_CSI0_DAT7__ECSPI1_SS0		| MUX_PAD_CTRL(ECSPI_PAD_SS),
-	MX6_PAD_EIM_D24__ECSPI1_SS2		| MUX_PAD_CTRL(ECSPI_PAD_SS),
-	MX6_PAD_EIM_D25__ECSPI1_SS3		| MUX_PAD_CTRL(ECSPI_PAD_SS),
-};
-
-iomux_v3_cfg_t const ecspi2_pads[] = {
-	MX6_PAD_EIM_CS0__ECSPI2_SCLK		| MUX_PAD_CTRL(ECSPI2_PAD_CLK),
-	MX6_PAD_EIM_OE__ECSPI2_MISO		| MUX_PAD_CTRL(ECSPI_PAD_MISO),
-	MX6_PAD_EIM_CS1__ECSPI2_MOSI		| MUX_PAD_CTRL(ECSPI_PAD_MOSI),
-	MX6_PAD_EIM_RW__ECSPI2_SS0		| MUX_PAD_CTRL(ECSPI_PAD_SS),
-	MX6_PAD_EIM_LBA__ECSPI2_SS1		| MUX_PAD_CTRL(ECSPI_PAD_SS),
-};
-
-iomux_v3_cfg_t const enet_pads[] = {
-	MX6_PAD_ENET_MDIO__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_CRS_DV__ENET_RX_EN		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_GPIO_16__ENET_REF_CLK		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_RX_ER__ENET_RX_ER		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_RXD0__ENET_RX_DATA0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_RXD1__ENET_RX_DATA1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_TX_EN__ENET_TX_EN		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_TXD0__ENET_TX_DATA0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_TXD1__ENET_TX_DATA1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-};
-
-/* PHY nRESET */
-iomux_v3_cfg_t const phy_reset_pad = {
-	MX6_PAD_SD1_DAT2__GPIO1_IO19		| MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-iomux_v3_cfg_t const uart1_pads[] = {
-	MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-iomux_v3_cfg_t const uart4_pads[] = {
-	MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_CSI0_DAT16__UART4_RTS_B   | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_CSI0_DAT17__UART4_CTS_B   | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-iomux_v3_cfg_t const uart5_pads[] = {
-	MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_CSI0_DAT18__UART5_RTS_B   | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_CSI0_DAT19__UART5_CTS_B   | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-iomux_v3_cfg_t const i2c0_mux_pads[] = {
-	MX6_PAD_EIM_A25__GPIO5_IO02		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_SD2_CMD__GPIO1_IO11		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_SD2_DAT2__GPIO1_IO13		| MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-iomux_v3_cfg_t const i2c2_mux_pads[] = {
-	MX6_PAD_SD1_DAT1__GPIO1_IO17		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_SD1_CLK__GPIO1_IO20		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_SD2_DAT1__GPIO1_IO14		| MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-struct i2c_pads_info i2c_pad_info0 = {
-	.scl = {
-		.i2c_mode  = MX6_PAD_CSI0_DAT9__I2C1_SCL	| PC_SCL,
-		.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27	| PC_SCL,
-		.gp = IMX_GPIO_NR(5, 27)
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA		| PC,
-		.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26	| PC,
-		.gp = IMX_GPIO_NR(5, 26)
-	 }
-};
-
-struct i2c_pads_info i2c_pad_info2 = {
-	.scl = {
-		.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL		| PC_SCL,
-		.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03		| PC_SCL,
-		.gp = IMX_GPIO_NR(1, 3)
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA		| PC,
-		.gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06		| PC,
-		.gp = IMX_GPIO_NR(1, 6)
-	 }
-};
-
-/*
- * This enet related pin-muxing and GPIO handling is done
- * in SPL U-Boot. For early initialization. And to give the
- * PHY some time to come out of reset before the U-Boot
- * ethernet driver tries to access its registers via MDIO.
- */
-int platinum_setup_enet(void)
-{
-	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-	unsigned phy_reset = IMX_GPIO_NR(1, 19);
-
-	/* First configure PHY reset GPIO pin */
-	imx_iomux_v3_setup_pad(phy_reset_pad);
-
-	/* Reconfigure enet muxing while PHY is in reset */
-	gpio_direction_output(phy_reset, 0);
-	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
-	mdelay(10);
-	gpio_set_value(phy_reset, 1);
-	udelay(100);
-
-	/* set GPIO_16 as ENET_REF_CLK_OUT */
-	setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
-
-	return enable_fec_anatop_clock(0, ENET_50MHZ);
-}
-
-int platinum_setup_i2c(void)
-{
-	imx_iomux_v3_setup_multiple_pads(i2c0_mux_pads,
-					 ARRAY_SIZE(i2c0_mux_pads));
-	imx_iomux_v3_setup_multiple_pads(i2c2_mux_pads,
-					 ARRAY_SIZE(i2c2_mux_pads));
-
-	mdelay(10);
-
-	/* Disable i2c mux 0 */
-	gpio_direction_output(GPIO_I2C0_SEL0, 0);
-	gpio_direction_output(GPIO_I2C0_SEL1, 0);
-	gpio_direction_output(GPIO_I2C0_ENBN, 1);
-
-	/* Disable i2c mux 1 */
-	gpio_direction_output(GPIO_I2C2_SEL0, 0);
-	gpio_direction_output(GPIO_I2C2_SEL1, 0);
-	gpio_direction_output(GPIO_I2C2_ENBN, 1);
-
-	udelay(10);
-
-	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
-	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
-
-	/* Disable all leds */
-	i2c_set_bus_num(0);
-	i2c_reg_write(0x60, 0x05, 0x55);
-
-	return 0;
-}
-
-int platinum_setup_spi(void)
-{
-	imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
-	imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads));
-
-	return 0;
-}
-
-int platinum_setup_uart(void)
-{
-	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
-	imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
-	imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
-
-	return 0;
-}
-
-int platinum_phy_config(struct phy_device *phydev)
-{
-	/* Use generic infrastructure, no specific setup */
-	if (phydev->drv->config)
-		phydev->drv->config(phydev);
-
-	return 0;
-}
-
-int platinum_init_gpio(void)
-{
-	/* Reset FPGA's */
-	gpio_direction_output(GPIO_IP_NCONFIG, 0);
-	gpio_direction_output(GPIO_HK_NCONFIG, 0);
-	gpio_direction_output(GPIO_LS_NCONFIG, 0);
-	udelay(3);
-	gpio_set_value(GPIO_IP_NCONFIG, 1);
-	gpio_set_value(GPIO_HK_NCONFIG, 1);
-	gpio_set_value(GPIO_LS_NCONFIG, 1);
-
-	/* no dmd configuration yet */
-
-	return 0;
-}
-
-int platinum_init_usb(void)
-{
-	/* Reset usb hub */
-	gpio_direction_output(GPIO_USB_RESET, 0);
-	udelay(100);
-	gpio_set_value(GPIO_USB_RESET, 1);
-
-	return 0;
-}
-
-int platinum_init_finished(void)
-{
-	/* Enable led 0 */
-	i2c_set_bus_num(0);
-	i2c_reg_write(0x60, 0x05, 0x54);
-
-	return 0;
-}
diff --git a/board/barco/platinum/platinum_titanium.c b/board/barco/platinum/platinum_titanium.c
deleted file mode 100644
index 9f7c93b..0000000
--- a/board/barco/platinum/platinum_titanium.c
+++ /dev/null
@@ -1,209 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2014, Barco (www.barco.com)
- * Copyright (C) 2014 Stefan Roese <sr@denx.de>
- */
-
-#include <common.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-pins.h>
-#include <asm/gpio.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <miiphy.h>
-#include <micrel.h>
-#include <linux/delay.h>
-
-#include "platinum.h"
-
-iomux_v3_cfg_t const ecspi1_pads[] = {
-	MX6_PAD_EIM_D16__ECSPI1_SCLK		| MUX_PAD_CTRL(ECSPI1_PAD_CLK),
-	MX6_PAD_EIM_D17__ECSPI1_MISO		| MUX_PAD_CTRL(ECSPI_PAD_MISO),
-	MX6_PAD_EIM_D18__ECSPI1_MOSI		| MUX_PAD_CTRL(ECSPI_PAD_MOSI),
-	MX6_PAD_CSI0_DAT7__ECSPI1_SS0		| MUX_PAD_CTRL(ECSPI_PAD_SS),
-	/* non mounted spi nor flash for booting */
-	MX6_PAD_EIM_D19__ECSPI1_SS1		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_EIM_D24__ECSPI1_SS2		| MUX_PAD_CTRL(ECSPI_PAD_SS),
-	MX6_PAD_EIM_D25__ECSPI1_SS3		| MUX_PAD_CTRL(ECSPI_PAD_SS),
-};
-
-iomux_v3_cfg_t const ecspi2_pads[] = {
-	MX6_PAD_EIM_CS0__ECSPI2_SCLK		| MUX_PAD_CTRL(ECSPI2_PAD_CLK),
-	MX6_PAD_EIM_OE__ECSPI2_MISO		| MUX_PAD_CTRL(ECSPI_PAD_MISO),
-	MX6_PAD_EIM_CS1__ECSPI2_MOSI		| MUX_PAD_CTRL(ECSPI_PAD_MOSI),
-	MX6_PAD_EIM_RW__ECSPI2_SS0		| MUX_PAD_CTRL(ECSPI_PAD_SS),
-};
-
-iomux_v3_cfg_t const enet_pads1[] = {
-	MX6_PAD_ENET_MDIO__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TXC__RGMII_TXC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD0__RGMII_TD0		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD1__RGMII_TD1		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD2__RGMII_TD2		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD3__RGMII_TD3		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	/* pin 35 - 1 (PHY_AD2) on reset */
-	MX6_PAD_RGMII_RXC__GPIO6_IO30		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* pin 32 - 1 - (MODE0) all */
-	MX6_PAD_RGMII_RD0__GPIO6_IO25		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* pin 31 - 1 - (MODE1) all */
-	MX6_PAD_RGMII_RD1__GPIO6_IO27		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* pin 28 - 1 - (MODE2) all */
-	MX6_PAD_RGMII_RD2__GPIO6_IO28		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* pin 27 - 1 - (MODE3) all */
-	MX6_PAD_RGMII_RD3__GPIO6_IO29		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
-	MX6_PAD_RGMII_RX_CTL__GPIO6_IO24	| MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* pin 42 PHY nRST */
-	MX6_PAD_EIM_D23__GPIO3_IO23		| MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-iomux_v3_cfg_t const enet_pads2[] = {
-	MX6_PAD_RGMII_RXC__RGMII_RXC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD0__RGMII_RD0		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD1__RGMII_RD1		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD2__RGMII_RD2		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD3__RGMII_RD3		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-};
-
-iomux_v3_cfg_t const uart1_pads[] = {
-	MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-iomux_v3_cfg_t const uart2_pads[] = {
-	MX6_PAD_EIM_D26__UART2_TX_DATA   | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_EIM_D27__UART2_RX_DATA   | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_EIM_D28__UART2_DTE_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_EIM_D29__UART2_RTS_B     | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-iomux_v3_cfg_t const uart4_pads[] = {
-	MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_CSI0_DAT16__UART4_RTS_B   | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_CSI0_DAT17__UART4_CTS_B   | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-struct i2c_pads_info i2c_pad_info0 = {
-	.scl = {
-		.i2c_mode  = MX6_PAD_CSI0_DAT9__I2C1_SCL	| PC_SCL,
-		.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27	| PC_SCL,
-		.gp = IMX_GPIO_NR(5, 27)
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA		| PC,
-		.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26	| PC,
-		.gp = IMX_GPIO_NR(5, 26)
-	 }
-};
-
-struct i2c_pads_info i2c_pad_info2 = {
-	.scl = {
-		.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL		| PC_SCL,
-		.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03		| PC_SCL,
-		.gp = IMX_GPIO_NR(1, 3)
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA		| PC,
-		.gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11	| PC,
-		.gp = IMX_GPIO_NR(7, 11)
-	 }
-};
-
-/*
- * This enet related pin-muxing and GPIO handling is done
- * in SPL U-Boot. For early initialization. And to give the
- * PHY some time to come out of reset before the U-Boot
- * ethernet driver tries to access its registers via MDIO.
- */
-int platinum_setup_enet(void)
-{
-	gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
-	gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
-	gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
-	gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
-	gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
-	gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
-	imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
-	gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
-
-	/* Need delay 10ms according to KSZ9021 spec */
-	mdelay(10);
-	gpio_set_value(IMX_GPIO_NR(3, 23), 1);
-	udelay(100);
-
-	imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
-
-	return 0;
-}
-
-int platinum_setup_i2c(void)
-{
-	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
-	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
-
-	return 0;
-}
-
-int platinum_setup_spi(void)
-{
-	imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
-	imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads));
-
-	return 0;
-}
-
-int platinum_setup_uart(void)
-{
-	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
-	imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
-	imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
-
-	return 0;
-}
-
-int platinum_phy_config(struct phy_device *phydev)
-{
-	/* min rx data delay */
-	ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
-				   0x0);
-	/* min tx data delay */
-	ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
-				   0x0);
-	/* max rx/tx clock delay, min rx/tx control */
-	ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
-				   0xf0f0);
-	if (phydev->drv->config)
-		phydev->drv->config(phydev);
-
-	return 0;
-}
-
-int platinum_init_gpio(void)
-{
-	/* Default GPIO's */
-	/* Toggle CONFIG_n to reset fpga on every boot */
-	gpio_direction_output(IMX_GPIO_NR(5, 18), 0);
-	/* Need delay >=2uS */
-	udelay(3);
-	gpio_set_value(IMX_GPIO_NR(5, 18), 1);
-
-	/* Default pin 1,15 high - DLP_FLASH_WPZ */
-	gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
-
-	return 0;
-}
-
-int platinum_init_usb(void)
-{
-	return 0;
-}
-
-int platinum_init_finished(void)
-{
-	return 0;
-}
diff --git a/board/barco/platinum/spl_picon.c b/board/barco/platinum/spl_picon.c
deleted file mode 100644
index 253a64d..0000000
--- a/board/barco/platinum/spl_picon.c
+++ /dev/null
@@ -1,183 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2014 Stefan Roese <sr@denx.de>
- *
- * Based on: gw_ventana_spl.c which is:
- * Copyright (C) 2014 Gateworks Corporation
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <init.h>
-#include <asm/io.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-ddr.h>
-#include <asm/arch/mx6-pins.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/mach-imx/boot_mode.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <spl.h>
-
-#include "platinum.h"
-
-#undef RTT_NOM_120OHM	/* use 120ohm Rtt_nom vs 60ohm (lower power) */
-
-/* Configure MX6Q/DUAL mmdc DDR io registers */
-struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
-	/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
-	.dram_sdclk_0 = 0x00020030,
-	.dram_sdclk_1 = 0x00020030,
-	.dram_cas = 0x00020030,
-	.dram_ras = 0x00020030,
-	.dram_reset = 0x00020030,
-	/* SDCKE[0:1]: 100k pull-up */
-	.dram_sdcke0 = 0x00003000,
-	.dram_sdcke1 = 0x00003000,
-	/* SDBA2: pull-up disabled */
-	.dram_sdba2 = 0x00000000,
-	/* SDODT[0:1]: 100k pull-up, 40 ohm */
-	.dram_sdodt0 = 0x00003030,
-	.dram_sdodt1 = 0x00003030,
-	/* SDQS[0:7]: Differential input, 40 ohm */
-	.dram_sdqs0 = 0x00000030,
-	.dram_sdqs1 = 0x00000030,
-	.dram_sdqs2 = 0x00000030,
-	.dram_sdqs3 = 0x00000030,
-	.dram_sdqs4 = 0x00000030,
-	.dram_sdqs5 = 0x00000030,
-	.dram_sdqs6 = 0x00000030,
-	.dram_sdqs7 = 0x00000030,
-	/* DQM[0:7]: Differential input, 40 ohm */
-	.dram_dqm0 = 0x00020030,
-	.dram_dqm1 = 0x00020030,
-	.dram_dqm2 = 0x00020030,
-	.dram_dqm3 = 0x00020030,
-	.dram_dqm4 = 0x00020030,
-	.dram_dqm5 = 0x00020030,
-	.dram_dqm6 = 0x00020030,
-	.dram_dqm7 = 0x00020030,
-};
-
-/* Configure MX6Q/DUAL mmdc GRP io registers */
-struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
-	/* DDR3 */
-	.grp_ddr_type = 0x000c0000,
-	.grp_ddrmode_ctl = 0x00020000,
-	/* disable DDR pullups */
-	.grp_ddrpke = 0x00000000,
-	/* ADDR[00:16], SDBA[0:1]: 40 ohm */
-	.grp_addds = 0x00000030,
-	/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
-	.grp_ctlds = 0x00000030,
-	/* DATA[00:63]: Differential input, 40 ohm */
-	.grp_ddrmode = 0x00020000,
-	.grp_b0ds = 0x00000030,
-	.grp_b1ds = 0x00000030,
-	.grp_b2ds = 0x00000030,
-	.grp_b3ds = 0x00000030,
-	.grp_b4ds = 0x00000030,
-	.grp_b5ds = 0x00000030,
-	.grp_b6ds = 0x00000030,
-	.grp_b7ds = 0x00000030,
-};
-
-/* MT41K256M16HA-125 */
-static struct mx6_ddr3_cfg mt41k256m16ha_125 = {
-	.mem_speed = 1600,
-	.density = 4,		/* 4Gbit */
-	.width = 16,
-	.banks = 8,
-	.rowaddr = 15,
-	.coladdr = 10,
-	.pagesz = 2,
-	.trcd = 1375,
-	.trcmin = 4875,
-	.trasmin = 3500,
-};
-
-/*
- * Values from running the Freescale DDR stress tool via USB
- */
-static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
-	/* write leveling calibration determine */
-	.p0_mpwldectrl0 = 0x0044004E,
-	.p0_mpwldectrl1 = 0x001F0023,
-	/* Read DQS Gating calibration */
-	.p0_mpdgctrl0 = 0x02480248,
-	.p0_mpdgctrl1 = 0x0210021C,
-	/* Read Calibration: DQS delay relative to DQ read access */
-	.p0_mprddlctl = 0x42444444,
-	/* Write Calibration: DQ/DM delay relative to DQS write access */
-	.p0_mpwrdlctl = 0x36322C32,
-};
-
-static void spl_dram_init(int width)
-{
-	struct mx6_ddr3_cfg *mem = &mt41k256m16ha_125;
-	struct mx6_ddr_sysinfo sysinfo = {
-		/* width of data bus:0=16,1=32,2=64 */
-		.dsize = width / 32,
-		/* config for full 4GB range so that get_mem_size() works */
-		.cs_density = 32, /* 32Gb per CS */
-		/* single chip select */
-		.ncs = 1,
-		.cs1_mirror = 1,
-		.rtt_wr = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Wr = RZQ/4 */
-#ifdef RTT_NOM_120OHM
-		.rtt_nom = 2 /*DDR3_RTT_120_OHM*/,	/* RTT_Nom = RZQ/2 */
-#else
-		.rtt_nom = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Nom = RZQ/4 */
-#endif
-		.walat = 0,	/* Write additional latency */
-		.ralat = 5,	/* Read additional latency */
-		.mif3_mode = 3,	/* Command prediction working mode */
-		.bi_on = 1,	/* Bank interleaving enabled */
-		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
-		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
-		.ddr_type = DDR_TYPE_DDR3,
-		.refsel = 1,	/* Refresh cycles at 32KHz */
-		.refr = 7, 	/* 8 refresh commands per refresh cycle */
-	};
-
-	mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
-	mx6_dram_cfg(&sysinfo, &mx6dq_mmdc_calib, mem);
-}
-
-/*
- * Called from C runtime startup code (arch/arm/lib/crt0.S:_main)
- * - we have a stack and a place to store GD, both in SRAM
- * - no variable global data is available
- */
-void board_init_f(ulong dummy)
-{
-	/* Setup AIPS and disable watchdog */
-	arch_cpu_init();
-
-	ccgr_init();
-	gpr_init();
-
-	/* UART iomux */
-	board_early_init_f();
-
-	/* Setup GP timer */
-	timer_init();
-
-	/* UART clocks enabled and gd valid - init serial console */
-	preloader_console_init();
-
-	/* Init DDR with 32bit width */
-	spl_dram_init(32);
-
-	/* Clear the BSS */
-	memset(__bss_start, 0, __bss_end - __bss_start);
-
-	/*
-	 * Setup enet related MUXing early to give the PHY
-	 * some time to wake-up from reset
-	 */
-	platinum_setup_enet();
-
-	/* load/boot image from boot device */
-	board_init_r(NULL, 0);
-}
diff --git a/board/barco/platinum/spl_titanium.c b/board/barco/platinum/spl_titanium.c
deleted file mode 100644
index 8c91b752..0000000
--- a/board/barco/platinum/spl_titanium.c
+++ /dev/null
@@ -1,186 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2014 Stefan Roese <sr@denx.de>
- *
- * Based on: gw_ventana_spl.c which is:
- * Copyright (C) 2014 Gateworks Corporation
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <init.h>
-#include <asm/io.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-ddr.h>
-#include <asm/arch/mx6-pins.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/mach-imx/boot_mode.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <spl.h>
-
-#include "platinum.h"
-
-#undef RTT_NOM_120OHM	/* use 120ohm Rtt_nom vs 60ohm (lower power) */
-
-/* Configure MX6Q/DUAL mmdc DDR io registers */
-struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
-	/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
-	.dram_sdclk_0 = 0x00020030,
-	.dram_sdclk_1 = 0x00020030,
-	.dram_cas = 0x00020030,
-	.dram_ras = 0x00020030,
-	.dram_reset = 0x00020030,
-	/* SDCKE[0:1]: 100k pull-up */
-	.dram_sdcke0 = 0x00003000,
-	.dram_sdcke1 = 0x00003000,
-	/* SDBA2: pull-up disabled */
-	.dram_sdba2 = 0x00000000,
-	/* SDODT[0:1]: 100k pull-up, 40 ohm */
-	.dram_sdodt0 = 0x00003030,
-	.dram_sdodt1 = 0x00003030,
-	/* SDQS[0:7]: Differential input, 40 ohm */
-	.dram_sdqs0 = 0x00000030,
-	.dram_sdqs1 = 0x00000030,
-	.dram_sdqs2 = 0x00000030,
-	.dram_sdqs3 = 0x00000030,
-	.dram_sdqs4 = 0x00000030,
-	.dram_sdqs5 = 0x00000030,
-	.dram_sdqs6 = 0x00000030,
-	.dram_sdqs7 = 0x00000030,
-	/* DQM[0:7]: Differential input, 40 ohm */
-	.dram_dqm0 = 0x00020030,
-	.dram_dqm1 = 0x00020030,
-	.dram_dqm2 = 0x00020030,
-	.dram_dqm3 = 0x00020030,
-	.dram_dqm4 = 0x00020030,
-	.dram_dqm5 = 0x00020030,
-	.dram_dqm6 = 0x00020030,
-	.dram_dqm7 = 0x00020030,
-};
-
-/* Configure MX6Q/DUAL mmdc GRP io registers */
-struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
-	/* DDR3 */
-	.grp_ddr_type = 0x000c0000,
-	.grp_ddrmode_ctl = 0x00020000,
-	/* disable DDR pullups */
-	.grp_ddrpke = 0x00000000,
-	/* ADDR[00:16], SDBA[0:1]: 40 ohm */
-	.grp_addds = 0x00000030,
-	/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
-	.grp_ctlds = 0x00000030,
-	/* DATA[00:63]: Differential input, 40 ohm */
-	.grp_ddrmode = 0x00020000,
-	.grp_b0ds = 0x00000030,
-	.grp_b1ds = 0x00000030,
-	.grp_b2ds = 0x00000030,
-	.grp_b3ds = 0x00000030,
-	.grp_b4ds = 0x00000030,
-	.grp_b5ds = 0x00000030,
-	.grp_b6ds = 0x00000030,
-	.grp_b7ds = 0x00000030,
-};
-
-/* MT41J128M16JT-125 */
-static struct mx6_ddr3_cfg mt41j128m16jt_125 = {
-	.mem_speed = 1600,
-	.density = 2,
-	.width = 16,
-	.banks = 8,
-	.rowaddr = 14,
-	.coladdr = 10,
-	.pagesz = 2,
-	.trcd = 1375,
-	.trcmin = 4875,
-	.trasmin = 3500,
-};
-
-static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
-	/* Write leveling calibration determine */
-	.p0_mpwldectrl0 = 0x001f001f,
-	.p0_mpwldectrl1 = 0x001f001f,
-	.p1_mpwldectrl0 = 0x00440044,
-	.p1_mpwldectrl1 = 0x00440044,
-	/* Read DQS Gating calibration */
-	.p0_mpdgctrl0 = 0x434b0350,
-	.p0_mpdgctrl1 = 0x034c0359,
-	.p1_mpdgctrl0 = 0x434b0350,
-	.p1_mpdgctrl1 = 0x03650348,
-	/* Read Calibration: DQS delay relative to DQ read access */
-	.p0_mprddlctl = 0x4436383b,
-	.p1_mprddlctl = 0x39393341,
-	/* Write Calibration: DQ/DM delay relative to DQS write access */
-	.p0_mpwrdlctl = 0x35373933,
-	.p1_mpwrdlctl = 0x48254a36,
-};
-
-static void spl_dram_init(int width)
-{
-	struct mx6_ddr3_cfg *mem = &mt41j128m16jt_125;
-	struct mx6_ddr_sysinfo sysinfo = {
-		/* width of data bus:0=16,1=32,2=64 */
-		.dsize = width / 32,
-		/* config for full 4GB range so that get_mem_size() works */
-		.cs_density = 32, /* 32Gb per CS */
-		/* single chip select */
-		.ncs = 1,
-		.cs1_mirror = 1,
-		.rtt_wr = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Wr = RZQ/4 */
-#ifdef RTT_NOM_120OHM
-		.rtt_nom = 2 /*DDR3_RTT_120_OHM*/,	/* RTT_Nom = RZQ/2 */
-#else
-		.rtt_nom = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Nom = RZQ/4 */
-#endif
-		.walat = 0,	/* Write additional latency */
-		.ralat = 5,	/* Read additional latency */
-		.mif3_mode = 3,	/* Command prediction working mode */
-		.bi_on = 1,	/* Bank interleaving enabled */
-		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
-		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
-		.ddr_type = DDR_TYPE_DDR3,
-		.refsel = 1,		/* Refresh cycles at 32KHz */
-		.refr = 7,		/* 8 refresh commands per refresh cycle */
-	};
-
-	mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
-	mx6_dram_cfg(&sysinfo, &mx6dq_mmdc_calib, mem);
-}
-
-/*
- * Called from C runtime startup code (arch/arm/lib/crt0.S:_main)
- * - we have a stack and a place to store GD, both in SRAM
- * - no variable global data is available
- */
-void board_init_f(ulong dummy)
-{
-	/* Setup AIPS and disable watchdog */
-	arch_cpu_init();
-
-	ccgr_init();
-	gpr_init();
-
-	/* UART iomux */
-	board_early_init_f();
-
-	/* Setup GP timer */
-	timer_init();
-
-	/* UART clocks enabled and gd valid - init serial console */
-	preloader_console_init();
-
-	/* Init DDR with 32bit width */
-	spl_dram_init(32);
-
-	/* Clear the BSS */
-	memset(__bss_start, 0, __bss_end - __bss_start);
-
-	/*
-	 * Setup enet related MUXing early to give the PHY
-	 * some time to wake-up from reset
-	 */
-	platinum_setup_enet();
-
-	/* load/boot image from boot device */
-	board_init_r(NULL, 0);
-}