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| author | Vikas Manocha <vikas.manocha@st.com> | 2017-02-12 10:25:53 -0800 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-03-17 14:15:16 -0400 |
| commit | e245f1a5db086d676cbd97371046ea5c5e554326 (patch) | |
| tree | 5244751424de78b7abd63dd22eaf7010893045f8 /board/st | |
| parent | c428a9583349f75f404750253920620207f70d55 (diff) | |
| download | u-boot-e245f1a5db086d676cbd97371046ea5c5e554326.zip u-boot-e245f1a5db086d676cbd97371046ea5c5e554326.tar.gz u-boot-e245f1a5db086d676cbd97371046ea5c5e554326.tar.bz2 | |
ARM: DT: stm32f7: add qspi pin contol node
It also removes the qspi pin configuration done during the
board initialization.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Diffstat (limited to 'board/st')
| -rw-r--r-- | board/st/stm32f746-disco/stm32f746-disco.c | 43 |
1 files changed, 0 insertions, 43 deletions
diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c index 8343f82..fdad8d1 100644 --- a/board/st/stm32f746-disco/stm32f746-disco.c +++ b/board/st/stm32f746-disco/stm32f746-disco.c @@ -262,55 +262,12 @@ static int stmmac_setup(void) #endif #ifdef CONFIG_STM32_QSPI -const struct stm32_gpio_ctl gpio_ctl_qspi_9 = { - .mode = STM32_GPIO_MODE_AF, - .otype = STM32_GPIO_OTYPE_PP, - .speed = STM32_GPIO_SPEED_100M, - .pupd = STM32_GPIO_PUPD_NO, - .af = STM32_GPIO_AF9 -}; - -const struct stm32_gpio_ctl gpio_ctl_qspi_10 = { - .mode = STM32_GPIO_MODE_AF, - .otype = STM32_GPIO_OTYPE_PP, - .speed = STM32_GPIO_SPEED_100M, - .pupd = STM32_GPIO_PUPD_NO, - .af = STM32_GPIO_AF10 -}; - -static const struct stm32_gpio_dsc qspi_af9_gpio[] = { - {STM32_GPIO_PORT_B, STM32_GPIO_PIN_2}, /* QUADSPI_CLK */ - {STM32_GPIO_PORT_D, STM32_GPIO_PIN_11}, /* QUADSPI_BK1_IO0 */ - {STM32_GPIO_PORT_D, STM32_GPIO_PIN_12}, /* QUADSPI_BK1_IO1 */ - {STM32_GPIO_PORT_D, STM32_GPIO_PIN_13}, /* QUADSPI_BK1_IO3 */ - {STM32_GPIO_PORT_E, STM32_GPIO_PIN_2}, /* QUADSPI_BK1_IO2 */ -}; - -static const struct stm32_gpio_dsc qspi_af10_gpio[] = { - {STM32_GPIO_PORT_B, STM32_GPIO_PIN_6}, /* QUADSPI_BK1_NCS */ -}; static int qspi_setup(void) { - int res = 0; - int i; - clock_setup(GPIO_B_CLOCK_CFG); clock_setup(GPIO_D_CLOCK_CFG); clock_setup(GPIO_E_CLOCK_CFG); - - for (i = 0; i < ARRAY_SIZE(qspi_af9_gpio); i++) { - res = stm32_gpio_config(&qspi_af9_gpio[i], &gpio_ctl_qspi_9); - if (res) - return res; - } - - for (i = 0; i < ARRAY_SIZE(qspi_af10_gpio); i++) { - res = stm32_gpio_config(&qspi_af10_gpio[i], &gpio_ctl_qspi_10); - if (res) - return res; - } - return 0; } #endif |