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| author | Paul Gortmaker <paul.gortmaker@windriver.com> | 2011-12-30 23:53:12 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2012-01-11 13:59:14 -0600 |
| commit | 3e3262bd149e21d0f5a82648218c26f2aa0e15e7 (patch) | |
| tree | 954100513b29dbcea5804303864c74d75ba729b0 /board/sbc8548 | |
| parent | 2a6b3b74d85cff3f9a76edd09a7b2e8e25bb4eb4 (diff) | |
| download | u-boot-3e3262bd149e21d0f5a82648218c26f2aa0e15e7.zip u-boot-3e3262bd149e21d0f5a82648218c26f2aa0e15e7.tar.gz u-boot-3e3262bd149e21d0f5a82648218c26f2aa0e15e7.tar.bz2 | |
sbc8548: enable support for hardware SPD errata workaround
Existing boards by default have an issue where the LBC SDRAM
SPD EEPROM and the DDR2 SDRAM SPD EEPROM both land at 0x51.
After the hardware modification listed in the README is made,
then the DDR2 SPD EEPROM appears at 0x53. So this implements
a board specific get_spd() by taking advantage of the existing
weak linkage, that 1st tries reading at 0x53 and then if that
fails, it falls back to the old 0x51.
Since the old dependency issue of "SPD implies no LBC SDRAM"
gets removed with the hardware errata fix, remove that restriction
in the code, so both LBC SDRAM and SPD can be selected.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/sbc8548')
| -rw-r--r-- | board/sbc8548/ddr.c | 31 |
1 files changed, 30 insertions, 1 deletions
diff --git a/board/sbc8548/ddr.c b/board/sbc8548/ddr.c index 0d9a1ba..45ec485 100644 --- a/board/sbc8548/ddr.c +++ b/board/sbc8548/ddr.c @@ -7,6 +7,7 @@ */ #include <common.h> +#include <i2c.h> #include <asm/fsl_ddr_sdram.h> #include <asm/fsl_ddr_dimm_params.h> @@ -55,7 +56,35 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->half_strength_driver_enable = 0; } -#if !defined(CONFIG_SPD_EEPROM) +#ifdef CONFIG_SPD_EEPROM +/* + * Workaround for hardware errata. An i2c address conflict + * existed on earlier boards; the workaround moved the DDR + * SPD from 0x51 to 0x53. So we try and read 0x53 1st, and + * if that fails, then fall back to reading at 0x51. + */ +void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) +{ + int ret; + +#ifdef ALT_SPD_EEPROM_ADDRESS + if (i2c_address == SPD_EEPROM_ADDRESS) { + ret = i2c_read(ALT_SPD_EEPROM_ADDRESS, 0, 1, (uchar *)spd, + sizeof(generic_spd_eeprom_t)); + if (ret == 0) + return; /* Good data at 0x53 */ + memset(spd, 0, sizeof(generic_spd_eeprom_t)); + } +#endif + ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, + sizeof(generic_spd_eeprom_t)); + if (ret) { + printf("DDR: failed to read SPD from addr %u\n", i2c_address); + memset(spd, 0, sizeof(generic_spd_eeprom_t)); + } +} + +#else /* * fixed_sdram init -- doesn't use serial presence detect. * Assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed. |