[INKA4x0] NG hardware: SDRAM support

Add support for three new DDR chips that may  be present on a NG
INKA4x0 hardware: HYB25D512160BF-5, K4H511638C-7CB3, T46V32M16BN-6IT.

Cleanup board/inka4x0/mt48lc16m16a2-75.h file.

Signed-off-by: Marian Balakowicz <m8@semihalf.com>

6 files changed, 108 insertions, 26 deletions

diff --git a/board/inka4x0/hyb25d512160bf-5.h b/board/inka4x0/hyb25d512160bf-5.h
new file mode 100644
index 0000000..7eb1f50
--- /dev/null
+++ b/board/inka4x0/hyb25d512160bf-5.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2007 Semihalf
+ * Written by Marian Balakowicz <m8@semihalf.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	1		/* is DDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x714F0F00
+#define SDRAM_CONFIG1	0x73711930
+#define SDRAM_CONFIG2	0x46770000
+#define SDRAM_TAPDELAY	0x10000000
diff --git a/board/inka4x0/inka4x0.c b/board/inka4x0/inka4x0.c
index c80fc3b..5157f7d 100644
--- a/board/inka4x0/inka4x0.c
+++ b/board/inka4x0/inka4x0.c
@@ -31,10 +31,18 @@
 #include <mpc5xxx.h>
 #include <pci.h>
 
-#if defined(CONFIG_MPC5200_DDR)
+#if defined(CONFIG_DDR_MT46V16M16)
 #include "mt46v16m16-75.h"
-#else
+#elif defined(CONFIG_SDR_MT48LC16M16A2)
 #include "mt48lc16m16a2-75.h"
+#elif defined(CONFIG_DDR_MT46V32M16)
+#include "mt46v32m16.h"
+#elif defined(CONFIG_DDR_HYB25D512160BF)
+#include "hyb25d512160bf.h"
+#elif defined(CONFIG_DDR_K4H511638C)
+#include "k4h511638c.h"
+#else
+#error "INKA4x0 SDRAM: invalid chip type specified!"
 #endif
 
 #ifndef CFG_RAMBOOT
diff --git a/board/inka4x0/k4h511638c.h b/board/inka4x0/k4h511638c.h
new file mode 100644
index 0000000..70cc405
--- /dev/null
+++ b/board/inka4x0/k4h511638c.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2007 Semihalf
+ * Written by Marian Balakowicz <m8@semihalf.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	1		/* is DDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x714F0F00
+#define SDRAM_CONFIG1	0x73722930
+#define SDRAM_CONFIG2	0x46770000
+#define SDRAM_TAPDELAY	0x10000000
diff --git a/board/inka4x0/mt46v16m16-75.h b/board/inka4x0/mt46v16m16-75.h
index f650faa..a78e50e 100644
--- a/board/inka4x0/mt46v16m16-75.h
+++ b/board/inka4x0/mt46v16m16-75.h
@@ -23,15 +23,10 @@
 
 #define SDRAM_DDR	1		/* is DDR */
 
-#if defined(CONFIG_MPC5200)
 /* Settings for XLB = 132 MHz */
 #define SDRAM_MODE	0x018D0000
 #define SDRAM_EMODE	0x40090000
-#define SDRAM_CONTROL	0x714f0f00
+#define SDRAM_CONTROL	0x714F0F00
 #define SDRAM_CONFIG1	0x73722930
 #define SDRAM_CONFIG2	0x47770000
 #define SDRAM_TAPDELAY	0x10000000
-
-#else
-#error CONFIG_MPC5200 not defined
-#endif
diff --git a/board/inka4x0/mt46v32m16-75.h b/board/inka4x0/mt46v32m16-75.h
new file mode 100644
index 0000000..7eb1f50
--- /dev/null
+++ b/board/inka4x0/mt46v32m16-75.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2007 Semihalf
+ * Written by Marian Balakowicz <m8@semihalf.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	1		/* is DDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x714F0F00
+#define SDRAM_CONFIG1	0x73711930
+#define SDRAM_CONFIG2	0x46770000
+#define SDRAM_TAPDELAY	0x10000000
diff --git a/board/inka4x0/mt48lc16m16a2-75.h b/board/inka4x0/mt48lc16m16a2-75.h
index 13a97ac..1547725 100644
--- a/board/inka4x0/mt48lc16m16a2-75.h
+++ b/board/inka4x0/mt48lc16m16a2-75.h
@@ -21,27 +21,10 @@
  * MA 02111-1307 USA
  */
 
-#define SDRAM_DDR	1		/* is SDR */
+#define SDRAM_DDR	0		/* is SDR */
 
-#if defined(CONFIG_MPC5200)
 /* Settings for XLB = 132 MHz */
 #define SDRAM_MODE	0x00CD0000
-/* #define SDRAM_MODE	0x008D0000 */ /* CAS latency 2 */
 #define SDRAM_CONTROL	0x504F0000
 #define SDRAM_CONFIG1	0xD2322800
-/* #define SDRAM_CONFIG1	0xD2222800 */ /* CAS latency 2 */
-/*#define SDRAM_CONFIG1	0xD7322800 */ /* SDRAM controller bug workaround */
 #define SDRAM_CONFIG2	0x8AD70000
-/*#define SDRAM_CONFIG2	0xDDD70000 */ /* SDRAM controller bug workaround */
-
-#elif defined(CONFIG_MGT5100)
-/* Settings for XLB = 66 MHz */
-#define SDRAM_MODE	0x008D0000
-#define SDRAM_CONTROL	0x504F0000
-#define SDRAM_CONFIG1	0xC2222600
-#define SDRAM_CONFIG2	0x88B70004
-#define SDRAM_ADDRSEL	0x02000000
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif