MIPS: drop incaip board

This is dead hardware and no one is interested in making the
necessary changes for upcoming features like generic board or
driver model.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>

6 files changed, 0 insertions, 1134 deletions

diff --git a/board/incaip/Makefile b/board/incaip/Makefile
deleted file mode 100644
index 602d30e..0000000
--- a/board/incaip/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= incaip.o flash.o
-obj-y	+= lowlevel_init.o
diff --git a/board/incaip/README b/board/incaip/README
deleted file mode 100644
index 1329152..0000000
--- a/board/incaip/README
+++ /dev/null
@@ -1,57 +0,0 @@
-
-Flash programming on the INCA-IP board is complicated because of the
-EBU swapping unit. A BDI2000 can be used for flash programming only
-if the EBU swapping unit is enabled; otherwise it will not detect the
-flash memory. But the EBU swapping unit is disadbled after reset, so
-if you program some code to flash with the swapping unit on, it will
-not be runnable with the swapping unit off.
-
-The consequence is that you have to write a pre-swapped image to
-flash using the BDI2000. A simple host-side tool "inca-swap-bytes" is
-provided in the "tools/" directory. Use it as follows:
-
-	bash$ ./inca-swap-bytes <u-boot.bin >u-boot.bin.swp
-
-Note that the current BDI config file _disables_ the EBU swapping
-unit for the flash bank 0. To enable it, (this is required for the
-BDI flash commands to work) uncomment the following line in the
-config file:
-
-	;WM32   0xb8000260      0x404161ff ; Swapping unit enabled
-
-and comment out
-
-	WM32    0xb8000260      0x004161ff ; Swapping unit disabled
-
-Alternatively, you can use "mm 0xb8000260 <value>" commands to
-enable/disable the swapping unit manually.
-
-Just for reference, here is the complete sequence of actions we took
-to install a U-Boot image into flash.
-
-    1. ./inca-swap-bytes <u-boot.bin >u-boot.bin.swp
-
-    2. From BDI:
-
-	mm 0xb8000260  0x404161ff
-	erase 0xb0000000
-	erase 0xb0010000
-	prog 0xb0000000 /tftpboot/INCA/u-boot.bin.swp bin
-	mm 0xb8000260 0x004161ff
-	go 0xb0000000
-
-
-Ethernet autonegotiation needs some time to complete. Instead of
-delaying the boot process in all cases, we just start the
-autonegotiation process when U-Boot comes up and that is all. Most
-likely, it will complete by the time the network transfer is
-attempted for the first time. In the worst case, if a transfer is
-attempted before the autonegotiation is complete, just a single
-packet would be lost resulting in a single timeout error, and then
-the transfer would proceed normally. So the time that we would have
-lost unconditionally waiting for the autonegotiation to complete, we
-have to wait only if the file transfer is started immediately after
-reset. We've verified that this works for all the clock
-configurations.
-
-(C) 2003 Wolfgang Denk
diff --git a/board/incaip/config.mk b/board/incaip/config.mk
deleted file mode 100644
index e854f8e..0000000
--- a/board/incaip/config.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-#
-# INCA-IP board with MIPS 4Kc CPU core
-#
-
-# ROM version
-CONFIG_SYS_TEXT_BASE = 0xB0000000
-
-# RAM version
-#CONFIG_SYS_TEXT_BASE = 0x80100000
diff --git a/board/incaip/flash.c b/board/incaip/flash.c
deleted file mode 100644
index a786ac9..0000000
--- a/board/incaip/flash.c
+++ /dev/null
@@ -1,655 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/inca-ip.h>
-
-flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
-
-/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
- *        has nothing to do with the flash chip being 8-bit or 16-bit.
- */
-#ifdef CONFIG_FLASH_16BIT
-typedef unsigned short FLASH_PORT_WIDTH;
-typedef volatile unsigned short FLASH_PORT_WIDTHV;
-#define	FLASH_ID_MASK	0xFFFF
-#else
-typedef unsigned long FLASH_PORT_WIDTH;
-typedef volatile unsigned long FLASH_PORT_WIDTHV;
-#define	FLASH_ID_MASK	0xFFFFFFFF
-#endif
-
-#define FPW	FLASH_PORT_WIDTH
-#define FPWV	FLASH_PORT_WIDTHV
-
-#define ORMASK(size) ((-size) & OR_AM_MSK)
-
-#if 0
-#define FLASH_CYCLE1	0x0555
-#define FLASH_CYCLE2	0x02aa
-#else
-#define FLASH_CYCLE1	0x0554
-#define FLASH_CYCLE2	0x02ab
-#endif
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(FPWV *addr, flash_info_t *info);
-static void flash_reset(flash_info_t *info);
-static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data);
-static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
-static void flash_get_offsets(ulong base, flash_info_t *info);
-static flash_info_t *flash_get_info(ulong base);
-
-/*-----------------------------------------------------------------------
- * flash_init()
- *
- * sets up flash_info and returns size of FLASH (bytes)
- */
-unsigned long flash_init (void)
-{
-	unsigned long size = 0;
-	int i;
-
-	/* Init: no FLASHes known */
-	for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		ulong flashbase = (i == 0) ? PHYS_FLASH_1 : PHYS_FLASH_2;
-		ulong * buscon = (ulong *)
-			((i == 0) ? INCA_IP_EBU_EBU_BUSCON0 : INCA_IP_EBU_EBU_BUSCON2);
-
-		/* Disable write protection */
-		*buscon &= ~INCA_IP_EBU_EBU_BUSCON1_WRDIS;
-
-#if 1
-		memset(&flash_info[i], 0, sizeof(flash_info_t));
-#endif
-
-		flash_info[i].size =
-			flash_get_size((FPW *)flashbase, &flash_info[i]);
-
-		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
-			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx\n",
-			i, flash_info[i].size);
-		}
-
-		size += flash_info[i].size;
-	}
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-	/* monitor protection ON by default */
-	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_SYS_MONITOR_BASE,
-		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
-		      flash_get_info(CONFIG_SYS_MONITOR_BASE));
-#endif
-
-#ifdef	CONFIG_ENV_IS_IN_FLASH
-	/* ENV protection ON by default */
-	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_ENV_ADDR,
-		      CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
-		      flash_get_info(CONFIG_ENV_ADDR));
-#endif
-
-
-	return size;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_reset(flash_info_t *info)
-{
-	FPWV *base = (FPWV *)(info->start[0]);
-
-	/* Put FLASH back in read mode */
-	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
-		*base = (FPW)0x00FF00FF;	/* Intel Read Mode */
-	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
-		*base = (FPW)0x00F000F0;	/* AMD Read Mode */
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
-	int i;
-
-	/* set up sector start address table */
-	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL
-	    && (info->flash_id & FLASH_BTYPE)) {
-		int bootsect_size;	/* number of bytes/boot sector	*/
-		int sect_size;		/* number of bytes/regular sector */
-
-		bootsect_size = 0x00002000 * (sizeof(FPW)/2);
-		sect_size =     0x00010000 * (sizeof(FPW)/2);
-
-		/* set sector offsets for bottom boot block type	*/
-		for (i = 0; i < 8; ++i) {
-			info->start[i] = base + (i * bootsect_size);
-		}
-		for (i = 8; i < info->sector_count; i++) {
-			info->start[i] = base + ((i - 7) * sect_size);
-		}
-	}
-	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
-		 && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) {
-
-		int sect_size;		/* number of bytes/sector */
-
-		sect_size = 0x00010000 * (sizeof(FPW)/2);
-
-		/* set up sector start address table (uniform sector type) */
-		for( i = 0; i < info->sector_count; i++ )
-			info->start[i] = base + (i * sect_size);
-	}
-}
-
-/*-----------------------------------------------------------------------
- */
-
-static flash_info_t *flash_get_info(ulong base)
-{
-	int i;
-	flash_info_t * info;
-
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
-		info = & flash_info[i];
-		if (info->start[0] <= base && base < info->start[0] + info->size)
-			break;
-	}
-
-	return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-void flash_print_info (flash_info_t *info)
-{
-	int i;
-	uchar *boottype;
-	uchar *bootletter;
-	char *fmt;
-	uchar botbootletter[] = "B";
-	uchar topbootletter[] = "T";
-	uchar botboottype[] = "bottom boot sector";
-	uchar topboottype[] = "top boot sector";
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_AMD:	printf ("AMD ");		break;
-	case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
-	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
-	case FLASH_MAN_SST:	printf ("SST ");		break;
-	case FLASH_MAN_STM:	printf ("STM ");		break;
-	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
-	default:		printf ("Unknown Vendor ");	break;
-	}
-
-	/* check for top or bottom boot, if it applies */
-	if (info->flash_id & FLASH_BTYPE) {
-		boottype = botboottype;
-		bootletter = botbootletter;
-	}
-	else {
-		boottype = topboottype;
-		bootletter = topbootletter;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_AM640U:
-		fmt = "29LV641D (64 Mbit, uniform sectors)\n";
-		break;
-	case FLASH_28F800C3B:
-	case FLASH_28F800C3T:
-		fmt = "28F800C3%s (8 Mbit, %s)\n";
-		break;
-	case FLASH_INTEL800B:
-	case FLASH_INTEL800T:
-		fmt = "28F800B3%s (8 Mbit, %s)\n";
-		break;
-	case FLASH_28F160C3B:
-	case FLASH_28F160C3T:
-		fmt = "28F160C3%s (16 Mbit, %s)\n";
-		break;
-	case FLASH_INTEL160B:
-	case FLASH_INTEL160T:
-		fmt = "28F160B3%s (16 Mbit, %s)\n";
-		break;
-	case FLASH_28F320C3B:
-	case FLASH_28F320C3T:
-		fmt = "28F320C3%s (32 Mbit, %s)\n";
-		break;
-	case FLASH_INTEL320B:
-	case FLASH_INTEL320T:
-		fmt = "28F320B3%s (32 Mbit, %s)\n";
-		break;
-	case FLASH_28F640C3B:
-	case FLASH_28F640C3T:
-		fmt = "28F640C3%s (64 Mbit, %s)\n";
-		break;
-	case FLASH_INTEL640B:
-	case FLASH_INTEL640T:
-		fmt = "28F640B3%s (64 Mbit, %s)\n";
-		break;
-	default:
-		fmt = "Unknown Chip Type\n";
-		break;
-	}
-
-	printf (fmt, bootletter, boottype);
-
-	printf ("  Size: %ld MB in %d Sectors\n",
-		info->size >> 20,
-		info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-
-	for (i=0; i<info->sector_count; ++i) {
-		if ((i % 5) == 0) {
-			printf ("\n   ");
-		}
-
-		printf (" %08lX%s", info->start[i],
-			info->protect[i] ? " (RO)" : "     ");
-	}
-
-	printf ("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-ulong flash_get_size (FPWV *addr, flash_info_t *info)
-{
-	/* Write auto select command: read Manufacturer ID */
-
-	/* Write auto select command sequence and test FLASH answer */
-	addr[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* for AMD, Intel ignores this */
-	addr[FLASH_CYCLE2] = (FPW)0x00550055;	/* for AMD, Intel ignores this */
-	addr[FLASH_CYCLE1] = (FPW)0x00900090;	/* selects Intel or AMD */
-
-	/* The manufacturer codes are only 1 byte, so just use 1 byte.
-	 * This works for any bus width and any FLASH device width.
-	 */
-	switch (addr[1] & 0xff) {
-
-	case (uchar)AMD_MANUFACT:
-		info->flash_id = FLASH_MAN_AMD;
-		break;
-
-	case (uchar)INTEL_MANUFACT:
-		info->flash_id = FLASH_MAN_INTEL;
-		break;
-
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		break;
-	}
-
-	/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
-	if (info->flash_id != FLASH_UNKNOWN) switch (addr[0]) {
-
-	case (FPW)AMD_ID_LV640U:	/* 29LV640 and 29LV641 have same ID */
-		info->flash_id += FLASH_AM640U;
-		info->sector_count = 128;
-		info->size = 0x00800000 * (sizeof(FPW)/2);
-		break;				/* => 8 or 16 MB	*/
-
-	case (FPW)INTEL_ID_28F800C3B:
-		info->flash_id += FLASH_28F800C3B;
-		info->sector_count = 23;
-		info->size = 0x00100000 * (sizeof(FPW)/2);
-		break;				/* => 1 or 2 MB		*/
-
-	case (FPW)INTEL_ID_28F800B3B:
-		info->flash_id += FLASH_INTEL800B;
-		info->sector_count = 23;
-		info->size = 0x00100000 * (sizeof(FPW)/2);
-		break;				/* => 1 or 2 MB		*/
-
-	case (FPW)INTEL_ID_28F160C3B:
-		info->flash_id += FLASH_28F160C3B;
-		info->sector_count = 39;
-		info->size = 0x00200000 * (sizeof(FPW)/2);
-		break;				/* => 2 or 4 MB		*/
-
-	case (FPW)INTEL_ID_28F160B3B:
-		info->flash_id += FLASH_INTEL160B;
-		info->sector_count = 39;
-		info->size = 0x00200000 * (sizeof(FPW)/2);
-		break;				/* => 2 or 4 MB		*/
-
-	case (FPW)INTEL_ID_28F320C3B:
-		info->flash_id += FLASH_28F320C3B;
-		info->sector_count = 71;
-		info->size = 0x00400000 * (sizeof(FPW)/2);
-		break;				/* => 4 or 8 MB		*/
-
-	case (FPW)INTEL_ID_28F320B3B:
-		info->flash_id += FLASH_INTEL320B;
-		info->sector_count = 71;
-		info->size = 0x00400000 * (sizeof(FPW)/2);
-		break;				/* => 4 or 8 MB		*/
-
-	case (FPW)INTEL_ID_28F640C3B:
-		info->flash_id += FLASH_28F640C3B;
-		info->sector_count = 135;
-		info->size = 0x00800000 * (sizeof(FPW)/2);
-		break;				/* => 8 or 16 MB	*/
-
-	case (FPW)INTEL_ID_28F640B3B:
-		info->flash_id += FLASH_INTEL640B;
-		info->sector_count = 135;
-		info->size = 0x00800000 * (sizeof(FPW)/2);
-		break;				/* => 8 or 16 MB	*/
-
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		return (0);			/* => no or unknown flash */
-	}
-
-	flash_get_offsets((ulong)addr, info);
-
-	/* Put FLASH back in read mode */
-	flash_reset(info);
-
-	return (info->size);
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int	flash_erase (flash_info_t *info, int s_first, int s_last)
-{
-	FPWV *addr;
-	int flag, prot, sect;
-	int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
-	ulong start, now, last;
-	int rcode = 0;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_INTEL800B:
-	case FLASH_INTEL160B:
-	case FLASH_INTEL320B:
-	case FLASH_INTEL640B:
-	case FLASH_28F800C3B:
-	case FLASH_28F160C3B:
-	case FLASH_28F320C3B:
-	case FLASH_28F640C3B:
-	case FLASH_AM640U:
-		break;
-	case FLASH_UNKNOWN:
-	default:
-		printf ("Can't erase unknown flash type %08lx - aborted\n",
-			info->flash_id);
-		return 1;
-	}
-
-	prot = 0;
-	for (sect=s_first; sect<=s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-			prot);
-	} else {
-		printf ("\n");
-	}
-
-	last  = get_timer(0);
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
-
-		if (info->protect[sect] != 0)	/* protected, skip it */
-			continue;
-
-		/* Disable interrupts which might cause a timeout here */
-		flag = disable_interrupts();
-
-		addr = (FPWV *)(info->start[sect]);
-		if (intel) {
-			*addr = (FPW)0x00500050; /* clear status register */
-			*addr = (FPW)0x00200020; /* erase setup */
-			*addr = (FPW)0x00D000D0; /* erase confirm */
-		}
-		else {
-			/* must be AMD style if not Intel */
-			FPWV *base;		/* first address in bank */
-
-			base = (FPWV *)(info->start[0]);
-			base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
-			base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
-			base[FLASH_CYCLE1] = (FPW)0x00800080;	/* erase mode */
-			base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
-			base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
-			*addr = (FPW)0x00300030;	/* erase sector */
-		}
-
-		/* re-enable interrupts if necessary */
-		if (flag)
-			enable_interrupts();
-
-		start = get_timer(0);
-
-		/* wait at least 50us for AMD, 80us for Intel.
-		 * Let's wait 1 ms.
-		 */
-		udelay (1000);
-
-		while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
-			if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-				printf ("Timeout\n");
-
-				if (intel) {
-					/* suspend erase	*/
-					*addr = (FPW)0x00B000B0;
-				}
-
-				flash_reset(info);	/* reset to read mode */
-				rcode = 1;		/* failed */
-				break;
-			}
-
-			/* show that we're waiting */
-			if ((get_timer(last)) > CONFIG_SYS_HZ) {/* every second */
-				putc ('.');
-				last = get_timer(0);
-			}
-		}
-
-		/* show that we're waiting */
-		if ((get_timer(last)) > CONFIG_SYS_HZ) {	/* every second */
-			putc ('.');
-			last = get_timer(0);
-		}
-
-		flash_reset(info);	/* reset to read mode	*/
-	}
-
-	printf (" done\n");
-	return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-    FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
-    int bytes;	  /* number of bytes to program in current word		*/
-    int left;	  /* number of bytes left to program			*/
-    int i, res;
-
-    for (left = cnt, res = 0;
-	 left > 0 && res == 0;
-	 addr += sizeof(data), left -= sizeof(data) - bytes) {
-
-	bytes = addr & (sizeof(data) - 1);
-	addr &= ~(sizeof(data) - 1);
-
-	/* combine source and destination data so can program
-	 * an entire word of 16 or 32 bits
-	 */
-	for (i = 0; i < sizeof(data); i++) {
-	    data <<= 8;
-	    if (i < bytes || i - bytes >= left )
-		data += *((uchar *)addr + i);
-	    else
-		data += *src++;
-	}
-
-	/* write one word to the flash */
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_AMD:
-		res = write_word_amd(info, (FPWV *)addr, data);
-		break;
-	case FLASH_MAN_INTEL:
-		res = write_word_intel(info, (FPWV *)addr, data);
-		break;
-	default:
-		/* unknown flash type, error! */
-		printf ("missing or unknown FLASH type\n");
-		res = 1;	/* not really a timeout, but gives error */
-		break;
-	}
-    }
-
-    return (res);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash for AMD FLASH
- * A word is 16 or 32 bits, whichever the bus width of the flash bank
- * (not an individual chip) is.
- *
- * returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
-{
-    ulong start;
-    int flag;
-    int res = 0;	/* result, assume success	*/
-    FPWV *base;		/* first address in flash bank	*/
-
-    /* Check if Flash is (sufficiently) erased */
-    if ((*dest & data) != data) {
-	return (2);
-    }
-
-
-    base = (FPWV *)(info->start[0]);
-
-    /* Disable interrupts which might cause a timeout here */
-    flag = disable_interrupts();
-
-    base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
-    base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
-    base[FLASH_CYCLE1] = (FPW)0x00A000A0;	/* selects program mode */
-
-    *dest = data;		/* start programming the data	*/
-
-    /* re-enable interrupts if necessary */
-    if (flag)
-	enable_interrupts();
-
-    start = get_timer (0);
-
-    /* data polling for D7 */
-    while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
-	if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-	    *dest = (FPW)0x00F000F0;	/* reset bank */
-	    res = 1;
-	}
-    }
-
-    return (res);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash for Intel FLASH
- * A word is 16 or 32 bits, whichever the bus width of the flash bank
- * (not an individual chip) is.
- *
- * returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data)
-{
-    ulong start;
-    int flag;
-    int res = 0;	/* result, assume success	*/
-
-    /* Check if Flash is (sufficiently) erased */
-    if ((*dest & data) != data) {
-	return (2);
-    }
-
-    /* Disable interrupts which might cause a timeout here */
-    flag = disable_interrupts();
-
-    *dest = (FPW)0x00500050;	/* clear status register	*/
-    *dest = (FPW)0x00FF00FF;	/* make sure in read mode	*/
-    *dest = (FPW)0x00400040;	/* program setup		*/
-
-    *dest = data;		/* start programming the data	*/
-
-    /* re-enable interrupts if necessary */
-    if (flag)
-	enable_interrupts();
-
-    start = get_timer (0);
-
-    while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) {
-	if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-	    *dest = (FPW)0x00B000B0;	/* Suspend program	*/
-	    res = 1;
-	}
-    }
-
-    if (res == 0 && (*dest & (FPW)0x00100010))
-	res = 1;	/* write failed, time out error is close enough	*/
-
-    *dest = (FPW)0x00500050;	/* clear status register	*/
-    *dest = (FPW)0x00FF00FF;	/* make sure in read mode	*/
-
-    return (res);
-}
diff --git a/board/incaip/incaip.c b/board/incaip/incaip.c
deleted file mode 100644
index 217b8af..0000000
--- a/board/incaip/incaip.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <netdev.h>
-#include <asm/addrspace.h>
-#include <asm/inca-ip.h>
-#include <asm/io.h>
-#include <asm/reboot.h>
-
-extern uint incaip_get_cpuclk(void);
-
-void _machine_restart(void)
-{
-	*INCA_IP_WDT_RST_REQ = 0x3f;
-}
-
-static ulong max_sdram_size(void)
-{
-	/* The only supported SDRAM data width is 16bit.
-	 */
-#define CONFIG_SYS_DW	2
-
-	/* The only supported number of SDRAM banks is 4.
-	 */
-#define CONFIG_SYS_NB	4
-
-	ulong cfgpb0 = *INCA_IP_SDRAM_MC_CFGPB0;
-	int   cols   = cfgpb0 & 0xF;
-	int   rows   = (cfgpb0 & 0xF0) >> 4;
-	ulong size   = (1 << (rows + cols)) * CONFIG_SYS_DW * CONFIG_SYS_NB;
-
-	return size;
-}
-
-phys_size_t initdram(int board_type)
-{
-	int   rows, cols, best_val = *INCA_IP_SDRAM_MC_CFGPB0;
-	ulong size, max_size       = 0;
-	ulong our_address;
-
-	asm volatile ("move %0, $25" : "=r" (our_address) :);
-
-		/* Can't probe for RAM size unless we are running from Flash.
-		 */
-	if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1))
-	{
-		return max_sdram_size();
-	}
-
-	for (cols = 0x8; cols <= 0xC; cols++)
-	{
-		for (rows = 0xB; rows <= 0xD; rows++)
-		{
-			*INCA_IP_SDRAM_MC_CFGPB0 = (0x14 << 8) |
-						   (rows << 4) | cols;
-			size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
-							     max_sdram_size());
-
-			if (size > max_size)
-			{
-				best_val = *INCA_IP_SDRAM_MC_CFGPB0;
-				max_size = size;
-			}
-		}
-	}
-
-	*INCA_IP_SDRAM_MC_CFGPB0 = best_val;
-	return max_size;
-}
-
-int checkboard (void)
-{
-	unsigned long chipid = *INCA_IP_WDT_CHIPID;
-	int part_num;
-
-	puts ("Board: INCA-IP ");
-	part_num = (chipid >> 12) & 0xffff;
-	switch (part_num) {
-	case 0xc0:
-		printf ("Standard Version, ");
-		break;
-	case 0xc1:
-		printf ("Basic Version, ");
-		break;
-	default:
-		printf ("Unknown Part Number 0x%x ", part_num);
-		break;
-	}
-
-	printf ("Chip V1.%ld, ", (chipid >> 28));
-
-	printf("CPU Speed %d MHz\n", incaip_get_cpuclk()/1000000);
-
-	set_io_port_base(0);
-
-	return 0;
-}
-
-#if defined(CONFIG_INCA_IP_SWITCH)
-int board_eth_init(bd_t *bis)
-{
-	return inca_switch_initialize(bis);
-}
-#endif
diff --git a/board/incaip/lowlevel_init.S b/board/incaip/lowlevel_init.S
deleted file mode 100644
index b6cf6a9..0000000
--- a/board/incaip/lowlevel_init.S
+++ /dev/null
@@ -1,287 +0,0 @@
-/*
- *  Memory sub-system initialization code for INCA-IP development board.
- *
- *  Copyright (c) 2003	Wolfgang Denk <wd@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-#include <asm/regdef.h>
-
-
-#define EBU_MODUL_BASE		0xB8000200
-#define EBU_CLC(value)		0x0000(value)
-#define EBU_CON(value)		0x0010(value)
-#define EBU_ADDSEL0(value)	0x0020(value)
-#define EBU_ADDSEL1(value)	0x0024(value)
-#define EBU_ADDSEL2(value)	0x0028(value)
-#define EBU_BUSCON0(value)	0x0060(value)
-#define EBU_BUSCON1(value)	0x0064(value)
-#define EBU_BUSCON2(value)	0x0068(value)
-
-#define MC_MODUL_BASE		0xBF800000
-#define MC_ERRCAUSE(value)	0x0100(value)
-#define MC_ERRADDR(value)	0x0108(value)
-#define MC_IOGP(value)		0x0800(value)
-#define MC_SELFRFSH(value)	0x0A00(value)
-#define MC_CTRLENA(value)	0x1000(value)
-#define MC_MRSCODE(value)	0x1008(value)
-#define MC_CFGDW(value)		0x1010(value)
-#define MC_CFGPB0(value)	0x1018(value)
-#define MC_LATENCY(value)	0x1038(value)
-#define MC_TREFRESH(value)	0x1040(value)
-
-#define CGU_MODUL_BASE		0xBF107000
-#define CGU_PLL1CR(value)	0x0008(value)
-#define CGU_DIVCR(value)	0x0010(value)
-#define CGU_MUXCR(value)	0x0014(value)
-#define CGU_PLL1SR(value)	0x000C(value)
-
-	.set	noreorder
-
-
-/*
- * void ebu_init(long)
- *
- * a0 has the clock value we are going to run at
- */
-	.globl	ebu_init
-	.ent	ebu_init
-ebu_init:
-__ebu_init:
-
-	li	t1, EBU_MODUL_BASE
-	li	t2, 0xA0000041
-	sw	t2, EBU_ADDSEL0(t1)
-	li	t2, 0xA0800041
-	sw	t2, EBU_ADDSEL2(t1)
-	li	t2, 0xBE0000F1
-	sw	t2, EBU_ADDSEL1(t1)
-
-	li	t3, 100000000
-	beq	a0, t3, 1f
-	nop
-	li	t3, 133000000
-	beq	a0, t3, 2f
-	nop
-	li	t3, 150000000
-	beq	a0, t3, 2f
-	nop
-	b	3f
-	nop
-
-	/* 100 MHz */
-1:
-	li	t2, 0x8841417D
-	sw	t2, EBU_BUSCON0(t1)
-	sw	t2, EBU_BUSCON2(t1)
-	li	t2, 0x684142BD
-	b	3f
-	sw	t2, EBU_BUSCON1(t1)	/* delay slot */
-
-	/* 133 or 150 MHz */
-2:
-	li	t2, 0x8841417E
-	sw	t2, EBU_BUSCON0(t1)
-	sw	t2, EBU_BUSCON2(t1)
-	li	t2, 0x684143FD
-	sw	t2, EBU_BUSCON1(t1)
-3:
-	jr	ra
-	nop
-
-	.end	ebu_init
-
-
-/*
- * void cgu_init(long)
- *
- * a0 has the clock value
- */
-	.globl	cgu_init
-	.ent	cgu_init
-cgu_init:
-__cgu_init:
-
-	li	t1, CGU_MODUL_BASE
-
-	li	t3, 100000000
-	beq	a0, t3, 1f
-	nop
-	li	t3, 133000000
-	beq	a0, t3, 2f
-	nop
-	li	t3, 150000000
-	beq	a0, t3, 3f
-	nop
-	b	5f
-	nop
-
-	/* 100 MHz clock */
-1:
-	li	t2, 0x80000014
-	sw	t2, CGU_DIVCR(t1)
-	li	t2, 0x80000000
-	sw	t2, CGU_MUXCR(t1)
-	li	t2, 0x800B0001
-	b	5f
-	sw	t2, CGU_PLL1CR(t1)	/* delay slot */
-
-	/* 133 MHz clock */
-2:
-	li	t2, 0x80000054
-	sw	t2, CGU_DIVCR(t1)
-	li	t2, 0x80000000
-	sw	t2, CGU_MUXCR(t1)
-	li	t2, 0x800B0001
-	b	5f
-	sw	t2, CGU_PLL1CR(t1)	/* delay slot */
-
-	/* 150 MHz clock */
-3:
-	li	t2, 0x80000017
-	sw	t2, CGU_DIVCR(t1)
-	li	t2, 0xC00B0001
-	sw	t2, CGU_PLL1CR(t1)
-	li	t3, 0x80000000
-4:
-	lw	t2, CGU_PLL1SR(t1)
-	and	t2, t2, t3
-	beq	t2, zero, 4b
-	nop
-	li	t2, 0x80000001
-	sw	t2, CGU_MUXCR(t1)
-5:
-	jr	ra
-	nop
-
-	.end	cgu_init
-
-
-/*
- * void sdram_init(long)
- *
- * a0 has the clock value
- */
-	.globl	sdram_init
-	.ent	sdram_init
-sdram_init:
-__sdram_init:
-
-	li	t1, MC_MODUL_BASE
-
-#if 0
-	/* Disable memory controller before changing any of its registers */
-	sw	zero, MC_CTRLENA(t1)
-#endif
-
-	li	t2, 100000000
-	beq	a0, t2, 1f
-	nop
-	li	t2, 133000000
-	beq	a0, t2, 2f
-	nop
-	li	t2, 150000000
-	beq	a0, t2, 3f
-	nop
-	b	5f
-	nop
-
-	/* 100 MHz clock */
-1:
-	/* Set clock ratio (clkrat=1:1, rddel=3) */
-	li	t2, 0x00000003
-	sw	t2, MC_IOGP(t1)
-
-	/* Set sdram refresh rate (4K/64ms @ 100MHz) */
-	li	t2, 0x0000061A
-	b	4f
-	sw	t2, MC_TREFRESH(t1)
-
-	/* 133 MHz clock */
-2:
-	/* Set clock ratio (clkrat=1:1, rddel=3) */
-	li	t2, 0x00000003
-	sw	t2, MC_IOGP(t1)
-
-	/* Set sdram refresh rate (4K/64ms @ 133MHz) */
-	li	t2, 0x00000822
-	b	4f
-	sw	t2, MC_TREFRESH(t1)
-
-	/* 150 MHz clock */
-3:
-	/* Set clock ratio (clkrat=3:2, rddel=4) */
-	li	t2, 0x00000014
-	sw	t2, MC_IOGP(t1)
-
-	/* Set sdram refresh rate (4K/64ms @ 150MHz) */
-	li	t2, 0x00000927
-	sw	t2, MC_TREFRESH(t1)
-
-4:
-	/* Clear Error log registers */
-	sw	zero, MC_ERRCAUSE(t1)
-	sw	zero, MC_ERRADDR(t1)
-
-	/* Clear Power-down registers */
-	sw	zero, MC_SELFRFSH(t1)
-
-	/* Set CAS Latency */
-	li	t2, 0x00000020		/* CL = 2 */
-	sw	t2, MC_MRSCODE(t1)
-
-	/* Set word width to 16 bit */
-	li	t2, 0x2
-	sw	t2, MC_CFGDW(t1)
-
-	/* Set CS0 to SDRAM parameters */
-	li	t2, 0x000014C9
-	sw	t2, MC_CFGPB0(t1)
-
-	/* Set SDRAM latency parameters */
-	li	t2, 0x00026325		/* BC PC100 */
-	sw	t2, MC_LATENCY(t1)
-
-5:
-	/* Finally enable the controller */
-	li	t2, 0x00000001
-	sw	t2, MC_CTRLENA(t1)
-
-	jr	ra
-	nop
-
-	.end	sdram_init
-
-
-	.globl	lowlevel_init
-	.ent	lowlevel_init
-lowlevel_init:
-
-	/* Disable Watchdog.
-	 */
-	la	t9, disable_incaip_wdt
-	jalr	t9
-	nop
-
-	/* EBU, CGU and SDRAM Initialization.
-	 */
-	li	a0, CONFIG_CPU_CLOCK_RATE
-	move	t0, ra
-
-	/* We rely on the fact that neither ebu_init() nor cgu_init() nor sdram_init()
-	 * modify t0 and a0.
-	 */
-	bal	__cgu_init
-	nop
-	bal	__ebu_init
-	nop
-	bal	__sdram_init
-	nop
-	move	ra, t0
-
-	jr	ra
-	nop
-
-	.end	lowlevel_init