Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx

35 files changed, 1203 insertions, 1762 deletions

diff --git a/board/freescale/mpc8540ads/Makefile b/board/freescale/mpc8540ads/Makefile
index 2913650..be24388 100644
--- a/board/freescale/mpc8540ads/Makefile
+++ b/board/freescale/mpc8540ads/Makefile
@@ -25,9 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o
-SOBJS	:= init.o
-#SOBJS	:=
+COBJS	:= $(BOARD).o law.o tlb.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/freescale/mpc8540ads/init.S b/board/freescale/mpc8540ads/init.S
deleted file mode 100644
index 74d71c6..0000000
--- a/board/freescale/mpc8540ads/init.S
+++ /dev/null
@@ -1,265 +0,0 @@
-/*
- * Copyright 2004 Freescale Semiconductor.
- * Copyright (C) 2002,2003, Motorola Inc.
- * Xianghua Xiao <X.Xiao@motorola.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-#include <asm/cache.h>
-#include <asm/mmu.h>
-#include <config.h>
-#include <mpc85xx.h>
-
-
-/*
- * TLB0 and TLB1 Entries
- *
- * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
- * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
- * these TLB entries are established.
- *
- * The TLB entries for DDR are dynamically setup in spd_sdram()
- * and use TLB1 Entries 8 through 15 as needed according to the
- * size of DDR memory.
- *
- * MAS0: tlbsel, esel, nv
- * MAS1: valid, iprot, tid, ts, tsize
- * MAS2: epn, x0, x1, w, i, m, g, e
- * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
- */
-
-#define	entry_start \
-	mflr	r1 	;	\
-	bl	0f 	;
-
-#define	entry_end \
-0:	mflr	r0	;	\
-	mtlr	r1	;	\
-	blr		;
-
-
-	.section	.bootpg, "ax"
-	.globl	tlb1_entry
-tlb1_entry:
-	entry_start
-
-	/*
-	 * Number of TLB0 and TLB1 entries in the following table
-	 */
-	.long 13
-
-#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
-	/*
-	 * TLB0		4K	Non-cacheable, guarded
-	 * 0xff700000	4K	Initial CCSRBAR mapping
-	 *
-	 * This ends up at a TLB0 Index==0 entry, and must not collide
-	 * with other TLB0 Entries.
-	 */
-	.long FSL_BOOKE_MAS0(0, 0, 0)
-	.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
-	.long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-#else
-#error("Update the number of table entries in tlb1_entry")
-#endif
-
-	/*
-	 * TLB0		16K	Cacheable, non-guarded
-	 * 0xd001_0000	16K	Temporary Global data for initialization
-	 *
-	 * Use four 4K TLB0 entries.  These entries must be cacheable
-	 * as they provide the bootstrap memory before the memory
-	 * controler and real memory have been configured.
-	 *
-	 * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
-	 * and must not collide with other TLB0 entries.
-	 */
-	.long FSL_BOOKE_MAS0(0, 0, 0)
-	.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
-	.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)
-	.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	.long FSL_BOOKE_MAS0(0, 0, 0)
-	.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
-	.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4*1024, 0)
-	.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4*1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	.long FSL_BOOKE_MAS0(0, 0, 0)
-	.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
-	.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8*1024, 0)
-	.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8*1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	.long FSL_BOOKE_MAS0(0, 0, 0)
-	.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
-	.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12*1024, 0)
-	.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12*1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/*
-	 * TLB 0:	16M	Non-cacheable, guarded
-	 * 0xff000000	16M	FLASH
-	 * Out of reset this entry is only 4K.
-	 */
-	.long FSL_BOOKE_MAS0(1, 0, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
-	.long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/*
-	 * TLB 1:	256M	Non-cacheable, guarded
-	 * 0x80000000	256M	PCI1 MEM First half
-	 */
-	.long FSL_BOOKE_MAS0(1, 1, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-	.long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/*
-	 * TLB 2:	256M	Non-cacheable, guarded
-	 * 0x90000000	256M	PCI1 MEM Second half
-	 */
-	.long FSL_BOOKE_MAS0(1, 2, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-	.long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/*
-	 * TLB 3:	256M	Non-cacheable, guarded
-	 * 0xc0000000	256M	Rapid IO MEM First half
-	 */
-	.long FSL_BOOKE_MAS0(1, 3, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-	.long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/*
-	 * TLB 4:	256M	Non-cacheable, guarded
-	 * 0xd0000000	256M	Rapid IO MEM Second half
-	 */
-	.long FSL_BOOKE_MAS0(1, 4, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-	.long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/*
-	 * TLB 5:	64M	Non-cacheable, guarded
-	 * 0xe000_0000	1M	CCSRBAR
-	 * 0xe200_0000	16M	PCI1 IO
-	 */
-	.long FSL_BOOKE_MAS0(1, 5, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-	.long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/*
-	 * TLB 6:	64M	Cacheable, non-guarded
-	 * 0xf000_0000	64M	LBC SDRAM
-	 */
-	.long FSL_BOOKE_MAS0(1, 6, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-	.long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0)
-	.long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/*
-	 * TLB 7:	16K	Non-cacheable, guarded
-	 * 0xf8000000	16K	BCSR registers
-	 */
-	.long FSL_BOOKE_MAS0(1, 7, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K)
-	.long FSL_BOOKE_MAS2(CFG_BCSR, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_BCSR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-#if !defined(CONFIG_SPD_EEPROM)
-	/*
-	 * TLB 8, 9:	128M	DDR
-	 * 0x00000000	64M	DDR System memory
-	 * 0x04000000	64M	DDR System memory
-	 * Without SPD EEPROM configured DDR, this must be setup manually.
-	 * Make sure the TLB count at the top of this table is correct.
-	 * Likely it needs to be increased by two for these entries.
-	 */
-#error("Update the number of table entries in tlb1_entry")
-	.long FSL_BOOKE_MAS0(1, 8, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-	.long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE, 0)
-	.long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	.long FSL_BOOKE_MAS0(1, 9, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-	.long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE + 0x4000000, 0)
-	.long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE + 0x4000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-#endif
-
-	entry_end
-
-/*
- * LAW(Local Access Window) configuration:
- *
- * 0x0000_0000     0x7fff_ffff     DDR                     2G
- * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
- * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
- * 0xe000_0000     0xe000_ffff     CCSR                    1M
- * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
- * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
- * 0xf800_0000     0xf80f_ffff     BCSR                    1M
- * 0xff00_0000     0xffff_ffff     FLASH (boot bank)       16M
- *
- * Notes:
- *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- *    If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-#if !defined(CONFIG_SPD_EEPROM)
-#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
-#define LAWAR0	(LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
-#else
-#define LAWBAR0 0
-#define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
-#endif
-
-#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
-#define LAWAR1	(LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-/*
- * This is not so much the SDRAM map as it is the whole localbus map.
- */
-#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
-#define LAWAR2	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
-
-#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
-#define LAWAR3	(LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_1M))
-
-/*
- * Rapid IO at 0xc000_0000 for 512 M
- */
-#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
-#define LAWAR4	(LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-
-	.section .bootpg, "ax"
-	.globl	law_entry
-law_entry:
-	entry_start
-	.long 0x05
-	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
-	.long LAWBAR4,LAWAR4
-	entry_end
diff --git a/board/freescale/mpc8540ads/law.c b/board/freescale/mpc8540ads/law.c
new file mode 100644
index 0000000..785576a
--- /dev/null
+++ b/board/freescale/mpc8540ads/law.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x7fff_ffff     DDR                     2G
+ * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
+ * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
+ * 0xe000_0000     0xe000_ffff     CCSR                    1M
+ * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
+ * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
+ * 0xf800_0000     0xf80f_ffff     BCSR                    1M
+ * 0xff00_0000     0xffff_ffff     FLASH (boot bank)       16M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+#ifndef CONFIG_SPD_EEPROM
+	SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
+#endif
+	SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+	/* This is not so much the SDRAM map as it is the whole localbus map. */
+	SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
+	SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8540ads/tlb.c b/board/freescale/mpc8540ads/tlb.c
new file mode 100644
index 0000000..3eaff01
--- /dev/null
+++ b/board/freescale/mpc8540ads/tlb.c
@@ -0,0 +1,130 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/*
+	 * TLB 0:	16M	Non-cacheable, guarded
+	 * 0xff000000	16M	FLASH
+	 * Out of reset this entry is only 4K.
+	 */
+	SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_16M, 1),
+
+	/*
+	 * TLB 1:	256M	Non-cacheable, guarded
+	 * 0x80000000	256M	PCI1 MEM First half
+	 */
+	SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 2:	256M	Non-cacheable, guarded
+	 * 0x90000000	256M	PCI1 MEM Second half
+	 */
+	SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 3:	256M	Non-cacheable, guarded
+	 * 0xc0000000	256M	Rapid IO MEM First half
+	 */
+	SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 4:	256M	Non-cacheable, guarded
+	 * 0xd0000000	256M	Rapid IO MEM Second half
+	 */
+	SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 5:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe200_0000	16M	PCI1 IO
+	 */
+	SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 6:	64M	Cacheable, non-guarded
+	 * 0xf000_0000	64M	LBC SDRAM
+	 */
+	SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 6, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 7:	16K	Non-cacheable, guarded
+	 * 0xf8000000	16K	BCSR registers
+	 */
+	SET_TLB_ENTRY(1, CFG_BCSR, CFG_BCSR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 7, BOOKE_PAGESZ_16K, 1),
+
+#if !defined(CONFIG_SPD_EEPROM)
+	/*
+	 * TLB 8, 9:	128M	DDR
+	 * 0x00000000	64M	DDR System memory
+	 * 0x04000000	64M	DDR System memory
+	 * Without SPD EEPROM configured DDR, this must be setup manually.
+	 * Make sure the TLB count at the top of this table is correct.
+	 * Likely it needs to be increased by two for these entries.
+	 */
+#error("Update the number of table entries in tlb1_entry")
+	SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 8, BOOKE_PAGESZ_64M, 1),
+
+	SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x4000000, CFG_DDR_SDRAM_BASE + 0x4000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 9, BOOKE_PAGESZ_64M, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/mpc8540ads/u-boot.lds b/board/freescale/mpc8540ads/u-boot.lds
index bc0db55..86f8f13 100644
--- a/board/freescale/mpc8540ads/u-boot.lds
+++ b/board/freescale/mpc8540ads/u-boot.lds
@@ -35,7 +35,6 @@ SECTIONS
   .bootpg 0xFFFFF000 :
   {
     cpu/mpc85xx/start.o	(.bootpg)
-    board/freescale/mpc8540ads/init.o (.bootpg)
   } = 0xffff
 
   /* Read-only sections, merged into text segment: */
@@ -65,7 +64,6 @@ SECTIONS
   .text      :
   {
     cpu/mpc85xx/start.o	(.text)
-    board/freescale/mpc8540ads/init.o (.text)
     cpu/mpc85xx/traps.o (.text)
     cpu/mpc85xx/interrupts.o (.text)
     cpu/mpc85xx/cpu_init.o (.text)
diff --git a/board/freescale/mpc8541cds/Makefile b/board/freescale/mpc8541cds/Makefile
index 7f53098..d1a585a 100644
--- a/board/freescale/mpc8541cds/Makefile
+++ b/board/freescale/mpc8541cds/Makefile
@@ -29,14 +29,12 @@ endif
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o \
+COBJS	:= $(BOARD).o law.o tlb.o \
 	   ../common/cadmus.o \
 	   ../common/eeprom.o \
 	   ../common/ft_board.o \
 	   ../common/via.o
 
-SOBJS	:= init.o
-
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
diff --git a/board/freescale/mpc8541cds/init.S b/board/freescale/mpc8541cds/init.S
deleted file mode 100644
index 8c8c087c..0000000
--- a/board/freescale/mpc8541cds/init.S
+++ /dev/null
@@ -1,243 +0,0 @@
-/*
- * Copyright 2004 Freescale Semiconductor.
- * Copyright 2002,2003, Motorola Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-#include <asm/cache.h>
-#include <asm/mmu.h>
-#include <config.h>
-#include <mpc85xx.h>
-
-
-/*
- * TLB0 and TLB1 Entries
- *
- * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
- * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
- * these TLB entries are established.
- *
- * The TLB entries for DDR are dynamically setup in spd_sdram()
- * and use TLB1 Entries 8 through 15 as needed according to the
- * size of DDR memory.
- *
- * MAS0: tlbsel, esel, nv
- * MAS1: valid, iprot, tid, ts, tsize
- * MAS2: epn, x0, x1, w, i, m, g, e
- * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
- */
-
-#define	entry_start \
-	mflr	r1 	;	\
-	bl	0f 	;
-
-#define	entry_end \
-0:	mflr	r0	;	\
-	mtlr	r1	;	\
-	blr		;
-
-
-	.section	.bootpg, "ax"
-	.globl	tlb1_entry
-tlb1_entry:
-	entry_start
-
-	/*
-	 * Number of TLB0 and TLB1 entries in the following table
-	 */
-	.long 13
-
-#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
-	/*
-	 * TLB0		4K	Non-cacheable, guarded
-	 * 0xff700000	4K	Initial CCSRBAR mapping
-	 *
-	 * This ends up at a TLB0 Index==0 entry, and must not collide
-	 * with other TLB0 Entries.
-	 */
-	.long FSL_BOOKE_MAS0(0, 0, 0)
-	.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
-	.long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-#else
-#error("Update the number of table entries in tlb1_entry")
-#endif
-
-	/*
-	 * TLB0		16K	Cacheable, non-guarded
-	 * 0xd001_0000	16K	Temporary Global data for initialization
-	 *
-	 * Use four 4K TLB0 entries.  These entries must be cacheable
-	 * as they provide the bootstrap memory before the memory
-	 * controler and real memory have been configured.
-	 *
-	 * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
-	 * and must not collide with other TLB0 entries.
-	 */
-	.long FSL_BOOKE_MAS0(0, 0, 0)
-	.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
-	.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)
-	.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	.long FSL_BOOKE_MAS0(0, 0, 0)
-	.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
-	.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0)
-	.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	.long FSL_BOOKE_MAS0(0, 0, 0)
-	.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
-	.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0)
-	.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	.long FSL_BOOKE_MAS0(0, 0, 0)
-	.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
-	.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0)
-	.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-
-	/*
-	 * TLB 0:	16M	Non-cacheable, guarded
-	 * 0xff000000	16M	FLASH
-	 * Out of reset this entry is only 4K.
-	 */
-	.long FSL_BOOKE_MAS0(1, 0, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
-	.long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/*
-	 * TLB 1:	256M	Non-cacheable, guarded
-	 * 0x80000000	256M	PCI1 MEM First half
-	 */
-	.long FSL_BOOKE_MAS0(1, 1, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-	.long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/*
-	 * TLB 2:	256M	Non-cacheable, guarded
-	 * 0x90000000	256M	PCI1 MEM Second half
-	 */
-	.long FSL_BOOKE_MAS0(1, 2, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-	.long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/*
-	 * TLB 3:	256M	Non-cacheable, guarded
-	 * 0xa0000000	256M	PCI2 MEM First half
-	 */
-	.long FSL_BOOKE_MAS0(1, 3, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-	.long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/*
-	 * TLB 4:	256M	Non-cacheable, guarded
-	 * 0xb0000000	256M	PCI2 MEM Second half
-	 */
-	.long FSL_BOOKE_MAS0(1, 4, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-	.long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/*
-	 * TLB 5:	64M	Non-cacheable, guarded
-	 * 0xe000_0000	1M	CCSRBAR
-	 * 0xe200_0000	16M	PCI1 IO
-	 * 0xe300_0000	16M	PCI2 IO
-	 */
-	.long FSL_BOOKE_MAS0(1, 5, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-	.long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/*
-	 * TLB 6:	64M	Cacheable, non-guarded
-	 * 0xf000_0000	64M	LBC SDRAM
-	 */
-	.long FSL_BOOKE_MAS0(1, 6, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-	.long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0)
-	.long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/*
-	 * TLB 7:	1M	Non-cacheable, guarded
-	 * 0xf8000000	1M	CADMUS registers
-	 */
-	.long FSL_BOOKE_MAS0(1, 7, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)
-	.long FSL_BOOKE_MAS2(CADMUS_BASE_ADDR, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CADMUS_BASE_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	entry_end
-
-/*
- * LAW(Local Access Window) configuration:
- *
- * 0x0000_0000     0x7fff_ffff     DDR                     2G
- * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
- * 0xa000_0000     0xbfff_ffff     PCI2 MEM                512M
- * 0xe000_0000     0xe000_ffff     CCSR                    1M
- * 0xe200_0000     0xe20f_ffff     PCI1 IO                 1M
- * 0xe210_0000     0xe21f_ffff     PCI2 IO                 1M
- * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
- * 0xf800_0000     0xf80f_ffff     NVRAM/CADMUS (*)        1M
- * 0xff00_0000     0xff7f_ffff     FLASH (2nd bank)        8M
- * 0xff80_0000     0xffff_ffff     FLASH (boot bank)       8M
- *
- * Notes:
- *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- *    If flash is 8M at default position (last 8M), no LAW needed.
- *
- * The defines below are 1-off of the actual LAWAR0 usage.
- * So LAWAR3 define uses the LAWAR4 register in the ECM.
- */
-
-#define LAWBAR0 0
-#define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
-
-#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
-#define LAWAR1 	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
-#define LAWAR2 	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
-#define LAWAR3 	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
-
-#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff)
-#define LAWAR4 	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M))
-
-/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
-#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
-#define LAWAR5 	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
-
-	.section .bootpg, "ax"
-	.globl	law_entry
-
-law_entry:
-	entry_start
-	.long 6
-	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
-	.long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5
-	entry_end
diff --git a/board/freescale/mpc8541cds/law.c b/board/freescale/mpc8541cds/law.c
new file mode 100644
index 0000000..0ac223c
--- /dev/null
+++ b/board/freescale/mpc8541cds/law.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x7fff_ffff     DDR                     2G
+ * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
+ * 0xa000_0000     0xbfff_ffff     PCI2 MEM                512M
+ * 0xe000_0000     0xe000_ffff     CCSR                    1M
+ * 0xe200_0000     0xe20f_ffff     PCI1 IO                 1M
+ * 0xe210_0000     0xe21f_ffff     PCI2 IO                 1M
+ * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
+ * 0xf800_0000     0xf80f_ffff     NVRAM/CADMUS (*)        1M
+ * 0xff00_0000     0xff7f_ffff     FLASH (2nd bank)        8M
+ * 0xff80_0000     0xffff_ffff     FLASH (boot bank)       8M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+	SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+	SET_LAW_ENTRY(3, CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+	SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
+	SET_LAW_ENTRY(5, CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
+	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+	SET_LAW_ENTRY(6, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8541cds/tlb.c b/board/freescale/mpc8541cds/tlb.c
new file mode 100644
index 0000000..92f759b
--- /dev/null
+++ b/board/freescale/mpc8541cds/tlb.c
@@ -0,0 +1,112 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/*
+	 * TLB 0:	16M	Non-cacheable, guarded
+	 * 0xff000000	16M	FLASH
+	 * Out of reset this entry is only 4K.
+	 */
+	SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_16M, 1),
+
+	/*
+	 * TLB 1:	256M	Non-cacheable, guarded
+	 * 0x80000000	256M	PCI1 MEM First half
+	 */
+	SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 2:	256M	Non-cacheable, guarded
+	 * 0x90000000	256M	PCI1 MEM Second half
+	 */
+	SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 3:	256M	Non-cacheable, guarded
+	 * 0xa0000000	256M	PCI2 MEM First half
+	 */
+	SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS, CFG_PCI2_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 4:	256M	Non-cacheable, guarded
+	 * 0xb0000000	256M	PCI2 MEM Second half
+	 */
+	SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS + 0x10000000, CFG_PCI2_MEM_PHYS + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 5:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe200_0000	16M	PCI1 IO
+	 * 0xe300_0000	16M	PCI2 IO
+	 */
+	SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 6:	64M	Cacheable, non-guarded
+	 * 0xf000_0000	64M	LBC SDRAM
+	 */
+	SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 6, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 7:	1M	Non-cacheable, guarded
+	 * 0xf8000000	1M	CADMUS registers
+	 */
+	SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 7, BOOKE_PAGESZ_1M, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/mpc8541cds/u-boot.lds b/board/freescale/mpc8541cds/u-boot.lds
index 1e490d0..1cbadf2 100644
--- a/board/freescale/mpc8541cds/u-boot.lds
+++ b/board/freescale/mpc8541cds/u-boot.lds
@@ -34,7 +34,6 @@ SECTIONS
   .bootpg 0xFFFFF000 :
   {
     cpu/mpc85xx/start.o	(.bootpg)
-    board/freescale/mpc8541cds/init.o (.bootpg)
   } = 0xffff
 
   /* Read-only sections, merged into text segment: */
@@ -64,7 +63,6 @@ SECTIONS
   .text      :
   {
     cpu/mpc85xx/start.o	(.text)
-    board/freescale/mpc8541cds/init.o (.text)
     cpu/mpc85xx/traps.o (.text)
     cpu/mpc85xx/interrupts.o (.text)
     cpu/mpc85xx/cpu_init.o (.text)
diff --git a/board/freescale/mpc8544ds/Makefile b/board/freescale/mpc8544ds/Makefile
index c6f159a..53368b2 100644
--- a/board/freescale/mpc8544ds/Makefile
+++ b/board/freescale/mpc8544ds/Makefile
@@ -26,9 +26,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o
-
-SOBJS	:= init.o
+COBJS	:= $(BOARD).o law.o tlb.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/freescale/mpc8544ds/init.S b/board/freescale/mpc8544ds/init.S
deleted file mode 100644
index 544dc07..0000000
--- a/board/freescale/mpc8544ds/init.S
+++ /dev/null
@@ -1,222 +0,0 @@
-/*
- * Copyright 2007 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-#include <asm/cache.h>
-#include <asm/mmu.h>
-#include <config.h>
-#include <mpc85xx.h>
-
-/*
- * TLB0 and TLB1 Entries
- *
- * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
- * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
- * these TLB entries are established.
- *
- * The TLB entries for DDR are dynamically setup in spd_sdram()
- * and use TLB1 Entries 8 through 15 as needed according to the
- * size of DDR memory.
- *
- * MAS0: tlbsel, esel, nv
- * MAS1: valid, iprot, tid, ts, tsize
- * MAS2: epn, x0, x1, w, i, m, g, e
- * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
- */
-
-#define	entry_start \
-	mflr	r1	;	\
-	bl	0f	;
-
-#define	entry_end \
-0:	mflr	r0	;	\
-	mtlr	r1	;	\
-	blr		;
-
-
-	.section	.bootpg, "ax"
-	.globl	tlb1_entry
-tlb1_entry:
-	entry_start
-
-	/*
-	 * Number of TLB0 and TLB1 entries in the following table
-	 */
-	.long (2f-1f)/16
-1:
-	/*
-	 * TLB0		4K	Non-cacheable, guarded
-	 * 0xff700000	4K	Initial CCSRBAR mapping
-	 *
-	 * This ends up at a TLB0 Index==0 entry, and must not collide
-	 * with other TLB0 Entries.
-	 */
-	.long FSL_BOOKE_MAS0(0, 0, 0)
-	.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
-	.long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/*
-	 * TLB0		16K	Cacheable, guarded
-	 * Temporary Global data for initialization
-	 *
-	 * Use four 4K TLB0 entries.  These entries must be cacheable
-	 * as they provide the bootstrap memory before the memory
-	 * controler and real memory have been configured.
-	 *
-	 * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
-	 * and must not collide with other TLB0 entries.
-	 */
-	.long FSL_BOOKE_MAS0(0, 0, 0)
-	.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
-	.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, (MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	.long FSL_BOOKE_MAS0(0, 0, 0)
-	.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
-	.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, (MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	.long FSL_BOOKE_MAS0(0, 0, 0)
-	.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
-	.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, (MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	.long FSL_BOOKE_MAS0(0, 0, 0)
-	.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
-	.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, (MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-
-	/*
-	 * TLB 0:	64M	Non-cacheable, guarded
-	 * 0xfc000000	64M	Covers FLASH at 0xFE800000 and 0xFF800000
-	 * Out of reset this entry is only 4K.
-	 */
-	.long FSL_BOOKE_MAS0(1, 0, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-	.long FSL_BOOKE_MAS2(CFG_BOOT_BLOCK, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_BOOT_BLOCK, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/*
-	 * TLB 1:	1G	Non-cacheable, guarded
-	 * 0x80000000	1G	PCIE  8,9,a,b
-	 */
-	.long FSL_BOOKE_MAS0(1, 1, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
-	.long FSL_BOOKE_MAS2(CFG_PCIE_PHYS, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_PCIE_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/*
-	 * TLB 2:	256M	Non-cacheable, guarded
-	 */
-	.long FSL_BOOKE_MAS0(1, 2, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-	.long FSL_BOOKE_MAS2(CFG_PCI_PHYS, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_PCI_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/*
-	 * TLB 3:	256M	Non-cacheable, guarded
-	 */
-	.long FSL_BOOKE_MAS0(1, 3, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-	.long FSL_BOOKE_MAS2(CFG_PCI_PHYS + 0x10000000, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_PCI_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/*
-	 * TLB 4:	64M	Non-cacheable, guarded
-	 * 0xe000_0000	1M	CCSRBAR
-	 * 0xe100_0000	255M	PCI IO range
-	 */
-	.long FSL_BOOKE_MAS0(1, 4, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-	.long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-#ifdef CFG_LBC_CACHE_BASE
-	/*
-	 * TLB 5:	64M	Cacheable, non-guarded
-	 */
-	.long FSL_BOOKE_MAS0(1, 5, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-	.long FSL_BOOKE_MAS2(CFG_LBC_CACHE_BASE, 0)
-	.long FSL_BOOKE_MAS3(CFG_LBC_CACHE_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-#endif
-	/*
-	 * TLB 6:	64M	Non-cacheable, guarded
-	 * 0xf8000000	64M	PIXIS 0xF8000000 - 0xFBFFFFFF
-	 */
-	.long FSL_BOOKE_MAS0(1, 6, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-	.long FSL_BOOKE_MAS2(CFG_LBC_NONCACHE_BASE, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_LBC_NONCACHE_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-2:
-	entry_end
-
-/*
- * LAW(Local Access Window) configuration:
- *
- *
- * Notes:
- *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- *    If flash is 8M at default position (last 8M), no LAW needed.
- *
- * LAW 0 is reserved for boot mapping
- */
-
-	.section .bootpg, "ax"
-	.globl	law_entry
-law_entry:
-	entry_start
-
-	.long (4f-3f)/8
-3:
-	.long	0
-	.long	(LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
-
-	.long	(CFG_PCI1_MEM_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
-
-	.long	(CFG_PCI1_IO_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
-
-	.long	(CFG_LBC_CACHE_BASE>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
-
-	.long	(CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M)
-
-	.long	(CFG_PCIE1_IO_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
-
-	.long	(CFG_PCIE2_MEM_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_IF_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
-
-	.long	(CFG_PCIE2_IO_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_IF_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_64K)
-
-	/* contains both PCIE3 MEM & IO space */
-	.long	(CFG_PCIE3_MEM_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_IF_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_4M)
-4:
-	entry_end
diff --git a/board/freescale/mpc8544ds/law.c b/board/freescale/mpc8544ds/law.c
new file mode 100644
index 0000000..433e509
--- /dev/null
+++ b/board/freescale/mpc8544ds/law.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+	SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+	SET_LAW_ENTRY(3, CFG_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI),
+	SET_LAW_ENTRY(4, CFG_LBC_CACHE_BASE, LAWAR_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW_ENTRY(5, CFG_PCIE1_MEM_PHYS, LAWAR_SIZE_256M, LAW_TRGT_IF_PCIE_1),
+	SET_LAW_ENTRY(6, CFG_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
+	SET_LAW_ENTRY(7, CFG_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2),
+	SET_LAW_ENTRY(8, CFG_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
+	/* contains both PCIE3 MEM & IO space */
+	SET_LAW_ENTRY(9, CFG_PCIE3_MEM_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_PCIE_3),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8544ds/tlb.c b/board/freescale/mpc8544ds/tlb.c
new file mode 100644
index 0000000..34cfb38
--- /dev/null
+++ b/board/freescale/mpc8544ds/tlb.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	/*
+	 * TLB 0:	64M	Non-cacheable, guarded
+	 * 0xfc000000	64M	Covers FLASH at 0xFE800000 and 0xFF800000
+	 * Out of reset this entry is only 4K.
+	 */
+	SET_TLB_ENTRY(1, CFG_BOOT_BLOCK, CFG_BOOT_BLOCK,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_64M, 1),
+	/*
+	 * TLB 1:	1G	Non-cacheable, guarded
+	 * 0x80000000	1G	PCIE  8,9,a,b
+	 */
+	SET_TLB_ENTRY(1, CFG_PCIE_PHYS, CFG_PCIE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_1G, 1),
+
+	/*
+	 * TLB 2:	256M	Non-cacheable, guarded
+	 */
+	SET_TLB_ENTRY(1, CFG_PCI_PHYS, CFG_PCI_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 3:	256M	Non-cacheable, guarded
+	 */
+	SET_TLB_ENTRY(1, CFG_PCI_PHYS + 0x10000000, CFG_PCI_PHYS + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 4:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe100_0000	255M	PCI IO range
+	 */
+	SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_64M, 1),
+
+#ifdef CFG_LBC_CACHE_BASE
+	/*
+	 * TLB 5:	64M	Cacheable, non-guarded
+	 */
+	SET_TLB_ENTRY(1, CFG_LBC_CACHE_BASE, CFG_LBC_CACHE_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 5, BOOKE_PAGESZ_64M, 1),
+#endif
+	/*
+	 * TLB 6:	64M	Non-cacheable, guarded
+	 * 0xf8000000	64M	PIXIS 0xF8000000 - 0xFBFFFFFF
+	 */
+	SET_TLB_ENTRY(1, CFG_LBC_NONCACHE_BASE, CFG_LBC_NONCACHE_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 6, BOOKE_PAGESZ_64M, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/mpc8544ds/u-boot.lds b/board/freescale/mpc8544ds/u-boot.lds
index 66bd4b6..17db8c0 100644
--- a/board/freescale/mpc8544ds/u-boot.lds
+++ b/board/freescale/mpc8544ds/u-boot.lds
@@ -34,7 +34,6 @@ SECTIONS
   .bootpg 0xFFFFF000 :
   {
     cpu/mpc85xx/start.o	(.bootpg)
-    board/freescale/mpc8544ds/init.o (.bootpg)
   } = 0xffff
 
   /* Read-only sections, merged into text segment: */
@@ -64,7 +63,6 @@ SECTIONS
   .text      :
   {
     cpu/mpc85xx/start.o	(.text)
-    board/freescale/mpc8544ds/init.o (.text)
     cpu/mpc85xx/traps.o (.text)
     cpu/mpc85xx/interrupts.o (.text)
     cpu/mpc85xx/cpu_init.o (.text)
diff --git a/board/freescale/mpc8548cds/Makefile b/board/freescale/mpc8548cds/Makefile
index 7f53098..d1a585a 100644
--- a/board/freescale/mpc8548cds/Makefile
+++ b/board/freescale/mpc8548cds/Makefile
@@ -29,14 +29,12 @@ endif
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o \
+COBJS	:= $(BOARD).o law.o tlb.o \
 	   ../common/cadmus.o \
 	   ../common/eeprom.o \
 	   ../common/ft_board.o \
 	   ../common/via.o
 
-SOBJS	:= init.o
-
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
diff --git a/board/freescale/mpc8548cds/init.S b/board/freescale/mpc8548cds/init.S
deleted file mode 100644
index ed0fc44..0000000
--- a/board/freescale/mpc8548cds/init.S
+++ /dev/null
@@ -1,252 +0,0 @@
-/*
- * Copyright 2004, 2007 Freescale Semiconductor.
- * Copyright 2002,2003, Motorola Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-#include <asm/cache.h>
-#include <asm/mmu.h>
-#include <config.h>
-#include <mpc85xx.h>
-
-/*
- * TLB0 and TLB1 Entries
- *
- * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
- * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
- * these TLB entries are established.
- *
- * The TLB entries for DDR are dynamically setup in spd_sdram()
- * and use TLB1 Entries 8 through 15 as needed according to the
- * size of DDR memory.
- *
- * MAS0: tlbsel, esel, nv
- * MAS1: valid, iprot, tid, ts, tsize
- * MAS2: epn, x0, x1, w, i, m, g, e
- * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
- */
-
-#define	entry_start \
-	mflr	r1	;	\
-	bl	0f	;
-
-#define	entry_end \
-0:	mflr	r0	;	\
-	mtlr	r1	;	\
-	blr		;
-
-
-	.section	.bootpg, "ax"
-	.globl	tlb1_entry
-tlb1_entry:
-	entry_start
-
-	/*
-	 * Number of TLB0 and TLB1 entries in the following table
-	 */
-	.long (2f-1f)/16
-
-1:
-#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
-	/*
-	 * TLB0		4K	Non-cacheable, guarded
-	 * 0xff700000	4K	Initial CCSRBAR mapping
-	 *
-	 * This ends up at a TLB0 Index==0 entry, and must not collide
-	 * with other TLB0 Entries.
-	 */
-	.long FSL_BOOKE_MAS0(0, 0, 0)
-	.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
-	.long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-#else
-#error("Update the number of table entries in tlb1_entry")
-#endif
-
-	/*
-	 * TLB0		16K	Cacheable, guarded
-	 * Temporary Global data for initialization
-	 *
-	 * Use four 4K TLB0 entries.  These entries must be cacheable
-	 * as they provide the bootstrap memory before the memory
-	 * controler and real memory have been configured.
-	 *
-	 * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
-	 * and must not collide with other TLB0 entries.
-	 */
-	.long FSL_BOOKE_MAS0(0, 0, 0)
-	.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
-	.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, (MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	.long FSL_BOOKE_MAS0(0, 0, 0)
-	.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
-	.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, (MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	.long FSL_BOOKE_MAS0(0, 0, 0)
-	.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
-	.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, (MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	.long FSL_BOOKE_MAS0(0, 0, 0)
-	.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
-	.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, (MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-
-	/*
-	 * TLB 0:	16M	Non-cacheable, guarded
-	 * 0xff000000	16M	FLASH
-	 * Out of reset this entry is only 4K.
-	 */
-	.long FSL_BOOKE_MAS0(1, 0, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
-	.long FSL_BOOKE_MAS2(CFG_BOOT_BLOCK, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_BOOT_BLOCK, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/*
-	 * TLB 1:	1G	Non-cacheable, guarded
-	 * 0x80000000	1G	PCI1/PCIE  8,9,a,b
-	 */
-	.long FSL_BOOKE_MAS0(1, 1, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
-	.long FSL_BOOKE_MAS2(CFG_PCI_PHYS, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_PCI_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-#ifdef CFG_RIO_MEM_PHYS
-	/*
-	 * TLB 2:	256M	Non-cacheable, guarded
-	 */
-	.long FSL_BOOKE_MAS0(1, 2, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-	.long FSL_BOOKE_MAS2(CFG_RIO_MEM_PHYS, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_RIO_MEM_PHYS,	0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/*
-	 * TLB 3:	256M	Non-cacheable, guarded
-	 */
-	.long FSL_BOOKE_MAS0(1, 3, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-	.long FSL_BOOKE_MAS2(CFG_RIO_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_RIO_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-#endif
-	/*
-	 * TLB 5:	64M	Non-cacheable, guarded
-	 * 0xe000_0000	1M	CCSRBAR
-	 * 0xe200_0000	1M	PCI1 IO
-	 * 0xe210_0000	1M	PCI2 IO
-	 * 0xe300_0000	1M	PCIe IO
-	 */
-	.long FSL_BOOKE_MAS0(1, 5, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-	.long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/*
-	 * TLB 6:	64M	Cacheable, non-guarded
-	 * 0xf000_0000	64M	LBC SDRAM
-	 */
-	.long FSL_BOOKE_MAS0(1, 6, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-	.long FSL_BOOKE_MAS2(CFG_LBC_CACHE_BASE, 0)
-	.long FSL_BOOKE_MAS3(CFG_LBC_CACHE_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/*
-	 * TLB 7:	64M	Non-cacheable, guarded
-	 * 0xf8000000	64M	CADMUS registers, relocated L2SRAM
-	 */
-	.long FSL_BOOKE_MAS0(1, 7, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-	.long FSL_BOOKE_MAS2(CFG_LBC_NONCACHE_BASE, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_LBC_NONCACHE_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-2:
-	entry_end
-
-/*
- * LAW(Local Access Window) configuration:
- *
- * 0x0000_0000     0x7fff_ffff     DDR                     2G
- * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
- * 0xa000_0000     0xbfff_ffff     PCIe MEM                512M
- * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
- * 0xe000_0000     0xe000_ffff     CCSR                    1M
- * 0xe200_0000     0xe10f_ffff     PCI1 IO                 1M
- * 0xe280_0000     0xe20f_ffff     PCI2 IO                 1M
- * 0xe300_0000     0xe30f_ffff     PCIe IO                 1M
- * 0xf000_0000     0xf3ff_ffff     SDRAM                   64M
- * 0xf800_0000     0xf80f_ffff     NVRAM/CADMUS (*)        1M
- * 0xff00_0000     0xff7f_ffff     FLASH (2nd bank)        8M
- * 0xff80_0000     0xffff_ffff     FLASH (boot bank)       8M
- *
- * Notes:
- *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- *    If flash is 8M at default position (last 8M), no LAW needed.
- *
- * LAW 0 is reserved for boot mapping
- */
-
-	.section .bootpg, "ax"
-	.globl	law_entry
-law_entry:
-	entry_start
-
-	.long (4f-3f)/8
-3:
-	.long  0
-	.long  (LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
-
-#ifdef CFG_PCI1_MEM_PHYS
-	.long	(CFG_PCI1_MEM_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
-
-	.long	(CFG_PCI1_IO_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
-#endif
-
-#ifdef CFG_PCI2_MEM_PHYS
-	.long	(CFG_PCI2_MEM_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
-
-	.long	(CFG_PCI2_IO_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)
-#endif
-
-#ifdef CFG_PCIE1_MEM_PHYS
-	.long	(CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
-
-	.long	(CFG_PCIE1_IO_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
-#endif
-
-	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
-	.long	(CFG_LBC_CACHE_BASE>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
-
-#ifdef CFG_RIO_MEM_PHYS
-	.long	(CFG_RIO_MEM_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)
-#endif
-4:
-	entry_end
diff --git a/board/freescale/mpc8548cds/law.c b/board/freescale/mpc8548cds/law.c
new file mode 100644
index 0000000..0ee53e2
--- /dev/null
+++ b/board/freescale/mpc8548cds/law.c
@@ -0,0 +1,73 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x7fff_ffff     DDR                     2G
+ * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
+ * 0xa000_0000     0xbfff_ffff     PCIe MEM                512M
+ * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
+ * 0xe000_0000     0xe000_ffff     CCSR                    1M
+ * 0xe200_0000     0xe10f_ffff     PCI1 IO                 1M
+ * 0xe280_0000     0xe20f_ffff     PCI2 IO                 1M
+ * 0xe300_0000     0xe30f_ffff     PCIe IO                 1M
+ * 0xf000_0000     0xf3ff_ffff     SDRAM                   64M
+ * 0xf800_0000     0xf80f_ffff     NVRAM/CADMUS (*)        1M
+ * 0xff00_0000     0xff7f_ffff     FLASH (2nd bank)        8M
+ * 0xff80_0000     0xffff_ffff     FLASH (boot bank)       8M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ * LAW 0 is reserved for boot mapping
+ */
+
+struct law_entry law_table[] = {
+#ifdef CFG_PCI1_MEM_PHYS
+	SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+	SET_LAW_ENTRY(3, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
+#endif
+#ifdef CFG_PCI2_MEM_PHYS
+	SET_LAW_ENTRY(4, CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+	SET_LAW_ENTRY(5, CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
+#endif
+#ifdef CFG_PCIE1_MEM_PHYS
+	SET_LAW_ENTRY(6, CFG_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
+	SET_LAW_ENTRY(7, CFG_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1),
+#endif
+	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+	SET_LAW_ENTRY(8, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+#ifdef CFG_RIO_MEM_PHYS
+	SET_LAW_ENTRY(9, CFG_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c
new file mode 100644
index 0000000..b21f71b
--- /dev/null
+++ b/board/freescale/mpc8548cds/tlb.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/*
+	 * TLB 0:	16M	Non-cacheable, guarded
+	 * 0xff000000	16M	FLASH
+	 * Out of reset this entry is only 4K.
+	 */
+	SET_TLB_ENTRY(1, CFG_BOOT_BLOCK, CFG_BOOT_BLOCK,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_16M, 1),
+
+	/*
+	 * TLB 1:	1G	Non-cacheable, guarded
+	 * 0x80000000	1G	PCI1/PCIE  8,9,a,b
+	 */
+	SET_TLB_ENTRY(1, CFG_PCI_PHYS, CFG_PCI_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_1G, 1),
+
+#ifdef CFG_RIO_MEM_PHYS
+	/*
+	 * TLB 2:	256M	Non-cacheable, guarded
+	 */
+	SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 3:	256M	Non-cacheable, guarded
+	 */
+	SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_256M, 1),
+#endif
+	/*
+	 * TLB 5:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe200_0000	1M	PCI1 IO
+	 * 0xe210_0000	1M	PCI2 IO
+	 * 0xe300_0000	1M	PCIe IO
+	 */
+	SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 6:	64M	Cacheable, non-guarded
+	 * 0xf000_0000	64M	LBC SDRAM
+	 */
+	SET_TLB_ENTRY(1, CFG_LBC_CACHE_BASE, CFG_LBC_CACHE_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 6, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 7:	64M	Non-cacheable, guarded
+	 * 0xf8000000	64M	CADMUS registers, relocated L2SRAM
+	 */
+	SET_TLB_ENTRY(1, CFG_LBC_NONCACHE_BASE, CFG_LBC_NONCACHE_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 7, BOOKE_PAGESZ_64M, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/mpc8548cds/u-boot.lds b/board/freescale/mpc8548cds/u-boot.lds
index acf25e3..d701096 100644
--- a/board/freescale/mpc8548cds/u-boot.lds
+++ b/board/freescale/mpc8548cds/u-boot.lds
@@ -34,7 +34,6 @@ SECTIONS
   .bootpg 0xFFFFF000 :
   {
     cpu/mpc85xx/start.o	(.bootpg)
-    board/freescale/mpc8548cds/init.o (.bootpg)
   } = 0xffff
 
   /* Read-only sections, merged into text segment: */
@@ -64,7 +63,6 @@ SECTIONS
   .text      :
   {
     cpu/mpc85xx/start.o	(.text)
-    board/freescale/mpc8548cds/init.o (.text)
     cpu/mpc85xx/traps.o (.text)
     cpu/mpc85xx/interrupts.o (.text)
     cpu/mpc85xx/cpu_init.o (.text)
diff --git a/board/freescale/mpc8555cds/Makefile b/board/freescale/mpc8555cds/Makefile
index 7f53098..d1a585a 100644
--- a/board/freescale/mpc8555cds/Makefile
+++ b/board/freescale/mpc8555cds/Makefile
@@ -29,14 +29,12 @@ endif
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o \
+COBJS	:= $(BOARD).o law.o tlb.o \
 	   ../common/cadmus.o \
 	   ../common/eeprom.o \
 	   ../common/ft_board.o \
 	   ../common/via.o
 
-SOBJS	:= init.o
-
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
diff --git a/board/freescale/mpc8555cds/init.S b/board/freescale/mpc8555cds/init.S
deleted file mode 100644
index 8c8c087c..0000000
--- a/board/freescale/mpc8555cds/init.S
+++ /dev/null
@@ -1,243 +0,0 @@
-/*
- * Copyright 2004 Freescale Semiconductor.
- * Copyright 2002,2003, Motorola Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-#include <asm/cache.h>
-#include <asm/mmu.h>
-#include <config.h>
-#include <mpc85xx.h>
-
-
-/*
- * TLB0 and TLB1 Entries
- *
- * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
- * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
- * these TLB entries are established.
- *
- * The TLB entries for DDR are dynamically setup in spd_sdram()
- * and use TLB1 Entries 8 through 15 as needed according to the
- * size of DDR memory.
- *
- * MAS0: tlbsel, esel, nv
- * MAS1: valid, iprot, tid, ts, tsize
- * MAS2: epn, x0, x1, w, i, m, g, e
- * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
- */
-
-#define	entry_start \
-	mflr	r1 	;	\
-	bl	0f 	;
-
-#define	entry_end \
-0:	mflr	r0	;	\
-	mtlr	r1	;	\
-	blr		;
-
-
-	.section	.bootpg, "ax"
-	.globl	tlb1_entry
-tlb1_entry:
-	entry_start
-
-	/*
-	 * Number of TLB0 and TLB1 entries in the following table
-	 */
-	.long 13
-
-#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
-	/*
-	 * TLB0		4K	Non-cacheable, guarded
-	 * 0xff700000	4K	Initial CCSRBAR mapping
-	 *
-	 * This ends up at a TLB0 Index==0 entry, and must not collide
-	 * with other TLB0 Entries.
-	 */
-	.long FSL_BOOKE_MAS0(0, 0, 0)
-	.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
-	.long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-#else
-#error("Update the number of table entries in tlb1_entry")
-#endif
-
-	/*
-	 * TLB0		16K	Cacheable, non-guarded
-	 * 0xd001_0000	16K	Temporary Global data for initialization
-	 *
-	 * Use four 4K TLB0 entries.  These entries must be cacheable
-	 * as they provide the bootstrap memory before the memory
-	 * controler and real memory have been configured.
-	 *
-	 * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
-	 * and must not collide with other TLB0 entries.
-	 */
-	.long FSL_BOOKE_MAS0(0, 0, 0)
-	.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
-	.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)
-	.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	.long FSL_BOOKE_MAS0(0, 0, 0)
-	.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
-	.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0)
-	.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	.long FSL_BOOKE_MAS0(0, 0, 0)
-	.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
-	.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0)
-	.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	.long FSL_BOOKE_MAS0(0, 0, 0)
-	.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
-	.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0)
-	.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-
-	/*
-	 * TLB 0:	16M	Non-cacheable, guarded
-	 * 0xff000000	16M	FLASH
-	 * Out of reset this entry is only 4K.
-	 */
-	.long FSL_BOOKE_MAS0(1, 0, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
-	.long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/*
-	 * TLB 1:	256M	Non-cacheable, guarded
-	 * 0x80000000	256M	PCI1 MEM First half
-	 */
-	.long FSL_BOOKE_MAS0(1, 1, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-	.long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/*
-	 * TLB 2:	256M	Non-cacheable, guarded
-	 * 0x90000000	256M	PCI1 MEM Second half
-	 */
-	.long FSL_BOOKE_MAS0(1, 2, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-	.long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/*
-	 * TLB 3:	256M	Non-cacheable, guarded
-	 * 0xa0000000	256M	PCI2 MEM First half
-	 */
-	.long FSL_BOOKE_MAS0(1, 3, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-	.long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/*
-	 * TLB 4:	256M	Non-cacheable, guarded
-	 * 0xb0000000	256M	PCI2 MEM Second half
-	 */
-	.long FSL_BOOKE_MAS0(1, 4, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-	.long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/*
-	 * TLB 5:	64M	Non-cacheable, guarded
-	 * 0xe000_0000	1M	CCSRBAR
-	 * 0xe200_0000	16M	PCI1 IO
-	 * 0xe300_0000	16M	PCI2 IO
-	 */
-	.long FSL_BOOKE_MAS0(1, 5, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-	.long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/*
-	 * TLB 6:	64M	Cacheable, non-guarded
-	 * 0xf000_0000	64M	LBC SDRAM
-	 */
-	.long FSL_BOOKE_MAS0(1, 6, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-	.long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0)
-	.long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/*
-	 * TLB 7:	1M	Non-cacheable, guarded
-	 * 0xf8000000	1M	CADMUS registers
-	 */
-	.long FSL_BOOKE_MAS0(1, 7, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)
-	.long FSL_BOOKE_MAS2(CADMUS_BASE_ADDR, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CADMUS_BASE_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	entry_end
-
-/*
- * LAW(Local Access Window) configuration:
- *
- * 0x0000_0000     0x7fff_ffff     DDR                     2G
- * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
- * 0xa000_0000     0xbfff_ffff     PCI2 MEM                512M
- * 0xe000_0000     0xe000_ffff     CCSR                    1M
- * 0xe200_0000     0xe20f_ffff     PCI1 IO                 1M
- * 0xe210_0000     0xe21f_ffff     PCI2 IO                 1M
- * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
- * 0xf800_0000     0xf80f_ffff     NVRAM/CADMUS (*)        1M
- * 0xff00_0000     0xff7f_ffff     FLASH (2nd bank)        8M
- * 0xff80_0000     0xffff_ffff     FLASH (boot bank)       8M
- *
- * Notes:
- *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- *    If flash is 8M at default position (last 8M), no LAW needed.
- *
- * The defines below are 1-off of the actual LAWAR0 usage.
- * So LAWAR3 define uses the LAWAR4 register in the ECM.
- */
-
-#define LAWBAR0 0
-#define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
-
-#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
-#define LAWAR1 	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
-#define LAWAR2 	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
-#define LAWAR3 	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
-
-#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff)
-#define LAWAR4 	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M))
-
-/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
-#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
-#define LAWAR5 	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
-
-	.section .bootpg, "ax"
-	.globl	law_entry
-
-law_entry:
-	entry_start
-	.long 6
-	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
-	.long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5
-	entry_end
diff --git a/board/freescale/mpc8555cds/law.c b/board/freescale/mpc8555cds/law.c
new file mode 100644
index 0000000..0ac223c
--- /dev/null
+++ b/board/freescale/mpc8555cds/law.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x7fff_ffff     DDR                     2G
+ * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
+ * 0xa000_0000     0xbfff_ffff     PCI2 MEM                512M
+ * 0xe000_0000     0xe000_ffff     CCSR                    1M
+ * 0xe200_0000     0xe20f_ffff     PCI1 IO                 1M
+ * 0xe210_0000     0xe21f_ffff     PCI2 IO                 1M
+ * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
+ * 0xf800_0000     0xf80f_ffff     NVRAM/CADMUS (*)        1M
+ * 0xff00_0000     0xff7f_ffff     FLASH (2nd bank)        8M
+ * 0xff80_0000     0xffff_ffff     FLASH (boot bank)       8M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+	SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+	SET_LAW_ENTRY(3, CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+	SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
+	SET_LAW_ENTRY(5, CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
+	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+	SET_LAW_ENTRY(6, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8555cds/tlb.c b/board/freescale/mpc8555cds/tlb.c
new file mode 100644
index 0000000..92f759b
--- /dev/null
+++ b/board/freescale/mpc8555cds/tlb.c
@@ -0,0 +1,112 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/*
+	 * TLB 0:	16M	Non-cacheable, guarded
+	 * 0xff000000	16M	FLASH
+	 * Out of reset this entry is only 4K.
+	 */
+	SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_16M, 1),
+
+	/*
+	 * TLB 1:	256M	Non-cacheable, guarded
+	 * 0x80000000	256M	PCI1 MEM First half
+	 */
+	SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 2:	256M	Non-cacheable, guarded
+	 * 0x90000000	256M	PCI1 MEM Second half
+	 */
+	SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 3:	256M	Non-cacheable, guarded
+	 * 0xa0000000	256M	PCI2 MEM First half
+	 */
+	SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS, CFG_PCI2_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 4:	256M	Non-cacheable, guarded
+	 * 0xb0000000	256M	PCI2 MEM Second half
+	 */
+	SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS + 0x10000000, CFG_PCI2_MEM_PHYS + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 5:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe200_0000	16M	PCI1 IO
+	 * 0xe300_0000	16M	PCI2 IO
+	 */
+	SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 6:	64M	Cacheable, non-guarded
+	 * 0xf000_0000	64M	LBC SDRAM
+	 */
+	SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 6, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 7:	1M	Non-cacheable, guarded
+	 * 0xf8000000	1M	CADMUS registers
+	 */
+	SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 7, BOOKE_PAGESZ_1M, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/mpc8555cds/u-boot.lds b/board/freescale/mpc8555cds/u-boot.lds
index e9fa51e..1cbadf2 100644
--- a/board/freescale/mpc8555cds/u-boot.lds
+++ b/board/freescale/mpc8555cds/u-boot.lds
@@ -34,7 +34,6 @@ SECTIONS
   .bootpg 0xFFFFF000 :
   {
     cpu/mpc85xx/start.o	(.bootpg)
-    board/freescale/mpc8555cds/init.o (.bootpg)
   } = 0xffff
 
   /* Read-only sections, merged into text segment: */
@@ -64,7 +63,6 @@ SECTIONS
   .text      :
   {
     cpu/mpc85xx/start.o	(.text)
-    board/freescale/mpc8555cds/init.o (.text)
     cpu/mpc85xx/traps.o (.text)
     cpu/mpc85xx/interrupts.o (.text)
     cpu/mpc85xx/cpu_init.o (.text)
diff --git a/board/freescale/mpc8560ads/Makefile b/board/freescale/mpc8560ads/Makefile
index 2913650..be24388 100644
--- a/board/freescale/mpc8560ads/Makefile
+++ b/board/freescale/mpc8560ads/Makefile
@@ -25,9 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o
-SOBJS	:= init.o
-#SOBJS	:=
+COBJS	:= $(BOARD).o law.o tlb.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/freescale/mpc8560ads/init.S b/board/freescale/mpc8560ads/init.S
deleted file mode 100644
index 37fd0c6..0000000
--- a/board/freescale/mpc8560ads/init.S
+++ /dev/null
@@ -1,266 +0,0 @@
-/*
- * Copyright 2004 Freescale Semiconductor.
- * Copyright (C) 2002,2003, Motorola Inc.
- * Xianghua Xiao <X.Xiao@motorola.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-#include <asm/cache.h>
-#include <asm/mmu.h>
-#include <config.h>
-#include <mpc85xx.h>
-
-
-/*
- * TLB0 and TLB1 Entries
- *
- * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
- * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
- * these TLB entries are established.
- *
- * The TLB entries for DDR are dynamically setup in spd_sdram()
- * and use TLB1 Entries 8 through 15 as needed according to the
- * size of DDR memory.
- *
- * MAS0: tlbsel, esel, nv
- * MAS1: valid, iprot, tid, ts, tsize
- * MAS2: epn, x0, x1, w, i, m, g, e
- * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
- */
-
-#define	entry_start \
-	mflr	r1 	;	\
-	bl	0f 	;
-
-#define	entry_end \
-0:	mflr	r0	;	\
-	mtlr	r1	;	\
-	blr		;
-
-
-	.section	.bootpg, "ax"
-	.globl	tlb1_entry
-tlb1_entry:
-	entry_start
-
-	/*
-	 * Number of TLB0 and TLB1 entries in the following table
-	 */
-	.long 13
-
-#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
-	/*
-	 * TLB0		4K	Non-cacheable, guarded
-	 * 0xff700000	4K	Initial CCSRBAR mapping
-	 *
-	 * This ends up at a TLB0 Index==0 entry, and must not collide
-	 * with other TLB0 Entries.
-	 */
-	.long FSL_BOOKE_MAS0(0, 0, 0)
-	.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
-	.long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-#else
-#error("Update the number of table entries in tlb1_entry")
-#endif
-
-	/*
-	 * TLB0		16K	Cacheable, non-guarded
-	 * 0xd001_0000	16K	Temporary Global data for initialization
-	 *
-	 * Use four 4K TLB0 entries.  These entries must be cacheable
-	 * as they provide the bootstrap memory before the memory
-	 * controler and real memory have been configured.
-	 *
-	 * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
-	 * and must not collide with other TLB0 entries.
-	 */
-	.long FSL_BOOKE_MAS0(0, 0, 0)
-	.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
-	.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)
-	.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	.long FSL_BOOKE_MAS0(0, 0, 0)
-	.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
-	.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0)
-	.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	.long FSL_BOOKE_MAS0(0, 0, 0)
-	.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
-	.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0)
-	.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	.long FSL_BOOKE_MAS0(0, 0, 0)
-	.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
-	.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0)
-	.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-
-	/*
-	 * TLB 0:	16M	Non-cacheable, guarded
-	 * 0xff000000	16M	FLASH
-	 * Out of reset this entry is only 4K.
-	 */
-	.long FSL_BOOKE_MAS0(1, 0, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
-	.long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/*
-	 * TLB 1:	256M	Non-cacheable, guarded
-	 * 0x80000000	256M	PCI1 MEM First half
-	 */
-	.long FSL_BOOKE_MAS0(1, 1, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-	.long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/*
-	 * TLB 2:	256M	Non-cacheable, guarded
-	 * 0x90000000	256M	PCI1 MEM Second half
-	 */
-	.long FSL_BOOKE_MAS0(1, 2, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-	.long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/*
-	 * TLB 3:	256M	Non-cacheable, guarded
-	 * 0xc0000000	256M	Rapid IO MEM First half
-	 */
-	.long FSL_BOOKE_MAS0(1, 3, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-	.long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/*
-	 * TLB 4:	256M	Non-cacheable, guarded
-	 * 0xd0000000	256M	Rapid IO MEM Second half
-	 */
-	.long FSL_BOOKE_MAS0(1, 4, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-	.long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/*
-	 * TLB 5:	64M	Non-cacheable, guarded
-	 * 0xe000_0000	1M	CCSRBAR
-	 * 0xe200_0000	16M	PCI1 IO
-	 */
-	.long FSL_BOOKE_MAS0(1, 5, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-	.long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/*
-	 * TLB 6:	64M	Cacheable, non-guarded
-	 * 0xf000_0000	64M	LBC SDRAM
-	 */
-	.long FSL_BOOKE_MAS0(1, 6, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-	.long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0)
-	.long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/*
-	 * TLB 7:	16K	Non-cacheable, guarded
-	 * 0xf8000000	16K	BCSR registers
-	 */
-	.long FSL_BOOKE_MAS0(1, 7, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K)
-	.long FSL_BOOKE_MAS2(CFG_BCSR, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_BCSR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-#if !defined(CONFIG_SPD_EEPROM)
-	/*
-	 * TLB 8, 9:	128M	DDR
-	 * 0x00000000	64M	DDR System memory
-	 * 0x04000000	64M	DDR System memory
-	 * Without SPD EEPROM configured DDR, this must be setup manually.
-	 * Make sure the TLB count at the top of this table is correct.
-	 * Likely it needs to be increased by two for these entries.
-	 */
-#error("Update the number of table entries in tlb1_entry")
-	.long FSL_BOOKE_MAS0(1, 8, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-	.long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE, 0)
-	.long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	.long FSL_BOOKE_MAS0(1, 9, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-	.long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE + 0x4000000, 0)
-	.long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE + 0x4000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-#endif
-
-	entry_end
-
-/*
- * LAW(Local Access Window) configuration:
- *
- * 0x0000_0000     0x7fff_ffff     DDR                     2G
- * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
- * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
- * 0xe000_0000     0xe000_ffff     CCSR                    1M
- * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
- * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
- * 0xf800_0000     0xf80f_ffff     BCSR                    1M
- * 0xff00_0000     0xffff_ffff     FLASH (boot bank)       16M
- *
- * Notes:
- *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- *    If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-#if !defined(CONFIG_SPD_EEPROM)
-#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
-#define LAWAR0	(LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
-#else
-#define LAWBAR0 0
-#define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
-#endif
-
-#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
-#define LAWAR1	(LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-/*
- * This is not so much the SDRAM map as it is the whole localbus map.
- */
-#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
-#define LAWAR2	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
-
-#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
-#define LAWAR3	(LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_1M))
-
-/*
- * Rapid IO at 0xc000_0000 for 512 M
- */
-#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
-#define LAWAR4	(LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-
-	.section .bootpg, "ax"
-	.globl	law_entry
-law_entry:
-	entry_start
-	.long 0x05
-	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
-	.long LAWBAR4,LAWAR4
-	entry_end
diff --git a/board/freescale/mpc8560ads/law.c b/board/freescale/mpc8560ads/law.c
new file mode 100644
index 0000000..785576a
--- /dev/null
+++ b/board/freescale/mpc8560ads/law.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x7fff_ffff     DDR                     2G
+ * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
+ * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
+ * 0xe000_0000     0xe000_ffff     CCSR                    1M
+ * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
+ * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
+ * 0xf800_0000     0xf80f_ffff     BCSR                    1M
+ * 0xff00_0000     0xffff_ffff     FLASH (boot bank)       16M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+#ifndef CONFIG_SPD_EEPROM
+	SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
+#endif
+	SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+	/* This is not so much the SDRAM map as it is the whole localbus map. */
+	SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
+	SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8560ads/tlb.c b/board/freescale/mpc8560ads/tlb.c
new file mode 100644
index 0000000..3eaff01
--- /dev/null
+++ b/board/freescale/mpc8560ads/tlb.c
@@ -0,0 +1,130 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/*
+	 * TLB 0:	16M	Non-cacheable, guarded
+	 * 0xff000000	16M	FLASH
+	 * Out of reset this entry is only 4K.
+	 */
+	SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_16M, 1),
+
+	/*
+	 * TLB 1:	256M	Non-cacheable, guarded
+	 * 0x80000000	256M	PCI1 MEM First half
+	 */
+	SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 2:	256M	Non-cacheable, guarded
+	 * 0x90000000	256M	PCI1 MEM Second half
+	 */
+	SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 3:	256M	Non-cacheable, guarded
+	 * 0xc0000000	256M	Rapid IO MEM First half
+	 */
+	SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 4:	256M	Non-cacheable, guarded
+	 * 0xd0000000	256M	Rapid IO MEM Second half
+	 */
+	SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 5:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe200_0000	16M	PCI1 IO
+	 */
+	SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 6:	64M	Cacheable, non-guarded
+	 * 0xf000_0000	64M	LBC SDRAM
+	 */
+	SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 6, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 7:	16K	Non-cacheable, guarded
+	 * 0xf8000000	16K	BCSR registers
+	 */
+	SET_TLB_ENTRY(1, CFG_BCSR, CFG_BCSR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 7, BOOKE_PAGESZ_16K, 1),
+
+#if !defined(CONFIG_SPD_EEPROM)
+	/*
+	 * TLB 8, 9:	128M	DDR
+	 * 0x00000000	64M	DDR System memory
+	 * 0x04000000	64M	DDR System memory
+	 * Without SPD EEPROM configured DDR, this must be setup manually.
+	 * Make sure the TLB count at the top of this table is correct.
+	 * Likely it needs to be increased by two for these entries.
+	 */
+#error("Update the number of table entries in tlb1_entry")
+	SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 8, BOOKE_PAGESZ_64M, 1),
+
+	SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x4000000, CFG_DDR_SDRAM_BASE + 0x4000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 9, BOOKE_PAGESZ_64M, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/mpc8560ads/u-boot.lds b/board/freescale/mpc8560ads/u-boot.lds
index 96af2b1..e2474e5 100644
--- a/board/freescale/mpc8560ads/u-boot.lds
+++ b/board/freescale/mpc8560ads/u-boot.lds
@@ -35,7 +35,6 @@ SECTIONS
   .bootpg 0xFFFFF000 :
   {
     cpu/mpc85xx/start.o	(.bootpg)
-    board/freescale/mpc8560ads/init.o (.bootpg)
   } = 0xffff
 
   /* Read-only sections, merged into text segment: */
@@ -65,7 +64,6 @@ SECTIONS
   .text      :
   {
     cpu/mpc85xx/start.o	(.text)
-    board/freescale/mpc8560ads/init.o (.text)
     cpu/mpc85xx/commproc.o (.text)
     cpu/mpc85xx/traps.o (.text)
     cpu/mpc85xx/interrupts.o (.text)
diff --git a/board/freescale/mpc8568mds/Makefile b/board/freescale/mpc8568mds/Makefile
index 643fbc0..d9f20f9 100644
--- a/board/freescale/mpc8568mds/Makefile
+++ b/board/freescale/mpc8568mds/Makefile
@@ -29,9 +29,7 @@ endif
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o bcsr.o
-
-SOBJS	:= init.o
+COBJS	:= $(BOARD).o bcsr.o law.o tlb.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/freescale/mpc8568mds/init.S b/board/freescale/mpc8568mds/init.S
deleted file mode 100644
index 2748c51..0000000
--- a/board/freescale/mpc8568mds/init.S
+++ /dev/null
@@ -1,236 +0,0 @@
-/*
- * Copyright 2004-2007 Freescale Semiconductor.
- * Copyright 2002,2003, Motorola Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-#include <asm/cache.h>
-#include <asm/mmu.h>
-#include <config.h>
-#include <mpc85xx.h>
-
-/*
- * TLB0 and TLB1 Entries
- *
- * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
- * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
- * these TLB entries are established.
- *
- * The TLB entries for DDR are dynamically setup in spd_sdram()
- * and use TLB1 Entries 8 through 15 as needed according to the
- * size of DDR memory.
- *
- * MAS0: tlbsel, esel, nv
- * MAS1: valid, iprot, tid, ts, tsize
- * MAS2: epn, x0, x1, w, i, m, g, e
- * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
- */
-#define	entry_start \
-	mflr	r1	;	\
-	bl	0f	;
-
-#define	entry_end \
-0:	mflr	r0	;	\
-	mtlr	r1	;	\
-	blr		;
-
-
-	.section	.bootpg, "ax"
-	.globl	tlb1_entry
-tlb1_entry:
-	entry_start
-
-	/*
-	 * Number of TLB0 and TLB1 entries in the following table
-	 */
-	.long (2f-1f)/16
-
-1:
-#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
-	/*
-	 * TLB0		4K	Non-cacheable, guarded
-	 * 0xff700000	4K	Initial CCSRBAR mapping
-	 *
-	 * This ends up at a TLB0 Index==0 entry, and must not collide
-	 * with other TLB0 Entries.
-	 */
-	.long FSL_BOOKE_MAS0(0, 0, 0)
-	.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
-	.long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-#else
-#error("Update the number of table entries in tlb1_entry")
-#endif
-
-	/*
-	 * TLB0		16K	Cacheable, non-guarded
-	 * 0xd001_0000	16K	Temporary Global data for initialization
-	 *
-	 * Use four 4K TLB0 entries.  These entries must be cacheable
-	 * as they provide the bootstrap memory before the memory
-	 * controler and real memory have been configured.
-	 *
-	 * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
-	 * and must not collide with other TLB0 entries.
-	 */
-
-	.long FSL_BOOKE_MAS0(0, 0, 0)
-	.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
-	.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)
-	.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	.long FSL_BOOKE_MAS0(0, 0, 0)
-	.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
-	.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0)
-	.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	.long FSL_BOOKE_MAS0(0, 0, 0)
-	.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
-	.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0)
-	.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	.long FSL_BOOKE_MAS0(0, 0, 0)
-	.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
-	.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0)
-	.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/* TLB 1 Initializations */
-	/*
-	 * TLBe 0:	16M	Non-cacheable, guarded
-	 * 0xff000000	16M	FLASH (upper half)
-	 * Out of reset this entry is only 4K.
-	 */
-	.long FSL_BOOKE_MAS0(1, 0, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
-	.long FSL_BOOKE_MAS2(CFG_FLASH_BASE + 0x1000000, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_FLASH_BASE + 0x1000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/*
-	 * TLBe 1:	16M	Non-cacheable, guarded
-	 * 0xfe000000	16M	FLASH (lower half)
-	 */
-	.long FSL_BOOKE_MAS0(1, 1, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
-	.long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/*
-	 * TLBe 2:	1G	Non-cacheable, guarded
-	 * 0x80000000	512M	PCI1 MEM
-	 * 0xa0000000 	512M	PCIe MEM
-	 */
-	.long FSL_BOOKE_MAS0(1, 2, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
-	.long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/*
-	 * TLBe 3:	64M	Non-cacheable, guarded
-	 * 0xe000_0000	1M	CCSRBAR
-	 * 0xe200_0000	8M	PCI1 IO
-	 * 0xe280_0000	8M	PCIe IO
-	 */
-	.long FSL_BOOKE_MAS0(1, 3, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-	.long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/*
-	 * TLBe 4:	64M	Cacheable, non-guarded
-	 * 0xf000_0000	64M	LBC SDRAM
-	 */
-	.long FSL_BOOKE_MAS0(1, 4, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-	.long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0)
-	.long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-	/*
-	 * TLBe 5:	256K	Non-cacheable, guarded
-	 * 0xf8000000	32K BCSR
-	 * 0xf8008000	32K PIB (CS4)
-	 * 0xf8010000	32K PIB (CS5)
-	 */
-	.long FSL_BOOKE_MAS0(1, 5, 0)
-	.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)
-	.long FSL_BOOKE_MAS2(CFG_BCSR_BASE, (MAS2_I|MAS2_G))
-	.long FSL_BOOKE_MAS3(CFG_BCSR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
-
-2:
-	entry_end
-
-/*
- * LAW(Local Access Window) configuration:
- *
- *0)   0x0000_0000   0x7fff_ffff     DDR                     2G
- *1)   0x8000_0000   0x9fff_ffff     PCI1 MEM                512MB
- *2)   0xa000_0000   0xbfff_ffff     PCIe MEM                512MB
- *-)   0xe000_0000   0xe00f_ffff     CCSR                    1M
- *3)   0xe200_0000   0xe27f_ffff     PCI1 I/O                8M
- *4)   0xe280_0000   0xe2ff_ffff     PCIe I/O                8M
- *5)   0xc000_0000   0xdfff_ffff     SRIO                    512MB
- *6.a) 0xf000_0000   0xf3ff_ffff     SDRAM                   64MB
- *6.b) 0xf800_0000   0xf800_7fff     BCSR                    32KB
- *6.c) 0xf800_8000   0xf800_ffff     PIB (CS4)		     32KB
- *6.d) 0xf801_0000   0xf801_7fff     PIB (CS5)		     32KB
- *6.e) 0xfe00_0000   0xffff_ffff     Flash                   32MB
- *
- *Notes:
- *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- *    If flash is 8M at default position (last 8M), no LAW needed.
- *
- * The defines below are 1-off of the actual LAWAR0 usage.
- * So LAWAR3 define uses the LAWAR4 register in the ECM.
- */
-
-#define LAWBAR0 0
-#define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
-
-#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
-#define LAWAR1	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-#define LAWBAR2 ((CFG_PCIE1_MEM_BASE>>12) & 0xfffff)
-#define LAWAR2	(LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
-#define LAWAR3	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
-
-#define LAWBAR4 ((CFG_PCIE1_IO_PHYS>>12) & 0xfffff)
-#define LAWAR4  (LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
-
-#define LAWBAR5 ((CFG_SRIO_MEM_BASE>>12) & 0xfffff)
-#define LAWAR5	(LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-/* LBC window - maps 256M.  That's SDRAM, BCSR, PIBs, and Flash */
-#define LAWBAR6 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
-#define LAWAR6	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
-
-	.section .bootpg, "ax"
-	.globl	law_entry
-
-law_entry:
-	entry_start
-	.long (4f-3f)/8
-3:
-	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
-	.long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5,LAWBAR6,LAWAR6
-4:
-	entry_end
diff --git a/board/freescale/mpc8568mds/law.c b/board/freescale/mpc8568mds/law.c
new file mode 100644
index 0000000..5e96ea7
--- /dev/null
+++ b/board/freescale/mpc8568mds/law.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ *0)   0x0000_0000   0x7fff_ffff     DDR                     2G
+ *1)   0x8000_0000   0x9fff_ffff     PCI1 MEM                512MB
+ *2)   0xa000_0000   0xbfff_ffff     PCIe MEM                512MB
+ *-)   0xe000_0000   0xe00f_ffff     CCSR                    1M
+ *3)   0xe200_0000   0xe27f_ffff     PCI1 I/O                8M
+ *4)   0xe280_0000   0xe2ff_ffff     PCIe I/O                8M
+ *5)   0xc000_0000   0xdfff_ffff     SRIO                    512MB
+ *6.a) 0xf000_0000   0xf3ff_ffff     SDRAM                   64MB
+ *6.b) 0xf800_0000   0xf800_7fff     BCSR                    32KB
+ *6.c) 0xf800_8000   0xf800_ffff     PIB (CS4)		     32KB
+ *6.d) 0xf801_0000   0xf801_7fff     PIB (CS5)		     32KB
+ *6.e) 0xfe00_0000   0xffff_ffff     Flash                   32MB
+ *
+ *Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ */
+
+struct law_entry law_table[] = {
+	SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+	SET_LAW_ENTRY(3, CFG_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
+	SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI),
+	SET_LAW_ENTRY(5, CFG_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
+	SET_LAW_ENTRY(6, CFG_SRIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
+	/* LBC window - maps 256M.  That's SDRAM, BCSR, PIBs, and Flash */
+	SET_LAW_ENTRY(7, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8568mds/tlb.c b/board/freescale/mpc8568mds/tlb.c
new file mode 100644
index 0000000..225fc94
--- /dev/null
+++ b/board/freescale/mpc8568mds/tlb.c
@@ -0,0 +1,100 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 Initializations */
+	/*
+	 * TLBe 0:	16M	Non-cacheable, guarded
+	 * 0xff000000	16M	FLASH (upper half)
+	 * Out of reset this entry is only 4K.
+	 */
+	SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x1000000, CFG_FLASH_BASE + 0x1000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_16M, 1),
+
+	/*
+	 * TLBe 1:	16M	Non-cacheable, guarded
+	 * 0xfe000000	16M	FLASH (lower half)
+	 */
+	SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_16M, 1),
+
+	/*
+	 * TLBe 2:	1G	Non-cacheable, guarded
+	 * 0x80000000	512M	PCI1 MEM
+	 * 0xa0000000 	512M	PCIe MEM
+	 */
+	SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_1G, 1),
+
+	/*
+	 * TLBe 3:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe200_0000	8M	PCI1 IO
+	 * 0xe280_0000	8M	PCIe IO
+	 */
+	SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLBe 4:	64M	Cacheable, non-guarded
+	 * 0xf000_0000	64M	LBC SDRAM
+	 */
+	SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 4, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLBe 5:	256K	Non-cacheable, guarded
+	 * 0xf8000000	32K BCSR
+	 * 0xf8008000	32K PIB (CS4)
+	 * 0xf8010000	32K PIB (CS5)
+	 */
+	SET_TLB_ENTRY(1, CFG_BCSR_BASE, CFG_BCSR_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_256K, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/mpc8568mds/u-boot.lds b/board/freescale/mpc8568mds/u-boot.lds
index 7917409..6b30f15 100644
--- a/board/freescale/mpc8568mds/u-boot.lds
+++ b/board/freescale/mpc8568mds/u-boot.lds
@@ -37,7 +37,6 @@ SECTIONS
   .bootpg 0xFFFFF000:
   {
 	cpu/mpc85xx/start.o	(.bootpg)
-	board/freescale/mpc8568mds/init.o (.bootpg)
   } = 0xffff
 
   /* Read-only sections, merged into text segment: */
@@ -67,7 +66,6 @@ SECTIONS
   .text      :
   {
     cpu/mpc85xx/start.o	(.text)
-    board/freescale/mpc8568mds/init.o (.text)
     cpu/mpc85xx/traps.o (.text)
     cpu/mpc85xx/interrupts.o (.text)
     cpu/mpc85xx/cpu_init.o (.text)