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| author | Shengzhou Liu <Shengzhou.Liu@nxp.com> | 2016-05-31 15:39:06 +0800 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-06-03 22:12:54 -0700 |
| commit | 534992827756c3a1ab49823ca487702a954fe433 (patch) | |
| tree | f00bfe6d3ebd02c921963584bb491fa63c7aa151 /board/freescale/t4qds | |
| parent | ed4708aaeaf74008d199866bfbd450d91439a9cf (diff) | |
| download | u-boot-534992827756c3a1ab49823ca487702a954fe433.zip u-boot-534992827756c3a1ab49823ca487702a954fe433.tar.gz u-boot-534992827756c3a1ab49823ca487702a954fe433.tar.bz2 | |
board/freescale: Use unified setup_ddr_tlbs for spl boot and non-spl boot
We should use unified setup_ddr_tlbs() for spl boot and non-spl boot
to make sure 'M' bit is set for DDR TLB to maintain cache coherence.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'board/freescale/t4qds')
| -rw-r--r-- | board/freescale/t4qds/ddr.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c index 62d58c5..d533924 100644 --- a/board/freescale/t4qds/ddr.c +++ b/board/freescale/t4qds/ddr.c @@ -117,13 +117,12 @@ phys_size_t initdram(int board_type) #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) dram_size = fsl_ddr_sdram(); - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - #else /* DDR has been initialised by first stage boot loader */ dram_size = fsl_ddr_sdram_size(); #endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + return dram_size; } |