diff options
author | Stefan Roese <sr@denx.de> | 2009-09-09 16:25:29 +0200 |
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committer | Stefan Roese <sr@denx.de> | 2009-09-11 10:35:58 +0200 |
commit | d1c3b27525b664e8c4db6bb173eed51bfc8220de (patch) | |
tree | c00f3d0bcfbd5fcc1954cc9cefdbc4c9c41f41ea /board/esd/cpci2dp/cpci2dp.c | |
parent | e7963772eb78a6aa1fa65063d64eab3a8626daac (diff) | |
download | u-boot-d1c3b27525b664e8c4db6bb173eed51bfc8220de.zip u-boot-d1c3b27525b664e8c4db6bb173eed51bfc8220de.tar.gz u-boot-d1c3b27525b664e8c4db6bb173eed51bfc8220de.tar.bz2 |
ppc4xx: Big cleanup of PPC4xx defines
This patch cleans up multiple issues of the 4xx register (mostly
DCR, SDR, CPR, etc) definitions:
- Change lower case defines to upper case (plb4_acr -> PLB4_ACR)
- Change the defines to better match the names from the
user's manuals (e.g. cprpllc -> CPR0_PLLC)
- Removal of some unused defines
Please test this patch intensive on your PPC4xx platform. Even though
I tried not to break anything and tested successfully on multiple
4xx AMCC platforms, testing on custom platforms is recommended.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/esd/cpci2dp/cpci2dp.c')
-rw-r--r-- | board/esd/cpci2dp/cpci2dp.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/board/esd/cpci2dp/cpci2dp.c b/board/esd/cpci2dp/cpci2dp.c index cd57ed4..00c7024 100644 --- a/board/esd/cpci2dp/cpci2dp.c +++ b/board/esd/cpci2dp/cpci2dp.c @@ -31,13 +31,13 @@ DECLARE_GLOBAL_DATA_PTR; int board_early_init_f (void) { - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; /* * Setup GPIO pins */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | ((CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED | CONFIG_SYS_SELF_RST | CONFIG_SYS_INTA_FAKE) << 5)); @@ -72,7 +72,7 @@ int board_early_init_f (void) int misc_init_r (void) { - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; /* adjust flash start and offset */ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; @@ -81,8 +81,8 @@ int misc_init_r (void) /* * Select cts (and not dsr) on uart1 */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x00001000); + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000); return (0); } |