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| author | Stefan Roese <sr@denx.de> | 2020-10-28 15:09:59 +0100 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2020-11-30 18:31:56 +0100 |
| commit | de24bc7e0e3528f3d3c4731ab053a3e8d621ab7a (patch) | |
| tree | 2a8c1b4070bb288b99ce830bf6275c4b5d55d2f2 /arch | |
| parent | a7ab4b71d563b6e0b65f911a8bf7d6950625982e (diff) | |
| download | u-boot-de24bc7e0e3528f3d3c4731ab053a3e8d621ab7a.zip u-boot-de24bc7e0e3528f3d3c4731ab053a3e8d621ab7a.tar.gz u-boot-de24bc7e0e3528f3d3c4731ab053a3e8d621ab7a.tar.bz2 | |
mips: start.S: Add Octeon boot header compatibility
Octeon has a specific boot header, when booted via SPI NOR, NAND or MMC.
Here the only 2 instructions are allowed in the first few bytes of the
image. And these instructions need to be one branch and a nop. This
patch adds the necessary nop after the nop, to that the common MIPS
image is compatible with this Octeon header.
The tool to patch the Octeon boot header into the image will be send in
a follow-up patch.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/mips/cpu/start.S | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index d0c4122..335aafa 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -74,9 +74,14 @@ .endm ENTRY(_start) - /* U-Boot entry point */ + /* + * U-Boot entry point. + * Do not add instructions to the branch delay slot! Some SoC's + * like Octeon might patch the final U-Boot binary at this location + * with additional boot headers. + */ b reset - mtc0 zero, CP0_COUNT # clear cp0 count for most accurate boot timing + nop #if defined(CONFIG_MIPS_INSERT_BOOT_CONFIG) /* @@ -123,6 +128,7 @@ ENTRY(_start) #endif reset: + mtc0 zero, CP0_COUNT # clear cp0 count for most accurate boot timing #if __mips_isa_rev >= 6 mfc0 t0, CP0_CONFIG, 5 and t0, t0, MIPS_CONF5_VP |