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| author | Simon Glass <sjg@chromium.org> | 2020-04-30 21:21:40 -0600 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2020-05-04 15:28:28 +0800 |
| commit | c2018cdd717732f3fc4b2bb9005d8c2e73088762 (patch) | |
| tree | b58ca1efe7a7541a3c63933865d69f4fa3179ca4 /arch | |
| parent | 7ec0e7b6356b12f495b780ecdb25b14204b62a9f (diff) | |
| download | u-boot-c2018cdd717732f3fc4b2bb9005d8c2e73088762.zip u-boot-c2018cdd717732f3fc4b2bb9005d8c2e73088762.tar.gz u-boot-c2018cdd717732f3fc4b2bb9005d8c2e73088762.tar.bz2 | |
x86: Allow building an SPL image for coreboot
Coreboot runs in 32-bit mode and cannot run a 64-bit U-Boot. To get around
this we can build a combined image with 32-bit SPL and 64-bit U-Boot. Add
a build rule and binman definition for this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/x86/cpu/coreboot/Kconfig | 1 | ||||
| -rw-r--r-- | arch/x86/dts/coreboot-u-boot.dtsi | 18 |
2 files changed, 19 insertions, 0 deletions
diff --git a/arch/x86/cpu/coreboot/Kconfig b/arch/x86/cpu/coreboot/Kconfig index c8e6a88..497d628 100644 --- a/arch/x86/cpu/coreboot/Kconfig +++ b/arch/x86/cpu/coreboot/Kconfig @@ -25,5 +25,6 @@ config SYS_COREBOOT imply FS_CBFS imply CBMEM_CONSOLE imply X86_TSC_READ_BASE + select BINMAN if X86_64 endif diff --git a/arch/x86/dts/coreboot-u-boot.dtsi b/arch/x86/dts/coreboot-u-boot.dtsi new file mode 100644 index 0000000..38efc48 --- /dev/null +++ b/arch/x86/dts/coreboot-u-boot.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 Google LLC + * Written by Simon Glass <sjg@chromium.org> + */ + +#include <config.h> + +/ { + binman { + filename = "u-boot-x86-with-spl.bin"; + u-boot-spl { + }; + u-boot { + offset = <0x10000>; + }; + }; +}; |