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| author | Vladimir Zapolskiy <vz@mleia.com> | 2015-08-27 03:16:48 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-09-11 14:05:35 -0400 |
| commit | bab8d1e2280f039fbbb3039ec4750e54091b6113 (patch) | |
| tree | 52d0faf44c994f1d628b52ccca1ebc2763c9dc0d /arch | |
| parent | c12e0d9317cf9a86622a32c7060b62f3b0f151f2 (diff) | |
| download | u-boot-bab8d1e2280f039fbbb3039ec4750e54091b6113.zip u-boot-bab8d1e2280f039fbbb3039ec4750e54091b6113.tar.gz u-boot-bab8d1e2280f039fbbb3039ec4750e54091b6113.tar.bz2 | |
lpc32xx: remove duplicated DMA_CLK_ENABLE bit definition
Because there is an originally defined CLK_DMA_ENABLE macro in clk.h,
no reason to add another DMA_CLK_ENABLE macro with the same value.
Remove DMA_CLK_ENABLE, since it does not follow naming convention from
the code, this implies renaming of DMA_CLK_ENABLE to CLK_DMA_ENABLE in
lpc32xx/devices.c file.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 3 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-lpc32xx/clk.h | 3 |
2 files changed, 1 insertions, 5 deletions
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c index d9fa280..b1c3f8f 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c +++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c @@ -44,8 +44,7 @@ void lpc32xx_uart_init(unsigned int uart_id) void lpc32xx_dma_init(void) { /* Enable DMA interface */ - writel(DMA_CLK_ENABLE, &clk->dmaclk_ctrl); - + writel(CLK_DMA_ENABLE, &clk->dmaclk_ctrl); } void lpc32xx_mac_init(void) diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h b/arch/arm/include/asm/arch-lpc32xx/clk.h index d21310e..303ff1c 100644 --- a/arch/arm/include/asm/arch-lpc32xx/clk.h +++ b/arch/arm/include/asm/arch-lpc32xx/clk.h @@ -158,9 +158,6 @@ struct clk_pm_regs { #define CLK_NAND_SLC_SELECT (1 << 2) #define CLK_NAND_MLC_INT (1 << 5) -/* DMA Clock Control Register bits */ -#define DMA_CLK_ENABLE (1 << 0) - /* SSP Clock Control Register bits */ #define CLK_SSP0_ENABLE_CLOCK (1 << 0) |