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| author | Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> | 2018-01-29 07:36:37 +0100 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2018-02-15 13:45:15 +0100 |
| commit | a6fbf9455090bdfa4d92e8215e81bdf7bb397757 (patch) | |
| tree | 7cb51f18d4a8fab3d7c636ebaa239ac75e2ed70d /arch | |
| parent | 0c502b6c176281a096a23803e517b19e964485f1 (diff) | |
| download | u-boot-a6fbf9455090bdfa4d92e8215e81bdf7bb397757.zip u-boot-a6fbf9455090bdfa4d92e8215e81bdf7bb397757.tar.gz u-boot-a6fbf9455090bdfa4d92e8215e81bdf7bb397757.tar.bz2 | |
arm: socfpga: fix qspi flash compatible (add "spi-flash")
This patch adds "spi-flash" to the compatible list of the qspi flash
chip for all socfpga boards. This is required to make qspi work on
these boards on top of the recent fixes. Without the "spi-flash"
compatible string for the flash chip, the speed cannot be read and a
speed of 0Hz is used (which results in a divide-by-zero on these
boards).
Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/socfpga_arria5_socdk.dts | 2 | ||||
| -rw-r--r-- | arch/arm/dts/socfpga_cyclone5_is1.dts | 2 | ||||
| -rw-r--r-- | arch/arm/dts/socfpga_cyclone5_socdk.dts | 2 | ||||
| -rw-r--r-- | arch/arm/dts/socfpga_cyclone5_socrates.dts | 2 |
4 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/dts/socfpga_arria5_socdk.dts b/arch/arm/dts/socfpga_arria5_socdk.dts index 1e91a65..4e4b619 100644 --- a/arch/arm/dts/socfpga_arria5_socdk.dts +++ b/arch/arm/dts/socfpga_arria5_socdk.dts @@ -88,7 +88,7 @@ u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; - compatible = "n25q00"; + compatible = "n25q00", "spi-flash"; reg = <0>; /* chip select */ spi-max-frequency = <50000000>; m25p,fast-read; diff --git a/arch/arm/dts/socfpga_cyclone5_is1.dts b/arch/arm/dts/socfpga_cyclone5_is1.dts index 2e2b71f..ea323a1 100644 --- a/arch/arm/dts/socfpga_cyclone5_is1.dts +++ b/arch/arm/dts/socfpga_cyclone5_is1.dts @@ -87,7 +87,7 @@ u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; - compatible = "n25q00"; + compatible = "n25q00", "spi-flash"; reg = <0>; /* chip select */ spi-max-frequency = <100000000>; m25p,fast-read; diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts index 95a8e65..3af5113 100644 --- a/arch/arm/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts @@ -98,7 +98,7 @@ u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; - compatible = "n25q00"; + compatible = "n25q00", "spi-flash"; reg = <0>; /* chip select */ spi-max-frequency = <100000000>; m25p,fast-read; diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts index e3ae8a8..e612eee 100644 --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts @@ -68,7 +68,7 @@ flash0: n25q00@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "n25q00"; + compatible = "n25q00", "spi-flash"; reg = <0>; /* chip select */ spi-max-frequency = <50000000>; m25p,fast-read; |