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| author | Kishon Vijay Abraham I <kishon@ti.com> | 2018-01-30 16:01:34 +0100 |
|---|---|---|
| committer | Jaehoon Chung <jh80.chung@samsung.com> | 2018-02-19 16:58:54 +0900 |
| commit | 9b3fc21837dc32eda9656f264f74719ea77311a2 (patch) | |
| tree | 066b0b655cabb565d1ed4e67a0869d8940f4dc82 /arch | |
| parent | 8fc238bfada16d61dee4240de2d49f38a6a6f941 (diff) | |
| download | u-boot-9b3fc21837dc32eda9656f264f74719ea77311a2.zip u-boot-9b3fc21837dc32eda9656f264f74719ea77311a2.tar.gz u-boot-9b3fc21837dc32eda9656f264f74719ea77311a2.tar.bz2 | |
mmc: omap_hsmmc: Enable DDR mode support
In order to enable DDR mode, Dual Data Rate mode bit has to be set in
MMCHS_CON register. Set it here.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/include/asm/omap_mmc.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h index 507435a..6aca9e9 100644 --- a/arch/arm/include/asm/omap_mmc.h +++ b/arch/arm/include/asm/omap_mmc.h @@ -89,6 +89,7 @@ struct omap_hsmmc_plat { #define WPP_ACTIVEHIGH (0x0 << 8) #define RESERVED_MASK (0x3 << 9) #define CTPL_MMC_SD (0x0 << 11) +#define DDR (0x1 << 19) #define DMA_MASTER (0x1 << 20) #define BLEN_512BYTESLEN (0x200 << 0) #define NBLK_STPCNT (0x0 << 16) |