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authorAshok Reddy Soma <ashok.reddy.soma@xilinx.com>2020-10-07 00:36:54 -0600
committerMichal Simek <michal.simek@xilinx.com>2020-10-27 08:13:31 +0100
commit90f06e9d20a402311b89b08eff5e1e0f2c987840 (patch)
tree76c455a825112f19fc531dd681e50c54c856f252 /arch
parent44d2be8d6aa5b73a8d8ca1b1d36d2e1e794f449d (diff)
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arm64: versal: Update mini u-boot eMMC node parameters
Mini u-boot eMMC dt parameters are not in sync with full u-boot dt. Frequency for eMMC is fixed to 25Mhz. Due to this, mmc multi-block write commands are failing. Increase frequency to 200Mhz to fix this issue. Add bus-width = <8>, non-removable and disable-wp properties to the node as this is eMMC. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/dts/versal-mini-emmc0.dts9
-rw-r--r--arch/arm/dts/versal-mini-emmc1.dts9
2 files changed, 12 insertions, 6 deletions
diff --git a/arch/arm/dts/versal-mini-emmc0.dts b/arch/arm/dts/versal-mini-emmc0.dts
index 7826a28..6a6e746 100644
--- a/arch/arm/dts/versal-mini-emmc0.dts
+++ b/arch/arm/dts/versal-mini-emmc0.dts
@@ -16,10 +16,10 @@
#size-cells = <2>;
model = "Xilinx Versal MINI eMMC0";
- clk25: clk25 {
+ clk200: clk200 {
compatible = "fixed-clock";
#clock-cells = <0x0>;
- clock-frequency = <25000000>;
+ clock-frequency = <200000000>;
};
dcc: dcc {
@@ -38,9 +38,12 @@
sdhci0: sdhci@f1040000 {
compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
status = "okay";
+ non-removable;
+ disable-wp;
+ bus-width = <8>;
reg = <0x0 0xf1040000 0x0 0x10000>;
clock-names = "clk_xin", "clk_ahb";
- clocks = <&clk25 &clk25>;
+ clocks = <&clk200 &clk200>;
xlnx,device_id = <0>;
no-1-8-v;
xlnx,mio-bank = <0>;
diff --git a/arch/arm/dts/versal-mini-emmc1.dts b/arch/arm/dts/versal-mini-emmc1.dts
index 2f28f85..c342e6b 100644
--- a/arch/arm/dts/versal-mini-emmc1.dts
+++ b/arch/arm/dts/versal-mini-emmc1.dts
@@ -16,10 +16,10 @@
#size-cells = <2>;
model = "Xilinx Versal MINI eMMC1";
- clk25: clk25 {
+ clk200: clk200 {
compatible = "fixed-clock";
#clock-cells = <0x0>;
- clock-frequency = <25000000>;
+ clock-frequency = <200000000>;
};
dcc: dcc {
@@ -38,9 +38,12 @@
sdhci1: sdhci@f1050000 {
compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
status = "okay";
+ non-removable;
+ disable-wp;
+ bus-width = <8>;
reg = <0x0 0xf1050000 0x0 0x10000>;
clock-names = "clk_xin", "clk_ahb";
- clocks = <&clk25 &clk25>;
+ clocks = <&clk200 &clk200>;
xlnx,device_id = <1>;
no-1-8-v;
xlnx,mio-bank = <0>;