m68k: rename CONFIG_MCFTMR to CFG_MCFTMR

This is not a Kconfig option so changing to _CFG.

Signed-off-by: Angelo Durgehello <angelo@kernel-space.org>

6 files changed, 23 insertions, 23 deletions

diff --git a/arch/m68k/cpu/mcf523x/interrupts.c b/arch/m68k/cpu/mcf523x/interrupts.c
index 331288e..b02ea29 100644
--- a/arch/m68k/cpu/mcf523x/interrupts.c
+++ b/arch/m68k/cpu/mcf523x/interrupts.c
@@ -22,7 +22,7 @@ int interrupt_init(void)
 	return 0;
 }
 
-#if defined(CONFIG_MCFTMR)
+#if defined(CFG_MCFTMR)
 void dtimer_intr_setup(void)
 {
 	int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
diff --git a/arch/m68k/cpu/mcf52x2/interrupts.c b/arch/m68k/cpu/mcf52x2/interrupts.c
index e8a1e13..e787c76 100644
--- a/arch/m68k/cpu/mcf52x2/interrupts.c
+++ b/arch/m68k/cpu/mcf52x2/interrupts.c
@@ -34,7 +34,7 @@ int interrupt_init(void)
 	return 0;
 }
 
-#if defined(CONFIG_MCFTMR)
+#if defined(CFG_MCFTMR)
 void dtimer_intr_setup(void)
 {
 	intctrl_t *intp = (intctrl_t *) (CFG_SYS_INTR_BASE);
@@ -42,7 +42,7 @@ void dtimer_intr_setup(void)
 	clrbits_be32(&intp->int_icr1, INT_ICR1_TMR3MASK);
 	setbits_be32(&intp->int_icr1, CFG_SYS_TMRINTR_PRI);
 }
-#endif				/* CONFIG_MCFTMR */
+#endif				/* CFG_MCFTMR */
 #endif				/* CONFIG_M5272 */
 
 #if defined(CONFIG_M5208) || defined(CONFIG_M5282) || \
@@ -63,7 +63,7 @@ int interrupt_init(void)
 	return 0;
 }
 
-#if defined(CONFIG_MCFTMR)
+#if defined(CFG_MCFTMR)
 void dtimer_intr_setup(void)
 {
 	int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
@@ -72,7 +72,7 @@ void dtimer_intr_setup(void)
 	clrbits_be32(&intp->imrl0, 0x00000001);
 	clrbits_be32(&intp->imrl0, CFG_SYS_TMRINTR_MASK);
 }
-#endif				/* CONFIG_MCFTMR */
+#endif				/* CFG_MCFTMR */
 #endif				/* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */
 
 #if defined(CONFIG_M5249) || defined(CONFIG_M5253)
@@ -83,11 +83,11 @@ int interrupt_init(void)
 	return 0;
 }
 
-#if defined(CONFIG_MCFTMR)
+#if defined(CFG_MCFTMR)
 void dtimer_intr_setup(void)
 {
 	mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400);
 	mbar_writeByte(MCFSIM_TIMER2ICR, CFG_SYS_TMRINTR_PRI);
 }
-#endif				/* CONFIG_MCFTMR */
+#endif				/* CFG_MCFTMR */
 #endif				/* CONFIG_M5249 || CONFIG_M5253 */
diff --git a/arch/m68k/cpu/mcf532x/interrupts.c b/arch/m68k/cpu/mcf532x/interrupts.c
index 64e0466..bbe823c 100644
--- a/arch/m68k/cpu/mcf532x/interrupts.c
+++ b/arch/m68k/cpu/mcf532x/interrupts.c
@@ -23,7 +23,7 @@ int interrupt_init(void)
 	return 0;
 }
 
-#if defined(CONFIG_MCFTMR)
+#if defined(CFG_MCFTMR)
 void dtimer_intr_setup(void)
 {
 	int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
diff --git a/arch/m68k/cpu/mcf5445x/interrupts.c b/arch/m68k/cpu/mcf5445x/interrupts.c
index ea0cf87..fb80a87 100644
--- a/arch/m68k/cpu/mcf5445x/interrupts.c
+++ b/arch/m68k/cpu/mcf5445x/interrupts.c
@@ -26,7 +26,7 @@ int interrupt_init(void)
 	return 0;
 }
 
-#if defined(CONFIG_MCFTMR)
+#if defined(CFG_MCFTMR)
 void dtimer_intr_setup(void)
 {
 	int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h
index 8207c8d..74516cc 100644
--- a/arch/m68k/include/asm/immap.h
+++ b/arch/m68k/include/asm/immap.h
@@ -16,7 +16,7 @@
 #define CFG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
 
 /* Timer */
-#ifdef CONFIG_MCFTMR
+#ifdef CFG_MCFTMR
 #define CFG_SYS_UDELAY_BASE		(MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE		(MMAP_DTMR1)
 #define CFG_SYS_TMRPND_REG		(((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
@@ -38,7 +38,7 @@
 #define CFG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
 
 /* Timer */
-#ifdef CONFIG_MCFTMR
+#ifdef CFG_MCFTMR
 #define CFG_SYS_UDELAY_BASE		(MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE		(MMAP_DTMR3)
 #define CFG_SYS_TMRPND_REG		(((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
@@ -63,7 +63,7 @@
 #define CFG_SYS_NUM_IRQS		(64)
 
 /* Timer */
-#ifdef CONFIG_MCFTMR
+#ifdef CFG_MCFTMR
 #define CFG_SYS_UDELAY_BASE		(MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE		(MMAP_DTMR1)
 #define CFG_SYS_TMRPND_REG		(mbar_readLong(MCFSIM_IPR))
@@ -86,7 +86,7 @@
 #define CFG_SYS_NUM_IRQS		(64)
 
 /* Timer */
-#ifdef CONFIG_MCFTMR
+#ifdef CFG_MCFTMR
 #define CFG_SYS_UDELAY_BASE		(MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE		(MMAP_DTMR1)
 #define CFG_SYS_TMRPND_REG		(mbar_readLong(MCFSIM_IPR))
@@ -105,7 +105,7 @@
 #define CFG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
 
 /* Timer */
-#ifdef CONFIG_MCFTMR
+#ifdef CFG_MCFTMR
 #define CFG_SYS_UDELAY_BASE		(MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE		(MMAP_DTMR3)
 #define CFG_SYS_TMRPND_REG		(((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
@@ -130,7 +130,7 @@
 #define CFG_SYS_NUM_IRQS		(64)
 
 /* Timer */
-#ifdef CONFIG_MCFTMR
+#ifdef CFG_MCFTMR
 #define CFG_SYS_UDELAY_BASE		(MMAP_TMR0)
 #define CFG_SYS_TMR_BASE		(MMAP_TMR3)
 #define CFG_SYS_TMRPND_REG		(((volatile intctrl_t *)(CFG_SYS_INTR_BASE))->int_isr)
@@ -152,7 +152,7 @@
 #define CFG_SYS_NUM_IRQS		(192)
 
 /* Timer */
-#ifdef CONFIG_MCFTMR
+#ifdef CFG_MCFTMR
 #define CFG_SYS_UDELAY_BASE		(MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE		(MMAP_DTMR3)
 #define CFG_SYS_TMRPND_REG		(((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
@@ -174,7 +174,7 @@
 #define CFG_SYS_NUM_IRQS		(128)
 
 /* Timer */
-#ifdef CONFIG_MCFTMR
+#ifdef CFG_MCFTMR
 #define CFG_SYS_UDELAY_BASE		(MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE		(MMAP_DTMR3)
 #define CFG_SYS_TMRPND_REG		(((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
@@ -196,7 +196,7 @@
 #define CFG_SYS_NUM_IRQS             (64)
 
 /* Timer */
-#ifdef CONFIG_MCFTMR
+#ifdef CFG_MCFTMR
 #define CFG_SYS_UDELAY_BASE          (MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE             (MMAP_DTMR1)
 #define CFG_SYS_TMRPND_REG		(((volatile intctrl_t *) \
@@ -217,7 +217,7 @@
 #define CFG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
 
 /* Timer */
-#ifdef CONFIG_MCFTMR
+#ifdef CFG_MCFTMR
 #define CFG_SYS_UDELAY_BASE		(MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE		(MMAP_DTMR1)
 #define CFG_SYS_TMRPND_REG		(((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
@@ -239,7 +239,7 @@
 #define CFG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
 
 /* Timer */
-#ifdef CONFIG_MCFTMR
+#ifdef CFG_MCFTMR
 #define CFG_SYS_UDELAY_BASE		(MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE		(MMAP_DTMR1)
 #define CFG_SYS_TMRPND_REG		(((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
@@ -269,7 +269,7 @@
 #define MMAP_DSPI			MMAP_DSPI0
 
 /* Timer */
-#ifdef CONFIG_MCFTMR
+#ifdef CFG_MCFTMR
 #define CFG_SYS_UDELAY_BASE		(MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE		(MMAP_DTMR1)
 #define CFG_SYS_TMRPND_REG	(((int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
diff --git a/arch/m68k/lib/time.c b/arch/m68k/lib/time.c
index 2ce6908..ca8c039 100644
--- a/arch/m68k/lib/time.c
+++ b/arch/m68k/lib/time.c
@@ -25,7 +25,7 @@ static volatile ulong timestamp = 0;
 #define CFG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 2)
 #endif
 
-#if defined(CONFIG_MCFTMR)
+#if defined(CFG_MCFTMR)
 #ifndef CFG_SYS_UDELAY_BASE
 #	error	"uDelay base not defined!"
 #endif
@@ -111,7 +111,7 @@ ulong get_timer(ulong base)
 	return (timestamp - base);
 }
 
-#endif				/* CONFIG_MCFTMR */
+#endif				/* CFG_MCFTMR */
 
 /*
  * This function is derived from PowerPC code (read timebase as long long).