Merge tag 'xilinx-for-v2023.10-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into nextWIP/12Jun2023-next

Xilinx changes for v2023.10-rc1

global:
- Use proper U-Boot project name

Fix sparse warnings in zynqmp-clk, zynqmp handoff, board

cmd:
- Cover incorrect 0 length entries

Versal NET:
- Add bootmode logic
- Support SPP production version
- Add loadpdi command

ZynqMP:
- Clear pmufw node command ID handling
- Change power domain behavior around zynqmp_pmufw_node()
- Fix zynqmp cmd return values and pmufw command
- Fix R5 tcm init and modes

mmc:
- Sync Versal NET emmc DT binding

pcie:
- Add support for ZynqMP PCIe root port

video:
- Add support for ZynqMP DP

tools:
- Fix debug message in relocate-rela

17 files changed, 44 insertions, 16 deletions

diff --git a/arch/Kconfig.nxp b/arch/Kconfig.nxp
index 6e1c44b..e75226b 100644
--- a/arch/Kconfig.nxp
+++ b/arch/Kconfig.nxp
@@ -90,7 +90,7 @@ config SPL_UBOOT_KEY_HASH
 	default ""
 	help
 	  Set the key hash for U-Boot here if public/private key pair used to
-	  sign U-boot are different from the SRK hash put in the fuse.  Example
+	  sign U-Boot are different from the SRK hash put in the fuse.  Example
 	  of a key hash is
 	  41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b.
 	  Otherwise leave this empty.
diff --git a/arch/arc/include/asm/io.h b/arch/arc/include/asm/io.h
index 6adc0ed..c818b8b 100644
--- a/arch/arc/include/asm/io.h
+++ b/arch/arc/include/asm/io.h
@@ -80,7 +80,7 @@ static inline void sync(void)
 
 /*
  * We add memory barriers for __raw_readX / __raw_writeX accessors same way as
- * it is done for readX and writeX accessors as lots of U-boot driver uses
+ * it is done for readX and writeX accessors as lots of U-Boot driver uses
  * __raw_readX / __raw_writeX instead of proper accessor with barrier.
  */
 #define __raw_writeb(v, c)	({ __iowmb(); __arch_putb(v, c); })
diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig
index e33e536..ccc2f20 100644
--- a/arch/arm/cpu/armv7/Kconfig
+++ b/arch/arm/cpu/armv7/Kconfig
@@ -110,7 +110,7 @@ config ARMV7_LPAE
 config ARMV7_SET_CORTEX_SMPEN
 	bool
 	help
-	  Enable the ARM Cortex ACTLR.SMP enable bit in U-boot.
+	  Enable the ARM Cortex ACTLR.SMP enable bit in U-Boot.
 
 config SPL_ARMV7_SET_CORTEX_SMPEN
 	bool
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 7d5cf15..9f0fb36 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -145,7 +145,7 @@ config ARMV8_PSCI
 	bool "Enable PSCI support" if EXPERT
 	help
 	  PSCI is Power State Coordination Interface defined by ARM.
-	  The PSCI in U-boot provides a general framework and each platform
+	  The PSCI in U-Boot provides a general framework and each platform
 	  can implement their own specific PSCI functions.
 	  Say Y here to enable PSCI support on ARMv8 platform.
 
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
index 6f3fe7c..1ddf947 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
@@ -125,7 +125,7 @@ mcinitcmd:	This environment variable is defined to initiate MC and DPL deploymen
 		from the location where it is stored(NOR, NAND, SD, SATA, USB)during
 		u-boot booting.If this variable is not defined then MC_BOOT_ENV_VAR
 		will be null and MC will not be booted and DPL will not be applied
-		during U-boot booting.However the MC, DPC and DPL can be applied from
+		during U-Boot booting.However the MC, DPC and DPL can be applied from
 		console independently.
 		The variable needs to be set from the console once and then on
 		rebooting the parameters set in the variable will automatically be
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index 06b36cc..dde0c40 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -51,7 +51,7 @@
 
 	idle-states {
 		/*
-		 * PSCI node is not added default, U-boot will add missing
+		 * PSCI node is not added default, U-Boot will add missing
 		 * parts if it determines to use PSCI.
 		 */
 		entry-method = "psci";
diff --git a/arch/arm/dts/meson-g12-common-u-boot.dtsi b/arch/arm/dts/meson-g12-common-u-boot.dtsi
index efa6a05..8070b62 100644
--- a/arch/arm/dts/meson-g12-common-u-boot.dtsi
+++ b/arch/arm/dts/meson-g12-common-u-boot.dtsi
@@ -5,7 +5,7 @@
  */
 
 / {
-	/* Keep HW order from U-boot */
+	/* Keep HW order from U-Boot */
 	aliases {
 		/delete-property/ mmc0;
 		/delete-property/ mmc1;
diff --git a/arch/arm/dts/meson-gx-u-boot.dtsi b/arch/arm/dts/meson-gx-u-boot.dtsi
index 9f123ab..9e0620f 100644
--- a/arch/arm/dts/meson-gx-u-boot.dtsi
+++ b/arch/arm/dts/meson-gx-u-boot.dtsi
@@ -5,7 +5,7 @@
  */
 
 / {
-	/* Keep HW order from U-boot */
+	/* Keep HW order from U-Boot */
 	aliases {
 		/delete-property/ mmc0;
 		/delete-property/ mmc1;
diff --git a/arch/arm/dts/rk3328-evb-u-boot.dtsi b/arch/arm/dts/rk3328-evb-u-boot.dtsi
index 4bfa0c2..95e4979 100644
--- a/arch/arm/dts/rk3328-evb-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-evb-u-boot.dtsi
@@ -41,7 +41,7 @@
 };
 
 &gmac2phy {
-	/* Integrated PHY unsupported by U-boot */
+	/* Integrated PHY unsupported by U-Boot */
 	status = "broken";
 };
 
diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi
index 27e45d5..e8d8f00 100644
--- a/arch/arm/dts/rk3328.dtsi
+++ b/arch/arm/dts/rk3328.dtsi
@@ -984,7 +984,7 @@
 	};
 
 	/*
-	 * U-boot Specific Change
+	 * U-Boot Specific Change
 	 *
 	 * The OTG controller must come after the USB host pair for it
 	 * to work. This is likely due to lack of support for the USB
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h
index 1b02d48..c18c51e 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h
@@ -22,7 +22,7 @@
  *
  *  -PCIe
  *     -there is a range of stream IDs set aside for PCI in this
- *      file.  U-boot will scan the PCI bus and for each device discovered:
+ *      file.  U-Boot will scan the PCI bus and for each device discovered:
  *         -allocate a streamID
  *         -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID'
  *         -set a msi-map entry in the PEXn controller node in the
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
index b36b6d38..140849d 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
@@ -23,7 +23,7 @@
  *
  *  -PCIe
  *     -there is a range of stream IDs set aside for PCI in this
- *      file.  U-boot will scan the PCI bus and for each device discovered:
+ *      file.  U-Boot will scan the PCI bus and for each device discovered:
  *         -allocate a streamID
  *         -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID'
  *         -set a msi-map entry in the PEXn controller node in the
diff --git a/arch/arm/mach-versal-net/include/mach/hardware.h b/arch/arm/mach-versal-net/include/mach/hardware.h
index c5e4e22..3f04104 100644
--- a/arch/arm/mach-versal-net/include/mach/hardware.h
+++ b/arch/arm/mach-versal-net/include/mach/hardware.h
@@ -27,7 +27,13 @@ struct iou_scntrs_regs {
 	u32 base_frequency_id_register; /* 0x20 */
 };
 
+struct crp_regs {
+	u32 reserved0[128];
+	u32 boot_mode_usr;	/* 0x200 */
+};
+
 #define VERSAL_NET_CRL_APB_BASEADDR		0xEB5E0000
+#define VERSAL_NET_CRP_BASEADDR			0xF1260000
 #define VERSAL_NET_IOU_SCNTR_SECURE		0xEC920000
 
 #define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT	BIT(25)
@@ -36,6 +42,7 @@ struct iou_scntrs_regs {
 #define IOU_SCNTRS_CONTROL_EN			1
 
 #define crlapb_base ((struct crlapb_regs *)VERSAL_NET_CRL_APB_BASEADDR)
+#define crp_base ((struct crp_regs *)VERSAL_NET_CRP_BASEADDR)
 #define iou_scntr_secure ((struct iou_scntrs_regs *)VERSAL_NET_IOU_SCNTR_SECURE)
 
 #define PMC_TAP	0xF11A0000
@@ -44,11 +51,26 @@ struct iou_scntrs_regs {
 #define PMC_TAP_VERSION		(PMC_TAP + 0x4)
 # define PMC_VERSION_MASK	GENMASK(7, 0)
 # define PS_VERSION_MASK	GENMASK(15, 8)
+# define PS_VERSION_PRODUCTION	0x20
 # define RTL_VERSION_MASK	GENMASK(23, 16)
 # define PLATFORM_MASK		GENMASK(27, 24)
 # define PLATFORM_VERSION_MASK	GENMASK(31, 28)
 #define PMC_TAP_USERCODE	(PMC_TAP + 0x8)
 
+/* Bootmode setting values */
+#define BOOT_MODES_MASK	0x0000000F
+#define QSPI_MODE_24BIT	0x00000001
+#define QSPI_MODE_32BIT	0x00000002
+#define SD_MODE		0x00000003 /* sd 0 */
+#define SD_MODE1	0x00000005 /* sd 1 */
+#define EMMC_MODE	0x00000006
+#define USB_MODE	0x00000007
+#define OSPI_MODE	0x00000008
+#define SD1_LSHFT_MODE	0x0000000E /* SD1 Level shifter */
+#define JTAG_MODE	0x00000000
+#define BOOT_MODE_USE_ALT	0x100
+#define BOOT_MODE_ALT_SHIFT	12
+
 enum versal_net_platform {
 	VERSAL_NET_SILICON = 0,
 	VERSAL_NET_SPP = 1,
diff --git a/arch/arm/mach-versal/include/mach/sys_proto.h b/arch/arm/mach-versal/include/mach/sys_proto.h
index 3f01508..433f9ba 100644
--- a/arch/arm/mach-versal/include/mach/sys_proto.h
+++ b/arch/arm/mach-versal/include/mach/sys_proto.h
@@ -10,6 +10,7 @@ enum {
 	TCM_SPLIT,
 };
 
+void initialize_tcm(bool mode);
 void tcm_init(u8 mode);
 void mem_map_fill(void);
 
diff --git a/arch/arm/mach-versal/mp.c b/arch/arm/mach-versal/mp.c
index 9b0518d..5b850f3 100644
--- a/arch/arm/mach-versal/mp.c
+++ b/arch/arm/mach-versal/mp.c
@@ -23,7 +23,7 @@
 #define VERSAL_CRL_RST_CPU_R5_RESET_PGE_MASK	0x10
 #define VERSAL_CRLAPB_CPU_R5_CTRL_CLKACT_MASK	0x1000000
 
-void set_r5_halt_mode(u8 halt, u8 mode)
+static void set_r5_halt_mode(u8 halt, u8 mode)
 {
 	u32 tmp;
 
@@ -44,7 +44,7 @@ void set_r5_halt_mode(u8 halt, u8 mode)
 	}
 }
 
-void set_r5_tcm_mode(u8 mode)
+static void set_r5_tcm_mode(u8 mode)
 {
 	u32 tmp;
 
@@ -62,7 +62,7 @@ void set_r5_tcm_mode(u8 mode)
 	writel(tmp, &rpu_base->rpu_glbl_ctrl);
 }
 
-void release_r5_reset(u8 mode)
+static void release_r5_reset(u8 mode)
 {
 	u32 tmp;
 
@@ -77,7 +77,7 @@ void release_r5_reset(u8 mode)
 	writel(tmp, &crlapb_base->rst_cpu_r5);
 }
 
-void enable_clock_r5(void)
+static void enable_clock_r5(void)
 {
 	u32 tmp;
 
diff --git a/arch/arm/mach-zynqmp/handoff.c b/arch/arm/mach-zynqmp/handoff.c
index b9e0c6c..511b241 100644
--- a/arch/arm/mach-zynqmp/handoff.c
+++ b/arch/arm/mach-zynqmp/handoff.c
@@ -9,6 +9,7 @@
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
+#include <spl.h>
 
 /*
  * atfhandoffparams
diff --git a/arch/arm/mach-zynqmp/mp.c b/arch/arm/mach-zynqmp/mp.c
index 7a12f4b..b06c867 100644
--- a/arch/arm/mach-zynqmp/mp.c
+++ b/arch/arm/mach-zynqmp/mp.c
@@ -326,6 +326,10 @@ int cpu_release(u32 nr, int argc, char *const argv[])
 		flush_dcache_all();
 
 		if (!strncmp(argv[1], "lockstep", 8)) {
+			if (nr != ZYNQMP_CORE_RPU0) {
+				printf("Lockstep mode should run on ZYNQMP_CORE_RPU0\n");
+				return 1;
+			}
 			printf("R5 lockstep mode\n");
 			set_r5_reset(nr, LOCK);
 			set_r5_tcm_mode(LOCK);