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| author | Bob Liu <lliubbo@gmail.com> | 2011-10-25 18:07:58 +0800 |
|---|---|---|
| committer | sonic <sonic@sonic-linuxvm.(none)> | 2013-03-04 13:42:07 +0800 |
| commit | 7677d65f6522b1a911ac3a24225ec29709106010 (patch) | |
| tree | 8da29d3a446b773b544929b5041c17be06f14132 /arch | |
| parent | ee8259623e57acf738aee548a8e9bee0a543f3f0 (diff) | |
| download | u-boot-7677d65f6522b1a911ac3a24225ec29709106010.zip u-boot-7677d65f6522b1a911ac3a24225ec29709106010.tar.gz u-boot-7677d65f6522b1a911ac3a24225ec29709106010.tar.bz2 | |
blackfin: bf60x: support big cplb page
BF60x support 16K, 64K, 16M and 64M cplb pages, this patch add support for them.
So that bf609-ezkit can use it's 128M memory.
Signed-off-by: Bob Liu <lliubbo@gmail.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Sonic Zhang <sonic.adi@gmail.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/blackfin/include/asm/cplb.h | 31 | ||||
| -rw-r--r-- | arch/blackfin/lib/board.c | 19 |
2 files changed, 44 insertions, 6 deletions
diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h index cc21e93..420380d 100644 --- a/arch/blackfin/include/asm/cplb.h +++ b/arch/blackfin/include/asm/cplb.h @@ -46,8 +46,13 @@ #define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL /* Data Attibutes*/ - -#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID) +#if defined(__ADSPBF60x__) +#define SDRAM_IGENERIC (PAGE_SIZE_16MB | CPLB_L1_CHBL | \ + CPLB_USER_RD | CPLB_VALID) +#else +#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | \ + CPLB_USER_RD | CPLB_VALID) +#endif #define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) #define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) #define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID) @@ -59,14 +64,32 @@ #endif #ifdef CONFIG_DCACHE_WB /*Write Back Policy */ -#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) +#if defined(__ADSPBF60x__) +#define SDRAM_DGENERIC (PAGE_SIZE_16MB | CPLB_L1_CHBL | CPLB_DIRTY | \ + CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | \ + CPLB_VALID | ANOMALY_05000158_WORKAROUND) +#else +#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | \ + CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | \ + CPLB_VALID | ANOMALY_05000158_WORKAROUND) +#endif #define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND) #define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158_WORKAROUND) #define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) #define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND) #else /*Write Through */ -#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND) +#if defined(__ADSPBF60x__) +#define SDRAM_DGENERIC (PAGE_SIZE_16MB | CPLB_L1_CHBL | CPLB_WT | \ + CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | \ + CPLB_USER_WR | CPLB_VALID | \ + ANOMALY_05000158_WORKAROUND) +#else +#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | \ + CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | \ + CPLB_USER_WR | CPLB_VALID | \ + ANOMALY_05000158_WORKAROUND) +#endif #define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) #define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158_WORKAROUND) #define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND) diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c index 098f685..288dc82 100644 --- a/arch/blackfin/lib/board.c +++ b/arch/blackfin/lib/board.c @@ -96,6 +96,13 @@ static void display_global_data(void) #define CPLB_PAGE_SIZE (4 * 1024 * 1024) #define CPLB_PAGE_MASK (~(CPLB_PAGE_SIZE - 1)) +#if defined(__ADSPBF60x__) +#define CPLB_EX_PAGE_SIZE (16 * 1024 * 1024) +#define CPLB_EX_PAGE_MASK (~(CPLB_EX_PAGE_SIZE - 1)) +#else +#define CPLB_EX_PAGE_SIZE CPLB_PAGE_SIZE +#define CPLB_EX_PAGE_MASK CPLB_PAGE_MASK +#endif void init_cplbtables(void) { volatile uint32_t *ICPLB_ADDR, *ICPLB_DATA; @@ -127,6 +134,11 @@ void init_cplbtables(void) icplb_add(0xFFA00000, L1_IMEMORY); dcplb_add(0xFF800000, L1_DMEMORY); ++i; +#if defined(__ADSPBF60x__) + icplb_add(0x0, 0x0); + dcplb_add(CONFIG_SYS_FLASH_BASE, SDRAM_EBIU); + ++i; +#endif if (CONFIG_MEM_SIZE) { uint32_t mbase = CONFIG_SYS_MONITOR_BASE; @@ -150,9 +162,11 @@ void init_cplbtables(void) } } +#ifndef __ADSPBF60x__ icplb_add(0x20000000, SDRAM_INON_CHBL); dcplb_add(0x20000000, SDRAM_EBIU); ++i; +#endif /* Add entries for the rest of external RAM up to the bootrom */ extern_memory = 0; @@ -167,10 +181,11 @@ void init_cplbtables(void) ++i; #endif - while (i < 16 && extern_memory < (CONFIG_SYS_MONITOR_BASE & CPLB_PAGE_MASK)) { + while (i < 16 && extern_memory < + (CONFIG_SYS_MONITOR_BASE & CPLB_EX_PAGE_MASK)) { icplb_add(extern_memory, SDRAM_IGENERIC); dcplb_add(extern_memory, SDRAM_DGENERIC); - extern_memory += CPLB_PAGE_SIZE; + extern_memory += CPLB_EX_PAGE_SIZE; ++i; } while (i < 16) { |