Merge tag 'u-boot-imx-20230525' of https://gitlab.denx.de/u-boot/custodians/u-boot-imxWIP/25May2023

u-boot-imx-20230525
-------------------

- i.MX93 series
- Fixes

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/16412

37 files changed, 1163 insertions, 1616 deletions

diff --git a/arch/arm/dts/imx7d-sdb-u-boot.dtsi b/arch/arm/dts/imx7d-sdb-u-boot.dtsi
index b78358f..ac1d6e2 100644
--- a/arch/arm/dts/imx7d-sdb-u-boot.dtsi
+++ b/arch/arm/dts/imx7d-sdb-u-boot.dtsi
@@ -5,3 +5,54 @@
 &usbotg1 {
 	dr_mode = "peripheral";
 };
+
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
+};
+
+&pinctrl_usdhc1 {
+		fsl,pins = <
+			MX7D_PAD_SD1_CMD__SD1_CMD		0x59
+			MX7D_PAD_SD1_CLK__SD1_CLK		0x19
+			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x59
+			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x59
+			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x59
+			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x59
+		>;
+};
+
+&iomuxc {
+	pinctrl_usdhc1_gpio: usdhc1gpiogrp {
+		fsl,pins = <
+			MX7D_PAD_SD1_CD_B__GPIO5_IO0		0x59 /* CD */
+			MX7D_PAD_SD1_WP__GPIO5_IO1		0x59 /* WP */
+			MX7D_PAD_SD1_RESET_B__GPIO5_IO2		0x59 /* vmmc */
+			MX7D_PAD_GPIO1_IO08__SD1_VSELECT	0x59 /* VSELECT */
+		>;
+	};
+
+	pinctrl_usdhc1_100mhz: usdhc1100mhzgrp {
+		fsl,pins = <
+			MX7D_PAD_SD1_CMD__SD1_CMD		0x5a
+			MX7D_PAD_SD1_CLK__SD1_CLK		0x1a
+			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5a
+			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5a
+			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5a
+			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x5a
+		>;
+	};
+
+	pinctrl_usdhc1_200mhz: usdhc1200mhzgrp {
+		fsl,pins = <
+			MX7D_PAD_SD1_CMD__SD1_CMD		0x5b
+			MX7D_PAD_SD1_CLK__SD1_CLK		0x1b
+			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5b
+			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5b
+			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5b
+			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x5b
+		>;
+	};
+};
diff --git a/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi
index 89e6434..5b465e2 100644
--- a/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi
@@ -10,25 +10,6 @@
 		bootph-pre-ram;
 	};
 
-	aliases {
-		usbgadget0 = &usbg1;
-		usbgadget1 = &usbg2;
-	};
-
-	usbg1: usbg1 {
-		compatible = "fsl,imx27-usb-gadget";
-		dr_mode = "peripheral";
-		chipidea,usb = <&usbotg1>;
-		status = "okay";
-	};
-
-	usbg2: usbg2 {
-		compatible = "fsl,imx27-usb-gadget";
-		dr_mode = "peripheral";
-		chipidea,usb = <&usbotg2>;
-		status = "okay";
-	};
-
 	firmware {
 		optee {
 			compatible = "linaro,optee-tz";
@@ -141,16 +122,6 @@
 	reset-deassert-us = <100000>;
 };
 
-&usbotg1 {
-	status = "okay";
-	extcon = <&ptn5110>;
-};
-
-&usbotg2 {
-	status = "okay";
-	extcon = <&ptn5110_2>;
-};
-
 &s4muap {
 	bootph-pre-ram;
 	status = "okay";
diff --git a/arch/arm/dts/imx93-11x11-evk.dts b/arch/arm/dts/imx93-11x11-evk.dts
index b3a5a3d..4322cc3 100644
--- a/arch/arm/dts/imx93-11x11-evk.dts
+++ b/arch/arm/dts/imx93-11x11-evk.dts
@@ -1,36 +1,25 @@
 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
- * Copyright 2021 NXP
+ * Copyright 2022 NXP
  */
 
 /dts-v1/;
 
 #include "imx93.dtsi"
 
-/{
+/ {
+	model = "NXP i.MX93 11X11 EVK board";
+	compatible = "fsl,imx93-11x11-evk", "fsl,imx93";
+
 	chosen {
 		stdout-path = &lpuart1;
 	};
 
-	reserved-memory {
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-
-		audio: audio@a4120000 {
-			compatible = "shared-dma-pool";
-			reg = <0 0xa4120000 0 0x100000>;
-			no-map;
-		};
-	};
-
-	reg_can2_stby: regulator-can2-stby {
+	reg_vref_1v8: regulator-adc-vref {
 		compatible = "regulator-fixed";
-		regulator-name = "can2-stby";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		gpio = <&adp5585gpio 5 GPIO_ACTIVE_LOW>;
-		enable-active-low;
+		regulator-name = "vref_1v8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
 	};
 
 	reg_usdhc2_vmmc: regulator-usdhc2 {
@@ -43,81 +32,57 @@
 		gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
 		enable-active-high;
 	};
+};
 
-	usdhc3_pwrseq: usdhc3_pwrseq {
-		compatible = "mmc-pwrseq-simple";
-		reset-gpios = <&pcal6524 20 GPIO_ACTIVE_LOW>;
-	};
-
-	reg_vref_1v8: regulator-adc-vref {
-		compatible = "regulator-fixed";
-		regulator-name = "vref_1v8";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-	};
+&adc1 {
+	vref-supply = <&reg_vref_1v8>;
+	status = "okay";
+};
 
+&mu1 {
+	status = "okay";
 };
 
-&lpi2c1 {
-	#address-cells = <1>;
-	#size-cells = <0>;
-	clock-frequency = <400000>;
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&pinctrl_lpi2c1>;
-	pinctrl-1 = <&pinctrl_lpi2c1>;
+&mu2 {
 	status = "okay";
+};
 
-	ptn5110: tcpc@50 {
-		compatible = "nxp,ptn5110";
-		reg = <0x50>;
-		interrupt-parent = <&pcal6524>;
-		interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
-		status = "okay";
+&eqos {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_eqos>;
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethphy1>;
+	status = "okay";
 
-		port {
-			typec1_dr_sw: endpoint {
-				remote-endpoint = <&usb1_drd_sw>;
-			};
-		};
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clock-frequency = <5000000>;
 
-		typec1_con: connector {
-			compatible = "usb-c-connector";
-			label = "USB-C";
-			power-role = "dual";
-			data-role = "dual";
-			try-power-role = "sink";
-			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
-			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
-				     PDO_VAR(5000, 20000, 3000)>;
-			op-sink-microwatt = <15000000>;
-			self-powered;
+		ethphy1: ethernet-phy@1 {
+			reg = <1>;
+			eee-broken-1000t;
 		};
 	};
+};
 
-	ptn5110_2: tcpc@51 {
-		compatible = "nxp,ptn5110";
-		reg = <0x51>;
-		interrupt-parent = <&pcal6524>;
-		interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
-		status = "okay";
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec>;
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethphy2>;
+	fsl,magic-packet;
+	status = "okay";
 
-		port {
-			typec2_dr_sw: endpoint {
-				remote-endpoint = <&usb2_drd_sw>;
-			};
-		};
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clock-frequency = <5000000>;
 
-		typec2_con: connector {
-			compatible = "usb-c-connector";
-			label = "USB-C";
-			power-role = "dual";
-			data-role = "dual";
-			try-power-role = "sink";
-			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
-			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
-				     PDO_VAR(5000, 20000, 3000)>;
-			op-sink-microwatt = <15000000>;
-			self-powered;
+		ethphy2: ethernet-phy@2 {
+			reg = <2>;
+			eee-broken-1000t;
 		};
 	};
 };
@@ -134,15 +99,14 @@
 	pmic@25 {
 		compatible = "nxp,pca9451a";
 		reg = <0x25>;
-		pinctrl-names = "default";
 		interrupt-parent = <&pcal6524>;
-		interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
+		interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
 
 		regulators {
 			buck1: BUCK1 {
 				regulator-name = "BUCK1";
-				regulator-min-microvolt = <600000>;
-				regulator-max-microvolt = <2187500>;
+				regulator-min-microvolt = <650000>;
+				regulator-max-microvolt = <2237500>;
 				regulator-boot-on;
 				regulator-always-on;
 				regulator-ramp-delay = <3125>;
@@ -189,22 +153,6 @@
 				regulator-always-on;
 			};
 
-			ldo2: LDO2 {
-				regulator-name = "LDO2";
-				regulator-min-microvolt = <800000>;
-				regulator-max-microvolt = <1150000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			ldo3: LDO3 {
-				regulator-name = "LDO3";
-				regulator-min-microvolt = <800000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
 			ldo4: LDO4 {
 				regulator-name = "LDO4";
 				regulator-min-microvolt = <800000>;
@@ -250,48 +198,6 @@
 	status = "okay";
 };
 
-&lpuart2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart2>;
-	status = "disabled";
-};
-
-&usbotg1 {
-	dr_mode = "otg";
-	hnp-disable;
-	srp-disable;
-	adp-disable;
-	usb-role-switch;
-	disable-over-current;
-	samsung,picophy-pre-emp-curr-control = <3>;
-	samsung,picophy-dc-vol-level-adjust = <7>;
-	status = "okay";
-
-	port {
-		usb1_drd_sw: endpoint {
-			remote-endpoint = <&typec1_dr_sw>;
-		};
-	};
-};
-
-&usbotg2 {
-	dr_mode = "otg";
-	hnp-disable;
-	srp-disable;
-	adp-disable;
-	usb-role-switch;
-	disable-over-current;
-	samsung,picophy-pre-emp-curr-control = <3>;
-	samsung,picophy-dc-vol-level-adjust = <7>;
-	status = "okay";
-
-	port {
-		usb2_drd_sw: endpoint {
-			remote-endpoint = <&typec2_dr_sw>;
-		};
-	};
-};
-
 &usdhc1 {
 	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 	pinctrl-0 = <&pinctrl_usdhc1>;
@@ -315,116 +221,17 @@
 	no-mmc;
 };
 
-&usdhc3 {
-	status = "disabled";
-};
-
-&fec {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_fec>;
-	phy-mode = "rgmii-id";
-	phy-handle = <&ethphy2>;
-	fsl,magic-packet;
-	status = "okay";
-
-	mdio {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clock-frequency = <5000000>;
-
-		ethphy2: ethernet-phy@2 {
-			compatible = "ethernet-phy-ieee802.3-c22";
-			reg = <2>;
-			eee-broken-1000t;
-			rtl821x,aldps-disable;
-			rtl821x,clkout-disable;
-		};
-	};
-};
-
-&eqos {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_eqos>;
-	phy-mode = "rgmii-id";
-	phy-handle = <&ethphy1>;
-	status = "okay";
-
-	mdio {
-		compatible = "snps,dwmac-mdio";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clock-frequency = <5000000>;
-
-		ethphy1: ethernet-phy@1 {
-			compatible = "ethernet-phy-ieee802.3-c22";
-			reg = <1>;
-			eee-broken-1000t;
-			rtl821x,aldps-disable;
-			rtl821x,clkout-disable;
-		};
-	};
-};
-
-&flexspi {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_flexspi>;
-	status = "disabled";
-
-	flash0: flash@0 {
-		reg = <0>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <80000000>;
-		spi-tx-bus-width = <1>;
-		spi-rx-bus-width = <1>;
-	};
-};
-
 &iomuxc {
-	pinctrl-names = "default";
-	status = "okay";
-
-	pinctrl_flexcan2: flexcan2grp {
-		fsl,pins = <
-			MX93_PAD_GPIO_IO25__CAN2_TX	0x139e
-			MX93_PAD_GPIO_IO27__CAN2_RX	0x139e
-		>;
-	};
-
-	pinctrl_flexspi: flexspigrp {
+	pinctrl_lpi2c2: lpi2c2grp {
 		fsl,pins = <
-			MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B	0x42
-			MX93_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B	0x42
-			MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK	0x42
-			MX93_PAD_SD1_STROBE__FLEXSPI1_A_DQS	0x42
-			MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00	0x42
-			MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01	0x42
-			MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02	0x42
-			MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03	0x42
-			MX93_PAD_SD1_DATA4__FLEXSPI1_A_DATA04	0x42
-			MX93_PAD_SD1_DATA5__FLEXSPI1_A_DATA05	0x42
-			MX93_PAD_SD1_DATA6__FLEXSPI1_A_DATA06	0x42
-			MX93_PAD_SD1_DATA7__FLEXSPI1_A_DATA07	0x42
+			MX93_PAD_I2C2_SCL__LPI2C2_SCL			0x40000b9e
+			MX93_PAD_I2C2_SDA__LPI2C2_SDA			0x40000b9e
 		>;
 	};
 
-	pinctrl_fec: fecgrp {
+	pinctrl_pcal6524: pcal6524grp {
 		fsl,pins = <
-			MX93_PAD_ENET2_MDC__ENET1_MDC			0x57e
-			MX93_PAD_ENET2_MDIO__ENET1_MDIO			0x57e
-			MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0		0x57e
-			MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1		0x57e
-			MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2		0x57e
-			MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3		0x57e
-			MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC		0x5fe
-			MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL	0x57e
-			MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0		0x57e
-			MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1		0x57e
-			MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2		0x57e
-			MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3		0x57e
-			MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC		0x5fe
-			MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL	0x57e
+			MX93_PAD_CCM_CLKO2__GPIO3_IO27			0x31e
 		>;
 	};
 
@@ -447,23 +254,22 @@
 		>;
 	};
 
-	pinctrl_lpi2c1: lpi2c1grp {
-		fsl,pins = <
-			MX93_PAD_I2C1_SCL__LPI2C1_SCL			0x40000b9e
-			MX93_PAD_I2C1_SDA__LPI2C1_SDA			0x40000b9e
-		>;
-	};
-
-	pinctrl_lpi2c2: lpi2c2grp {
-		fsl,pins = <
-			MX93_PAD_I2C2_SCL__LPI2C2_SCL			0x40000b9e
-			MX93_PAD_I2C2_SDA__LPI2C2_SDA			0x40000b9e
-		>;
-	};
-
-	pinctrl_pcal6524: pcal6524grp {
+	pinctrl_fec: fecgrp {
 		fsl,pins = <
-			MX93_PAD_CCM_CLKO2__GPIO3_IO27			0x31e
+			MX93_PAD_ENET2_MDC__ENET1_MDC			0x57e
+			MX93_PAD_ENET2_MDIO__ENET1_MDIO			0x57e
+			MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0		0x57e
+			MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1		0x57e
+			MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2		0x57e
+			MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3		0x57e
+			MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC		0x5fe
+			MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL	0x57e
+			MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0		0x57e
+			MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1		0x57e
+			MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2		0x57e
+			MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3		0x57e
+			MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC		0x5fe
+			MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL	0x57e
 		>;
 	};
 
@@ -474,54 +280,43 @@
 		>;
 	};
 
-	pinctrl_uart2: uart2grp {
-		fsl,pins = <
-			MX93_PAD_UART2_TXD__LPUART2_TX			0x31e
-			MX93_PAD_UART2_RXD__LPUART2_RX			0x31e
-		>;
-	};
-
 	pinctrl_usdhc1: usdhc1grp {
 		fsl,pins = <
-			MX93_PAD_SD1_CLK__USDHC1_CLK			0x17fe
-			MX93_PAD_SD1_CMD__USDHC1_CMD			0x13fe
-			MX93_PAD_SD1_DATA0__USDHC1_DATA0		0x13fe
-			MX93_PAD_SD1_DATA1__USDHC1_DATA1		0x13fe
-			MX93_PAD_SD1_DATA2__USDHC1_DATA2		0x13fe
-			MX93_PAD_SD1_DATA3__USDHC1_DATA3		0x13fe
-			MX93_PAD_SD1_DATA4__USDHC1_DATA4		0x13fe
-			MX93_PAD_SD1_DATA5__USDHC1_DATA5		0x13fe
-			MX93_PAD_SD1_DATA6__USDHC1_DATA6		0x13fe
-			MX93_PAD_SD1_DATA7__USDHC1_DATA7		0x13fe
-			MX93_PAD_SD1_STROBE__USDHC1_STROBE		0x17fe
+			MX93_PAD_SD1_CLK__USDHC1_CLK		0x15fe
+			MX93_PAD_SD1_CMD__USDHC1_CMD		0x13fe
+			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x13fe
+			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x13fe
+			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x13fe
+			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x13fe
+			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x13fe
+			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x13fe
+			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x13fe
+			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x13fe
+			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x15fe
 		>;
 	};
 
 	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
 		fsl,pins = <
-			MX93_PAD_SD2_RESET_B__GPIO3_IO07		0x31e
+			MX93_PAD_SD2_RESET_B__GPIO3_IO07	0x31e
 		>;
 	};
 
 	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
 		fsl,pins = <
-			MX93_PAD_SD2_CD_B__GPIO3_IO00			0x31e
+			MX93_PAD_SD2_CD_B__GPIO3_IO00		0x31e
 		>;
 	};
 
 	pinctrl_usdhc2: usdhc2grp {
 		fsl,pins = <
-			MX93_PAD_SD2_CLK__USDHC2_CLK			0x17fe
-			MX93_PAD_SD2_CMD__USDHC2_CMD			0x13fe
-			MX93_PAD_SD2_DATA0__USDHC2_DATA0		0x13fe
-			MX93_PAD_SD2_DATA1__USDHC2_DATA1		0x13fe
-			MX93_PAD_SD2_DATA2__USDHC2_DATA2		0x13fe
-			MX93_PAD_SD2_DATA3__USDHC2_DATA3		0x13fe
-			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT		0x51e
+			MX93_PAD_SD2_CLK__USDHC2_CLK		0x15fe
+			MX93_PAD_SD2_CMD__USDHC2_CMD		0x13fe
+			MX93_PAD_SD2_DATA0__USDHC2_DATA0	0x13fe
+			MX93_PAD_SD2_DATA1__USDHC2_DATA1	0x13fe
+			MX93_PAD_SD2_DATA2__USDHC2_DATA2	0x13fe
+			MX93_PAD_SD2_DATA3__USDHC2_DATA3	0x13fe
+			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e
 		>;
 	};
 };
-
-&wdog3 {
-	status = "okay";
-};
diff --git a/arch/arm/dts/imx93-pinfunc.h b/arch/arm/dts/imx93-pinfunc.h
index 7f0136c..4298a14 100644
--- a/arch/arm/dts/imx93-pinfunc.h
+++ b/arch/arm/dts/imx93-pinfunc.h
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
 /*
  * Copyright 2022 NXP
  */
@@ -10,57 +10,57 @@
  * The pin function ID is a tuple of
  * <mux_reg conf_reg input_reg mux_mode input_val>
  */
-#define MX93_PAD_DAP_TDI__JTAG_MUX_TDI                            0x0000 0x01B0 0x03E0 0x0 0x0
+#define MX93_PAD_DAP_TDI__JTAG_MUX_TDI                            0x0000 0x01B0 0x03D8 0x0 0x0
 #define MX93_PAD_DAP_TDI__MQS2_LEFT                               0x0000 0x01B0 0x0000 0x1 0x0
 #define MX93_PAD_DAP_TDI__CAN2_TX                                 0x0000 0x01B0 0x0000 0x3 0x0
 #define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30                        0x0000 0x01B0 0x0000 0x4 0x0
-#define MX93_PAD_DAP_TDI__GPIO3_IO28                              0x0000 0x01B0 0x03CC 0x5 0x0
-#define MX93_PAD_DAP_TDI__LPUART5_RX                              0x0000 0x01B0 0x0438 0x6 0x0
-#define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS                      0x0004 0x01B4 0x03E4 0x0 0x0
+#define MX93_PAD_DAP_TDI__GPIO3_IO28                              0x0000 0x01B0 0x0000 0x5 0x0
+#define MX93_PAD_DAP_TDI__LPUART5_RX                              0x0000 0x01B0 0x0430 0x6 0x0
+#define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS                      0x0004 0x01B4 0x03DC 0x0 0x0
 #define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31                  0x0004 0x01B4 0x0000 0x4 0x0
-#define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29                        0x0004 0x01B4 0x03D0 0x5 0x0
+#define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29                        0x0004 0x01B4 0x0000 0x5 0x0
 #define MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B                     0x0004 0x01B4 0x0000 0x6 0x0
-#define MX93_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK                     0x0008 0x01B8 0x03DC 0x0 0x0
+#define MX93_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK                     0x0008 0x01B8 0x03D4 0x0 0x0
 #define MX93_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30                 0x0008 0x01B8 0x0000 0x4 0x0
 #define MX93_PAD_DAP_TCLK_SWCLK__GPIO3_IO30                       0x0008 0x01B8 0x0000 0x5 0x0
-#define MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B                    0x0008 0x01B8 0x0434 0x6 0x0
+#define MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B                    0x0008 0x01B8 0x042C 0x6 0x0
 #define MX93_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO                   0x000C 0x01BC 0x0000 0x0 0x0
 #define MX93_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT                     0x000C 0x01BC 0x0000 0x1 0x0
 #define MX93_PAD_DAP_TDO_TRACESWO__CAN2_RX                        0x000C 0x01BC 0x0364 0x3 0x0
 #define MX93_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31               0x000C 0x01BC 0x0000 0x4 0x0
 #define MX93_PAD_DAP_TDO_TRACESWO__GPIO3_IO31                     0x000C 0x01BC 0x0000 0x5 0x0
-#define MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX                     0x000C 0x01BC 0x043C 0x6 0x0
+#define MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX                     0x000C 0x01BC 0x0434 0x6 0x0
 #define MX93_PAD_GPIO_IO00__GPIO2_IO00                            0x0010 0x01C0 0x0000 0x0 0x0
-#define MX93_PAD_GPIO_IO00__LPI2C3_SDA                            0x0010 0x01C0 0x03EC 0x1 0x0
+#define MX93_PAD_GPIO_IO00__LPI2C3_SDA                            0x0010 0x01C0 0x03E4 0x11 0x0
 #define MX93_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK                      0x0010 0x01C0 0x0000 0x2 0x0
 #define MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK                     0x0010 0x01C0 0x0000 0x3 0x0
 #define MX93_PAD_GPIO_IO00__LPSPI6_PCS0                           0x0010 0x01C0 0x0000 0x4 0x0
-#define MX93_PAD_GPIO_IO00__LPUART5_TX                            0x0010 0x01C0 0x043C 0x5 0x1
-#define MX93_PAD_GPIO_IO00__LPI2C5_SDA                            0x0010 0x01C0 0x03F4 0x6 0x0
+#define MX93_PAD_GPIO_IO00__LPUART5_TX                            0x0010 0x01C0 0x0434 0x5 0x1
+#define MX93_PAD_GPIO_IO00__LPI2C5_SDA                            0x0010 0x01C0 0x03EC 0x16 0x0
 #define MX93_PAD_GPIO_IO00__FLEXIO1_FLEXIO00                      0x0010 0x01C0 0x036C 0x7 0x0
 #define MX93_PAD_GPIO_IO01__GPIO2_IO01                            0x0014 0x01C4 0x0000 0x0 0x0
-#define MX93_PAD_GPIO_IO01__LPI2C3_SCL                            0x0014 0x01C4 0x03E8 0x1 0x0
+#define MX93_PAD_GPIO_IO01__LPI2C3_SCL                            0x0014 0x01C4 0x03E0 0x11 0x0
 #define MX93_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA00                   0x0014 0x01C4 0x0000 0x2 0x0
 #define MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE                      0x0014 0x01C4 0x0000 0x3 0x0
 #define MX93_PAD_GPIO_IO01__LPSPI6_SIN                            0x0014 0x01C4 0x0000 0x4 0x0
-#define MX93_PAD_GPIO_IO01__LPUART5_RX                            0x0014 0x01C4 0x0438 0x5 0x1
-#define MX93_PAD_GPIO_IO01__LPI2C5_SCL                            0x0014 0x01C4 0x03F0 0x6 0x0
+#define MX93_PAD_GPIO_IO01__LPUART5_RX                            0x0014 0x01C4 0x0430 0x5 0x1
+#define MX93_PAD_GPIO_IO01__LPI2C5_SCL                            0x0014 0x01C4 0x03E8 0x16 0x0
 #define MX93_PAD_GPIO_IO01__FLEXIO1_FLEXIO01                      0x0014 0x01C4 0x0370 0x7 0x0
 #define MX93_PAD_GPIO_IO02__GPIO2_IO02                            0x0018 0x01C8 0x0000 0x0 0x0
-#define MX93_PAD_GPIO_IO02__LPI2C4_SDA                            0x0018 0x01C8 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO02__LPI2C4_SDA                            0x0018 0x01C8 0x0000 0x11 0x0
 #define MX93_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC                    0x0018 0x01C8 0x0000 0x2 0x0
 #define MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC                   0x0018 0x01C8 0x0000 0x3 0x0
 #define MX93_PAD_GPIO_IO02__LPSPI6_SOUT                           0x0018 0x01C8 0x0000 0x4 0x0
-#define MX93_PAD_GPIO_IO02__LPUART5_CTS_B                         0x0018 0x01C8 0x0434 0x5 0x1
-#define MX93_PAD_GPIO_IO02__LPI2C6_SDA                            0x0018 0x01C8 0x03FC 0x6 0x0
+#define MX93_PAD_GPIO_IO02__LPUART5_CTS_B                         0x0018 0x01C8 0x042C 0x5 0x1
+#define MX93_PAD_GPIO_IO02__LPI2C6_SDA                            0x0018 0x01C8 0x03F4 0x16 0x0
 #define MX93_PAD_GPIO_IO02__FLEXIO1_FLEXIO02                      0x0018 0x01C8 0x0374 0x7 0x0
 #define MX93_PAD_GPIO_IO03__GPIO2_IO03                            0x001C 0x01CC 0x0000 0x0 0x0
-#define MX93_PAD_GPIO_IO03__LPI2C4_SCL                            0x001C 0x01CC 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO03__LPI2C4_SCL                            0x001C 0x01CC 0x0000 0x11 0x0
 #define MX93_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC                    0x001C 0x01CC 0x0000 0x2 0x0
 #define MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC                   0x001C 0x01CC 0x0000 0x3 0x0
 #define MX93_PAD_GPIO_IO03__LPSPI6_SCK                            0x001C 0x01CC 0x0000 0x4 0x0
 #define MX93_PAD_GPIO_IO03__LPUART5_RTS_B                         0x001C 0x01CC 0x0000 0x5 0x0
-#define MX93_PAD_GPIO_IO03__LPI2C6_SCL                            0x001C 0x01CC 0x03F8 0x6 0x0
+#define MX93_PAD_GPIO_IO03__LPI2C6_SCL                            0x001C 0x01CC 0x03F0 0x16 0x0
 #define MX93_PAD_GPIO_IO03__FLEXIO1_FLEXIO03                      0x001C 0x01CC 0x0378 0x7 0x0
 #define MX93_PAD_GPIO_IO04__GPIO2_IO04                            0x0020 0x01D0 0x0000 0x0 0x0
 #define MX93_PAD_GPIO_IO04__TPM3_CH0                              0x0020 0x01D0 0x0000 0x1 0x0
@@ -68,23 +68,23 @@
 #define MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00                  0x0020 0x01D0 0x0000 0x3 0x0
 #define MX93_PAD_GPIO_IO04__LPSPI7_PCS0                           0x0020 0x01D0 0x0000 0x4 0x0
 #define MX93_PAD_GPIO_IO04__LPUART6_TX                            0x0020 0x01D0 0x0000 0x5 0x0
-#define MX93_PAD_GPIO_IO04__LPI2C6_SDA                            0x0020 0x01D0 0x03FC 0x6 0x1
+#define MX93_PAD_GPIO_IO04__LPI2C6_SDA                            0x0020 0x01D0 0x03F4 0x16 0x1
 #define MX93_PAD_GPIO_IO04__FLEXIO1_FLEXIO04                      0x0020 0x01D0 0x037C 0x7 0x0
 #define MX93_PAD_GPIO_IO05__GPIO2_IO05                            0x0024 0x01D4 0x0000 0x0 0x0
 #define MX93_PAD_GPIO_IO05__TPM4_CH0                              0x0024 0x01D4 0x0000 0x1 0x0
-#define MX93_PAD_GPIO_IO05__PDM_BIT_STREAM00                      0x0024 0x01D4 0x0440 0x2 0x0
+#define MX93_PAD_GPIO_IO05__PDM_BIT_STREAM00                      0x0024 0x01D4 0x0438 0x2 0x0
 #define MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01                  0x0024 0x01D4 0x0000 0x3 0x0
 #define MX93_PAD_GPIO_IO05__LPSPI7_SIN                            0x0024 0x01D4 0x0000 0x4 0x0
 #define MX93_PAD_GPIO_IO05__LPUART6_RX                            0x0024 0x01D4 0x0000 0x5 0x0
-#define MX93_PAD_GPIO_IO05__LPI2C6_SCL                            0x0024 0x01D4 0x03F8 0x6 0x1
+#define MX93_PAD_GPIO_IO05__LPI2C6_SCL                            0x0024 0x01D4 0x03F0 0x16 0x1
 #define MX93_PAD_GPIO_IO05__FLEXIO1_FLEXIO05                      0x0024 0x01D4 0x0380 0x7 0x0
 #define MX93_PAD_GPIO_IO06__GPIO2_IO06                            0x0028 0x01D8 0x0000 0x0 0x0
 #define MX93_PAD_GPIO_IO06__TPM5_CH0                              0x0028 0x01D8 0x0000 0x1 0x0
-#define MX93_PAD_GPIO_IO06__PDM_BIT_STREAM01                      0x0028 0x01D8 0x0444 0x2 0x0
+#define MX93_PAD_GPIO_IO06__PDM_BIT_STREAM01                      0x0028 0x01D8 0x043C 0x2 0x0
 #define MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02                  0x0028 0x01D8 0x0000 0x3 0x0
 #define MX93_PAD_GPIO_IO06__LPSPI7_SOUT                           0x0028 0x01D8 0x0000 0x4 0x0
 #define MX93_PAD_GPIO_IO06__LPUART6_CTS_B                         0x0028 0x01D8 0x0000 0x5 0x0
-#define MX93_PAD_GPIO_IO06__LPI2C7_SDA                            0x0028 0x01D8 0x0404 0x6 0x0
+#define MX93_PAD_GPIO_IO06__LPI2C7_SDA                            0x0028 0x01D8 0x03FC 0x16 0x0
 #define MX93_PAD_GPIO_IO06__FLEXIO1_FLEXIO06                      0x0028 0x01D8 0x0384 0x7 0x0
 #define MX93_PAD_GPIO_IO07__GPIO2_IO07                            0x002C 0x01DC 0x0000 0x0 0x0
 #define MX93_PAD_GPIO_IO07__LPSPI3_PCS1                           0x002C 0x01DC 0x0000 0x1 0x0
@@ -92,7 +92,7 @@
 #define MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03                  0x002C 0x01DC 0x0000 0x3 0x0
 #define MX93_PAD_GPIO_IO07__LPSPI7_SCK                            0x002C 0x01DC 0x0000 0x4 0x0
 #define MX93_PAD_GPIO_IO07__LPUART6_RTS_B                         0x002C 0x01DC 0x0000 0x5 0x0
-#define MX93_PAD_GPIO_IO07__LPI2C7_SCL                            0x002C 0x01DC 0x0400 0x6 0x0
+#define MX93_PAD_GPIO_IO07__LPI2C7_SCL                            0x002C 0x01DC 0x03F8 0x16 0x0
 #define MX93_PAD_GPIO_IO07__FLEXIO1_FLEXIO07                      0x002C 0x01DC 0x0388 0x7 0x0
 #define MX93_PAD_GPIO_IO08__GPIO2_IO08                            0x0030 0x01E0 0x0000 0x0 0x0
 #define MX93_PAD_GPIO_IO08__LPSPI3_PCS0                           0x0030 0x01E0 0x0000 0x1 0x0
@@ -100,7 +100,7 @@
 #define MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04                  0x0030 0x01E0 0x0000 0x3 0x0
 #define MX93_PAD_GPIO_IO08__TPM6_CH0                              0x0030 0x01E0 0x0000 0x4 0x0
 #define MX93_PAD_GPIO_IO08__LPUART7_TX                            0x0030 0x01E0 0x0000 0x5 0x0
-#define MX93_PAD_GPIO_IO08__LPI2C7_SDA                            0x0030 0x01E0 0x0404 0x6 0x1
+#define MX93_PAD_GPIO_IO08__LPI2C7_SDA                            0x0030 0x01E0 0x03FC 0x16 0x1
 #define MX93_PAD_GPIO_IO08__FLEXIO1_FLEXIO08                      0x0030 0x01E0 0x038C 0x7 0x0
 #define MX93_PAD_GPIO_IO09__GPIO2_IO09                            0x0034 0x01E4 0x0000 0x0 0x0
 #define MX93_PAD_GPIO_IO09__LPSPI3_SIN                            0x0034 0x01E4 0x0000 0x1 0x0
@@ -108,7 +108,7 @@
 #define MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05                  0x0034 0x01E4 0x0000 0x3 0x0
 #define MX93_PAD_GPIO_IO09__TPM3_EXTCLK                           0x0034 0x01E4 0x0000 0x4 0x0
 #define MX93_PAD_GPIO_IO09__LPUART7_RX                            0x0034 0x01E4 0x0000 0x5 0x0
-#define MX93_PAD_GPIO_IO09__LPI2C7_SCL                            0x0034 0x01E4 0x0400 0x6 0x1
+#define MX93_PAD_GPIO_IO09__LPI2C7_SCL                            0x0034 0x01E4 0x03F8 0x16 0x1
 #define MX93_PAD_GPIO_IO09__FLEXIO1_FLEXIO09                      0x0034 0x01E4 0x0390 0x7 0x0
 #define MX93_PAD_GPIO_IO10__GPIO2_IO10                            0x0038 0x01E8 0x0000 0x0 0x0
 #define MX93_PAD_GPIO_IO10__LPSPI3_SOUT                           0x0038 0x01E8 0x0000 0x1 0x0
@@ -116,7 +116,7 @@
 #define MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06                  0x0038 0x01E8 0x0000 0x3 0x0
 #define MX93_PAD_GPIO_IO10__TPM4_EXTCLK                           0x0038 0x01E8 0x0000 0x4 0x0
 #define MX93_PAD_GPIO_IO10__LPUART7_CTS_B                         0x0038 0x01E8 0x0000 0x5 0x0
-#define MX93_PAD_GPIO_IO10__LPI2C8_SDA                            0x0038 0x01E8 0x040C 0x6 0x0
+#define MX93_PAD_GPIO_IO10__LPI2C8_SDA                            0x0038 0x01E8 0x0404 0x16 0x0
 #define MX93_PAD_GPIO_IO10__FLEXIO1_FLEXIO10                      0x0038 0x01E8 0x0394 0x7 0x0
 #define MX93_PAD_GPIO_IO11__GPIO2_IO11                            0x003C 0x01EC 0x0000 0x0 0x0
 #define MX93_PAD_GPIO_IO11__LPSPI3_SCK                            0x003C 0x01EC 0x0000 0x1 0x0
@@ -124,47 +124,47 @@
 #define MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07                  0x003C 0x01EC 0x0000 0x3 0x0
 #define MX93_PAD_GPIO_IO11__TPM5_EXTCLK                           0x003C 0x01EC 0x0000 0x4 0x0
 #define MX93_PAD_GPIO_IO11__LPUART7_RTS_B                         0x003C 0x01EC 0x0000 0x5 0x0
-#define MX93_PAD_GPIO_IO11__LPI2C8_SCL                            0x003C 0x01EC 0x0408 0x6 0x0
+#define MX93_PAD_GPIO_IO11__LPI2C8_SCL                            0x003C 0x01EC 0x0400 0x16 0x0
 #define MX93_PAD_GPIO_IO11__FLEXIO1_FLEXIO11                      0x003C 0x01EC 0x0398 0x7 0x0
 #define MX93_PAD_GPIO_IO12__GPIO2_IO12                            0x0040 0x01F0 0x0000 0x0 0x0
 #define MX93_PAD_GPIO_IO12__TPM3_CH2                              0x0040 0x01F0 0x0000 0x1 0x0
-#define MX93_PAD_GPIO_IO12__PDM_BIT_STREAM02                      0x0040 0x01F0 0x0448 0x2 0x0
+#define MX93_PAD_GPIO_IO12__PDM_BIT_STREAM02                      0x0040 0x01F0 0x0440 0x2 0x0
 #define MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08                  0x0040 0x01F0 0x0000 0x3 0x0
 #define MX93_PAD_GPIO_IO12__LPSPI8_PCS0                           0x0040 0x01F0 0x0000 0x4 0x0
 #define MX93_PAD_GPIO_IO12__LPUART8_TX                            0x0040 0x01F0 0x0000 0x5 0x0
-#define MX93_PAD_GPIO_IO12__LPI2C8_SDA                            0x0040 0x01F0 0x040C 0x6 0x1
-#define MX93_PAD_GPIO_IO12__SAI3_RX_SYNC                          0x0040 0x01F0 0x0458 0x7 0x0
+#define MX93_PAD_GPIO_IO12__LPI2C8_SDA                            0x0040 0x01F0 0x0404 0x16 0x1
+#define MX93_PAD_GPIO_IO12__SAI3_RX_SYNC                          0x0040 0x01F0 0x0450 0x7 0x0
 #define MX93_PAD_GPIO_IO13__GPIO2_IO13                            0x0044 0x01F4 0x0000 0x0 0x0
 #define MX93_PAD_GPIO_IO13__TPM4_CH2                              0x0044 0x01F4 0x0000 0x1 0x0
-#define MX93_PAD_GPIO_IO13__PDM_BIT_STREAM03                      0x0044 0x01F4 0x044C 0x2 0x0
+#define MX93_PAD_GPIO_IO13__PDM_BIT_STREAM03                      0x0044 0x01F4 0x0444 0x2 0x0
 #define MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09                  0x0044 0x01F4 0x0000 0x3 0x0
 #define MX93_PAD_GPIO_IO13__LPSPI8_SIN                            0x0044 0x01F4 0x0000 0x4 0x0
 #define MX93_PAD_GPIO_IO13__LPUART8_RX                            0x0044 0x01F4 0x0000 0x5 0x0
-#define MX93_PAD_GPIO_IO13__LPI2C8_SCL                            0x0044 0x01F4 0x0408 0x6 0x1
+#define MX93_PAD_GPIO_IO13__LPI2C8_SCL                            0x0044 0x01F4 0x0400 0x16 0x1
 #define MX93_PAD_GPIO_IO13__FLEXIO1_FLEXIO13                      0x0044 0x01F4 0x039C 0x7 0x0
 #define MX93_PAD_GPIO_IO14__GPIO2_IO14                            0x0048 0x01F8 0x0000 0x0 0x0
-#define MX93_PAD_GPIO_IO14__LPUART3_TX                            0x0048 0x01F8 0x0424 0x1 0x0
+#define MX93_PAD_GPIO_IO14__LPUART3_TX                            0x0048 0x01F8 0x041C 0x1 0x0
 #define MX93_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA06                   0x0048 0x01F8 0x0000 0x2 0x0
 #define MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10                  0x0048 0x01F8 0x0000 0x3 0x0
 #define MX93_PAD_GPIO_IO14__LPSPI8_SOUT                           0x0048 0x01F8 0x0000 0x4 0x0
 #define MX93_PAD_GPIO_IO14__LPUART8_CTS_B                         0x0048 0x01F8 0x0000 0x5 0x0
-#define MX93_PAD_GPIO_IO14__LPUART4_TX                            0x0048 0x01F8 0x0430 0x6 0x0
+#define MX93_PAD_GPIO_IO14__LPUART4_TX                            0x0048 0x01F8 0x0428 0x6 0x0
 #define MX93_PAD_GPIO_IO14__FLEXIO1_FLEXIO14                      0x0048 0x01F8 0x03A0 0x7 0x0
 #define MX93_PAD_GPIO_IO15__GPIO2_IO15                            0x004C 0x01FC 0x0000 0x0 0x0
-#define MX93_PAD_GPIO_IO15__LPUART3_RX                            0x004C 0x01FC 0x0420 0x1 0x0
+#define MX93_PAD_GPIO_IO15__LPUART3_RX                            0x004C 0x01FC 0x0418 0x1 0x0
 #define MX93_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA07                   0x004C 0x01FC 0x0000 0x2 0x0
 #define MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11                  0x004C 0x01FC 0x0000 0x3 0x0
 #define MX93_PAD_GPIO_IO15__LPSPI8_SCK                            0x004C 0x01FC 0x0000 0x4 0x0
 #define MX93_PAD_GPIO_IO15__LPUART8_RTS_B                         0x004C 0x01FC 0x0000 0x5 0x0
-#define MX93_PAD_GPIO_IO15__LPUART4_RX                            0x004C 0x01FC 0x042C 0x6 0x0
+#define MX93_PAD_GPIO_IO15__LPUART4_RX                            0x004C 0x01FC 0x0424 0x6 0x0
 #define MX93_PAD_GPIO_IO15__FLEXIO1_FLEXIO15                      0x004C 0x01FC 0x03A4 0x7 0x0
 #define MX93_PAD_GPIO_IO16__GPIO2_IO16                            0x0050 0x0200 0x0000 0x0 0x0
 #define MX93_PAD_GPIO_IO16__SAI3_TX_BCLK                          0x0050 0x0200 0x0000 0x1 0x0
-#define MX93_PAD_GPIO_IO16__PDM_BIT_STREAM02                      0x0050 0x0200 0x0448 0x2 0x1
+#define MX93_PAD_GPIO_IO16__PDM_BIT_STREAM02                      0x0050 0x0200 0x0440 0x2 0x1
 #define MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12                  0x0050 0x0200 0x0000 0x3 0x0
-#define MX93_PAD_GPIO_IO16__LPUART3_CTS_B                         0x0050 0x0200 0x041C 0x4 0x0
+#define MX93_PAD_GPIO_IO16__LPUART3_CTS_B                         0x0050 0x0200 0x0414 0x4 0x0
 #define MX93_PAD_GPIO_IO16__LPSPI4_PCS2                           0x0050 0x0200 0x0000 0x5 0x0
-#define MX93_PAD_GPIO_IO16__LPUART4_CTS_B                         0x0050 0x0200 0x0428 0x6 0x0
+#define MX93_PAD_GPIO_IO16__LPUART4_CTS_B                         0x0050 0x0200 0x0420 0x6 0x0
 #define MX93_PAD_GPIO_IO16__FLEXIO1_FLEXIO16                      0x0050 0x0200 0x03A8 0x7 0x0
 #define MX93_PAD_GPIO_IO17__GPIO2_IO17                            0x0054 0x0204 0x0000 0x0 0x0
 #define MX93_PAD_GPIO_IO17__SAI3_MCLK                             0x0054 0x0204 0x0000 0x1 0x0
@@ -175,7 +175,7 @@
 #define MX93_PAD_GPIO_IO17__LPUART4_RTS_B                         0x0054 0x0204 0x0000 0x6 0x0
 #define MX93_PAD_GPIO_IO17__FLEXIO1_FLEXIO17                      0x0054 0x0204 0x03AC 0x7 0x0
 #define MX93_PAD_GPIO_IO18__GPIO2_IO18                            0x0058 0x0208 0x0000 0x0 0x0
-#define MX93_PAD_GPIO_IO18__SAI3_RX_BCLK                          0x0058 0x0208 0x0454 0x1 0x0
+#define MX93_PAD_GPIO_IO18__SAI3_RX_BCLK                          0x0058 0x0208 0x044C 0x1 0x0
 #define MX93_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA09                   0x0058 0x0208 0x0000 0x2 0x0
 #define MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14                  0x0058 0x0208 0x0000 0x3 0x0
 #define MX93_PAD_GPIO_IO18__LPSPI5_PCS0                           0x0058 0x0208 0x0000 0x4 0x0
@@ -183,8 +183,8 @@
 #define MX93_PAD_GPIO_IO18__TPM5_CH2                              0x0058 0x0208 0x0000 0x6 0x0
 #define MX93_PAD_GPIO_IO18__FLEXIO1_FLEXIO18                      0x0058 0x0208 0x03B0 0x7 0x0
 #define MX93_PAD_GPIO_IO19__GPIO2_IO19                            0x005C 0x020C 0x0000 0x0 0x0
-#define MX93_PAD_GPIO_IO19__SAI3_RX_SYNC                          0x005C 0x020C 0x0458 0x1 0x1
-#define MX93_PAD_GPIO_IO19__PDM_BIT_STREAM03                      0x005C 0x020C 0x044C 0x2 0x1
+#define MX93_PAD_GPIO_IO19__SAI3_RX_SYNC                          0x005C 0x020C 0x0450 0x1 0x1
+#define MX93_PAD_GPIO_IO19__PDM_BIT_STREAM03                      0x005C 0x020C 0x0444 0x2 0x1
 #define MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15                  0x005C 0x020C 0x0000 0x3 0x0
 #define MX93_PAD_GPIO_IO19__LPSPI5_SIN                            0x005C 0x020C 0x0000 0x4 0x0
 #define MX93_PAD_GPIO_IO19__LPSPI4_SIN                            0x005C 0x020C 0x0000 0x5 0x0
@@ -192,7 +192,7 @@
 #define MX93_PAD_GPIO_IO19__SAI3_TX_DATA00                        0x005C 0x020C 0x0000 0x7 0x0
 #define MX93_PAD_GPIO_IO20__GPIO2_IO20                            0x0060 0x0210 0x0000 0x0 0x0
 #define MX93_PAD_GPIO_IO20__SAI3_RX_DATA00                        0x0060 0x0210 0x0000 0x1 0x0
-#define MX93_PAD_GPIO_IO20__PDM_BIT_STREAM00                      0x0060 0x0210 0x0440 0x2 0x1
+#define MX93_PAD_GPIO_IO20__PDM_BIT_STREAM00                      0x0060 0x0210 0x0438 0x2 0x1
 #define MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16                  0x0060 0x0210 0x0000 0x3 0x0
 #define MX93_PAD_GPIO_IO20__LPSPI5_SOUT                           0x0060 0x0210 0x0000 0x4 0x0
 #define MX93_PAD_GPIO_IO20__LPSPI4_SOUT                           0x0060 0x0210 0x0000 0x5 0x0
@@ -205,58 +205,58 @@
 #define MX93_PAD_GPIO_IO21__LPSPI5_SCK                            0x0064 0x0214 0x0000 0x4 0x0
 #define MX93_PAD_GPIO_IO21__LPSPI4_SCK                            0x0064 0x0214 0x0000 0x5 0x0
 #define MX93_PAD_GPIO_IO21__TPM4_CH1                              0x0064 0x0214 0x0000 0x6 0x0
-#define MX93_PAD_GPIO_IO21__SAI3_RX_BCLK                          0x0064 0x0214 0x0454 0x7 0x1
+#define MX93_PAD_GPIO_IO21__SAI3_RX_BCLK                          0x0064 0x0214 0x044C 0x7 0x1
 #define MX93_PAD_GPIO_IO22__GPIO2_IO22                            0x0068 0x0218 0x0000 0x0 0x0
-#define MX93_PAD_GPIO_IO22__USDHC3_CLK                            0x0068 0x0218 0x0460 0x1 0x0
-#define MX93_PAD_GPIO_IO22__SPDIF_IN                              0x0068 0x0218 0x045C 0x2 0x0
+#define MX93_PAD_GPIO_IO22__USDHC3_CLK                            0x0068 0x0218 0x0458 0x1 0x0
+#define MX93_PAD_GPIO_IO22__SPDIF_IN                              0x0068 0x0218 0x0454 0x2 0x0
 #define MX93_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18                  0x0068 0x0218 0x0000 0x3 0x0
 #define MX93_PAD_GPIO_IO22__TPM5_CH1                              0x0068 0x0218 0x0000 0x4 0x0
 #define MX93_PAD_GPIO_IO22__TPM6_EXTCLK                           0x0068 0x0218 0x0000 0x5 0x0
-#define MX93_PAD_GPIO_IO22__LPI2C5_SDA                            0x0068 0x0218 0x03F4 0x6 0x1
+#define MX93_PAD_GPIO_IO22__LPI2C5_SDA                            0x0068 0x0218 0x03EC 0x16 0x1
 #define MX93_PAD_GPIO_IO22__FLEXIO1_FLEXIO22                      0x0068 0x0218 0x03B8 0x7 0x0
 #define MX93_PAD_GPIO_IO23__GPIO2_IO23                            0x006C 0x021C 0x0000 0x0 0x0
-#define MX93_PAD_GPIO_IO23__USDHC3_CMD                            0x006C 0x021C 0x0464 0x1 0x0
+#define MX93_PAD_GPIO_IO23__USDHC3_CMD                            0x006C 0x021C 0x045C 0x1 0x0
 #define MX93_PAD_GPIO_IO23__SPDIF_OUT                             0x006C 0x021C 0x0000 0x2 0x0
 #define MX93_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19                  0x006C 0x021C 0x0000 0x3 0x0
 #define MX93_PAD_GPIO_IO23__TPM6_CH1                              0x006C 0x021C 0x0000 0x4 0x0
-#define MX93_PAD_GPIO_IO23__LPI2C5_SCL                            0x006C 0x021C 0x03F0 0x6 0x1
+#define MX93_PAD_GPIO_IO23__LPI2C5_SCL                            0x006C 0x021C 0x03E8 0x16 0x1
 #define MX93_PAD_GPIO_IO23__FLEXIO1_FLEXIO23                      0x006C 0x021C 0x03BC 0x7 0x0
 #define MX93_PAD_GPIO_IO24__GPIO2_IO24                            0x0070 0x0220 0x0000 0x0 0x0
-#define MX93_PAD_GPIO_IO24__USDHC3_DATA0                          0x0070 0x0220 0x0468 0x1 0x0
+#define MX93_PAD_GPIO_IO24__USDHC3_DATA0                          0x0070 0x0220 0x0460 0x1 0x0
 #define MX93_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20                  0x0070 0x0220 0x0000 0x3 0x0
 #define MX93_PAD_GPIO_IO24__TPM3_CH3                              0x0070 0x0220 0x0000 0x4 0x0
 #define MX93_PAD_GPIO_IO24__JTAG_MUX_TDO                          0x0070 0x0220 0x0000 0x5 0x0
 #define MX93_PAD_GPIO_IO24__LPSPI6_PCS1                           0x0070 0x0220 0x0000 0x6 0x0
 #define MX93_PAD_GPIO_IO24__FLEXIO1_FLEXIO24                      0x0070 0x0220 0x03C0 0x7 0x0
 #define MX93_PAD_GPIO_IO25__GPIO2_IO25                            0x0074 0x0224 0x0000 0x0 0x0
-#define MX93_PAD_GPIO_IO25__USDHC3_DATA1                          0x0074 0x0224 0x046C 0x1 0x0
+#define MX93_PAD_GPIO_IO25__USDHC3_DATA1                          0x0074 0x0224 0x0464 0x1 0x0
 #define MX93_PAD_GPIO_IO25__CAN2_TX                               0x0074 0x0224 0x0000 0x2 0x0
 #define MX93_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21                  0x0074 0x0224 0x0000 0x3 0x0
 #define MX93_PAD_GPIO_IO25__TPM4_CH3                              0x0074 0x0224 0x0000 0x4 0x0
-#define MX93_PAD_GPIO_IO25__JTAG_MUX_TCK                          0x0074 0x0224 0x03DC 0x5 0x1
+#define MX93_PAD_GPIO_IO25__JTAG_MUX_TCK                          0x0074 0x0224 0x03D4 0x5 0x1
 #define MX93_PAD_GPIO_IO25__LPSPI7_PCS1                           0x0074 0x0224 0x0000 0x6 0x0
 #define MX93_PAD_GPIO_IO25__FLEXIO1_FLEXIO25                      0x0074 0x0224 0x03C4 0x7 0x0
 #define MX93_PAD_GPIO_IO26__GPIO2_IO26                            0x0078 0x0228 0x0000 0x0 0x0
-#define MX93_PAD_GPIO_IO26__USDHC3_DATA2                          0x0078 0x0228 0x0470 0x1 0x0
-#define MX93_PAD_GPIO_IO26__PDM_BIT_STREAM01                      0x0078 0x0228 0x0444 0x2 0x1
+#define MX93_PAD_GPIO_IO26__USDHC3_DATA2                          0x0078 0x0228 0x0468 0x1 0x0
+#define MX93_PAD_GPIO_IO26__PDM_BIT_STREAM01                      0x0078 0x0228 0x043C 0x2 0x1
 #define MX93_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22                  0x0078 0x0228 0x0000 0x3 0x0
 #define MX93_PAD_GPIO_IO26__TPM5_CH3                              0x0078 0x0228 0x0000 0x4 0x0
-#define MX93_PAD_GPIO_IO26__JTAG_MUX_TDI                          0x0078 0x0228 0x03E0 0x5 0x1
+#define MX93_PAD_GPIO_IO26__JTAG_MUX_TDI                          0x0078 0x0228 0x03D8 0x5 0x1
 #define MX93_PAD_GPIO_IO26__LPSPI8_PCS1                           0x0078 0x0228 0x0000 0x6 0x0
 #define MX93_PAD_GPIO_IO26__SAI3_TX_SYNC                          0x0078 0x0228 0x0000 0x7 0x0
 #define MX93_PAD_GPIO_IO27__GPIO2_IO27                            0x007C 0x022C 0x0000 0x0 0x0
-#define MX93_PAD_GPIO_IO27__USDHC3_DATA3                          0x007C 0x022C 0x0474 0x1 0x0
+#define MX93_PAD_GPIO_IO27__USDHC3_DATA3                          0x007C 0x022C 0x046C 0x1 0x0
 #define MX93_PAD_GPIO_IO27__CAN2_RX                               0x007C 0x022C 0x0364 0x2 0x1
 #define MX93_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23                  0x007C 0x022C 0x0000 0x3 0x0
 #define MX93_PAD_GPIO_IO27__TPM6_CH3                              0x007C 0x022C 0x0000 0x4 0x0
-#define MX93_PAD_GPIO_IO27__JTAG_MUX_TMS                          0x007C 0x022C 0x03E4 0x5 0x1
+#define MX93_PAD_GPIO_IO27__JTAG_MUX_TMS                          0x007C 0x022C 0x03DC 0x5 0x1
 #define MX93_PAD_GPIO_IO27__LPSPI5_PCS1                           0x007C 0x022C 0x0000 0x6 0x0
 #define MX93_PAD_GPIO_IO27__FLEXIO1_FLEXIO27                      0x007C 0x022C 0x03C8 0x7 0x0
 #define MX93_PAD_GPIO_IO28__GPIO2_IO28                            0x0080 0x0230 0x0000 0x0 0x0
-#define MX93_PAD_GPIO_IO28__LPI2C3_SDA                            0x0080 0x0230 0x03EC 0x1 0x1
+#define MX93_PAD_GPIO_IO28__LPI2C3_SDA                            0x0080 0x0230 0x03E4 0x11 0x1
 #define MX93_PAD_GPIO_IO28__FLEXIO1_FLEXIO28                      0x0080 0x0230 0x0000 0x7 0x0
 #define MX93_PAD_GPIO_IO29__GPIO2_IO29                            0x0084 0x0234 0x0000 0x0 0x0
-#define MX93_PAD_GPIO_IO29__LPI2C3_SCL                            0x0084 0x0234 0x03E8 0x1 0x1
+#define MX93_PAD_GPIO_IO29__LPI2C3_SCL                            0x0084 0x0234 0x03E0 0x11 0x1
 #define MX93_PAD_GPIO_IO29__FLEXIO1_FLEXIO29                      0x0084 0x0234 0x0000 0x7 0x0
 #define MX93_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1                    0x0088 0x0238 0x0000 0x0 0x0
 #define MX93_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26                      0x0088 0x0238 0x0000 0x4 0x0
@@ -266,20 +266,19 @@
 #define MX93_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27                      0x008C 0x023C 0x03C8 0x4 0x1
 #define MX93_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3                    0x0090 0x0240 0x0000 0x0 0x0
 #define MX93_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28                      0x0090 0x0240 0x0000 0x4 0x0
-#define MX93_PAD_CCM_CLKO3__GPIO3_IO28                            0x0090 0x0240 0x03CC 0x5 0x1
+#define MX93_PAD_CCM_CLKO3__GPIO4_IO28                            0x0090 0x0240 0x0000 0x5 0x0
 #define MX93_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4                    0x0094 0x0244 0x0000 0x0 0x0
 #define MX93_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29                      0x0094 0x0244 0x0000 0x4 0x0
-#define MX93_PAD_CCM_CLKO4__GPIO3_IO29                            0x0094 0x0244 0x03D0 0x5 0x1
+#define MX93_PAD_CCM_CLKO4__GPIO4_IO29                            0x0094 0x0244 0x0000 0x5 0x0
 #define MX93_PAD_ENET1_MDC__ENET_QOS_MDC                          0x0098 0x0248 0x0000 0x0 0x0
 #define MX93_PAD_ENET1_MDC__LPUART3_DCB_B                         0x0098 0x0248 0x0000 0x1 0x0
-#define MX93_PAD_ENET1_MDC__I3C2_SCL                              0x0098 0x0248 0x03D4 0x2 0x0
+#define MX93_PAD_ENET1_MDC__I3C2_SCL                              0x0098 0x0248 0x03CC 0x2 0x0
 #define MX93_PAD_ENET1_MDC__HSIOMIX_OTG_ID1                       0x0098 0x0248 0x0000 0x3 0x0
 #define MX93_PAD_ENET1_MDC__FLEXIO2_FLEXIO00                      0x0098 0x0248 0x0000 0x4 0x0
 #define MX93_PAD_ENET1_MDC__GPIO4_IO00                            0x0098 0x0248 0x0000 0x5 0x0
-#define MX93_PAD_ENET1_MDC__LPUART5_RTS_B                         0x0098 0x0248 0x0000 0x6 0x0
 #define MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO                        0x009C 0x024C 0x0000 0x0 0x0
 #define MX93_PAD_ENET1_MDIO__LPUART3_RIN_B                        0x009C 0x024C 0x0000 0x1 0x0
-#define MX93_PAD_ENET1_MDIO__I3C2_SDA                             0x009C 0x024C 0x03D8 0x2 0x0
+#define MX93_PAD_ENET1_MDIO__I3C2_SDA                             0x009C 0x024C 0x03D0 0x2 0x0
 #define MX93_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1                     0x009C 0x024C 0x0000 0x3 0x0
 #define MX93_PAD_ENET1_MDIO__FLEXIO2_FLEXIO01                     0x009C 0x024C 0x0000 0x4 0x0
 #define MX93_PAD_ENET1_MDIO__GPIO4_IO01                           0x009C 0x024C 0x0000 0x5 0x0
@@ -302,7 +301,7 @@
 #define MX93_PAD_ENET1_TD1__GPIO4_IO04                            0x00A8 0x0258 0x0000 0x5 0x0
 #define MX93_PAD_ENET1_TD1__I3C2_PUR_B                            0x00A8 0x0258 0x0000 0x6 0x0
 #define MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0                    0x00AC 0x025C 0x0000 0x0 0x0
-#define MX93_PAD_ENET1_TD0__LPUART3_TX                            0x00AC 0x025C 0x0424 0x1 0x1
+#define MX93_PAD_ENET1_TD0__LPUART3_TX                            0x00AC 0x025C 0x041C 0x1 0x1
 #define MX93_PAD_ENET1_TD0__FLEXIO2_FLEXIO05                      0x00AC 0x025C 0x0000 0x4 0x0
 #define MX93_PAD_ENET1_TD0__GPIO4_IO05                            0x00AC 0x025C 0x0000 0x5 0x0
 #define MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL              0x00B0 0x0260 0x0000 0x0 0x0
@@ -323,21 +322,21 @@
 #define MX93_PAD_ENET1_RXC__FLEXIO2_FLEXIO09                      0x00BC 0x026C 0x0000 0x4 0x0
 #define MX93_PAD_ENET1_RXC__GPIO4_IO09                            0x00BC 0x026C 0x0000 0x5 0x0
 #define MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0                    0x00C0 0x0270 0x0000 0x0 0x0
-#define MX93_PAD_ENET1_RD0__LPUART3_RX                            0x00C0 0x0270 0x0420 0x1 0x1
+#define MX93_PAD_ENET1_RD0__LPUART3_RX                            0x00C0 0x0270 0x0418 0x1 0x1
 #define MX93_PAD_ENET1_RD0__FLEXIO2_FLEXIO10                      0x00C0 0x0270 0x0000 0x4 0x0
 #define MX93_PAD_ENET1_RD0__GPIO4_IO10                            0x00C0 0x0270 0x0000 0x5 0x0
 #define MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1                    0x00C4 0x0274 0x0000 0x0 0x0
-#define MX93_PAD_ENET1_RD1__LPUART3_CTS_B                         0x00C4 0x0274 0x041C 0x1 0x1
-#define MX93_PAD_ENET1_RD1__LPTMR2_ALT1                           0x00C4 0x0274 0x0410 0x3 0x0
+#define MX93_PAD_ENET1_RD1__LPUART3_CTS_B                         0x00C4 0x0274 0x0414 0x1 0x1
+#define MX93_PAD_ENET1_RD1__LPTMR2_ALT1                           0x00C4 0x0274 0x0408 0x3 0x0
 #define MX93_PAD_ENET1_RD1__FLEXIO2_FLEXIO11                      0x00C4 0x0274 0x0000 0x4 0x0
 #define MX93_PAD_ENET1_RD1__GPIO4_IO11                            0x00C4 0x0274 0x0000 0x5 0x0
 #define MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2                    0x00C8 0x0278 0x0000 0x0 0x0
-#define MX93_PAD_ENET1_RD2__LPTMR2_ALT2                           0x00C8 0x0278 0x0414 0x3 0x0
+#define MX93_PAD_ENET1_RD2__LPTMR2_ALT2                           0x00C8 0x0278 0x040C 0x3 0x0
 #define MX93_PAD_ENET1_RD2__FLEXIO2_FLEXIO12                      0x00C8 0x0278 0x0000 0x4 0x0
 #define MX93_PAD_ENET1_RD2__GPIO4_IO12                            0x00C8 0x0278 0x0000 0x5 0x0
 #define MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3                    0x00CC 0x027C 0x0000 0x0 0x0
 #define MX93_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER               0x00CC 0x027C 0x0000 0x2 0x0
-#define MX93_PAD_ENET1_RD3__LPTMR2_ALT3                           0x00CC 0x027C 0x0418 0x3 0x0
+#define MX93_PAD_ENET1_RD3__LPTMR2_ALT3                           0x00CC 0x027C 0x0410 0x3 0x0
 #define MX93_PAD_ENET1_RD3__FLEXIO2_FLEXIO13                      0x00CC 0x027C 0x0000 0x4 0x0
 #define MX93_PAD_ENET1_RD3__GPIO4_IO13                            0x00CC 0x027C 0x0000 0x5 0x0
 #define MX93_PAD_ENET2_MDC__ENET1_MDC                             0x00D0 0x0280 0x0000 0x0 0x0
@@ -365,7 +364,7 @@
 #define MX93_PAD_ENET2_TD1__FLEXIO2_FLEXIO18                      0x00E0 0x0290 0x0000 0x4 0x0
 #define MX93_PAD_ENET2_TD1__GPIO4_IO18                            0x00E0 0x0290 0x0000 0x5 0x0
 #define MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0                       0x00E4 0x0294 0x0000 0x0 0x0
-#define MX93_PAD_ENET2_TD0__LPUART4_TX                            0x00E4 0x0294 0x0430 0x1 0x1
+#define MX93_PAD_ENET2_TD0__LPUART4_TX                            0x00E4 0x0294 0x0428 0x1 0x1
 #define MX93_PAD_ENET2_TD0__SAI2_RX_DATA03                        0x00E4 0x0294 0x0000 0x2 0x0
 #define MX93_PAD_ENET2_TD0__FLEXIO2_FLEXIO19                      0x00E4 0x0294 0x0000 0x4 0x0
 #define MX93_PAD_ENET2_TD0__GPIO4_IO19                            0x00E4 0x0294 0x0000 0x5 0x0
@@ -390,24 +389,24 @@
 #define MX93_PAD_ENET2_RXC__FLEXIO2_FLEXIO23                      0x00F4 0x02A4 0x0000 0x4 0x0
 #define MX93_PAD_ENET2_RXC__GPIO4_IO23                            0x00F4 0x02A4 0x0000 0x5 0x0
 #define MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0                       0x00F8 0x02A8 0x0000 0x0 0x0
-#define MX93_PAD_ENET2_RD0__LPUART4_RX                            0x00F8 0x02A8 0x042C 0x1 0x1
+#define MX93_PAD_ENET2_RD0__LPUART4_RX                            0x00F8 0x02A8 0x0424 0x1 0x1
 #define MX93_PAD_ENET2_RD0__SAI2_TX_DATA02                        0x00F8 0x02A8 0x0000 0x2 0x0
 #define MX93_PAD_ENET2_RD0__FLEXIO2_FLEXIO24                      0x00F8 0x02A8 0x0000 0x4 0x0
 #define MX93_PAD_ENET2_RD0__GPIO4_IO24                            0x00F8 0x02A8 0x0000 0x5 0x0
 #define MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1                       0x00FC 0x02AC 0x0000 0x0 0x0
-#define MX93_PAD_ENET2_RD1__SPDIF_IN                              0x00FC 0x02AC 0x045C 0x1 0x1
+#define MX93_PAD_ENET2_RD1__SPDIF_IN                              0x00FC 0x02AC 0x0454 0x1 0x1
 #define MX93_PAD_ENET2_RD1__SAI2_TX_DATA03                        0x00FC 0x02AC 0x0000 0x2 0x0
 #define MX93_PAD_ENET2_RD1__FLEXIO2_FLEXIO25                      0x00FC 0x02AC 0x0000 0x4 0x0
 #define MX93_PAD_ENET2_RD1__GPIO4_IO25                            0x00FC 0x02AC 0x0000 0x5 0x0
 #define MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2                       0x0100 0x02B0 0x0000 0x0 0x0
-#define MX93_PAD_ENET2_RD2__LPUART4_CTS_B                         0x0100 0x02B0 0x0428 0x1 0x1
+#define MX93_PAD_ENET2_RD2__LPUART4_CTS_B                         0x0100 0x02B0 0x0420 0x1 0x1
 #define MX93_PAD_ENET2_RD2__SAI2_MCLK                             0x0100 0x02B0 0x0000 0x2 0x0
 #define MX93_PAD_ENET2_RD2__MQS2_RIGHT                            0x0100 0x02B0 0x0000 0x3 0x0
 #define MX93_PAD_ENET2_RD2__FLEXIO2_FLEXIO26                      0x0100 0x02B0 0x0000 0x4 0x0
 #define MX93_PAD_ENET2_RD2__GPIO4_IO26                            0x0100 0x02B0 0x0000 0x5 0x0
 #define MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3                       0x0104 0x02B4 0x0000 0x0 0x0
 #define MX93_PAD_ENET2_RD3__SPDIF_OUT                             0x0104 0x02B4 0x0000 0x1 0x0
-#define MX93_PAD_ENET2_RD3__SPDIF_IN                              0x0104 0x02B4 0x045C 0x2 0x2
+#define MX93_PAD_ENET2_RD3__SPDIF_IN                              0x0104 0x02B4 0x0454 0x2 0x2
 #define MX93_PAD_ENET2_RD3__MQS2_LEFT                             0x0104 0x02B4 0x0000 0x3 0x0
 #define MX93_PAD_ENET2_RD3__FLEXIO2_FLEXIO27                      0x0104 0x02B4 0x0000 0x4 0x0
 #define MX93_PAD_ENET2_RD3__GPIO4_IO27                            0x0104 0x02B4 0x0000 0x5 0x0
@@ -457,43 +456,42 @@
 #define MX93_PAD_SD1_STROBE__GPIO3_IO18                           0x0130 0x02E0 0x0000 0x5 0x0
 #define MX93_PAD_SD2_VSELECT__USDHC2_VSELECT                      0x0134 0x02E4 0x0000 0x0 0x0
 #define MX93_PAD_SD2_VSELECT__USDHC2_WP                           0x0134 0x02E4 0x0000 0x1 0x0
-#define MX93_PAD_SD2_VSELECT__LPTMR2_ALT3                         0x0134 0x02E4 0x0418 0x2 0x1
+#define MX93_PAD_SD2_VSELECT__LPTMR2_ALT3                         0x0134 0x02E4 0x0410 0x2 0x1
 #define MX93_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19                    0x0134 0x02E4 0x0000 0x4 0x0
 #define MX93_PAD_SD2_VSELECT__GPIO3_IO19                          0x0134 0x02E4 0x0000 0x5 0x0
 #define MX93_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1               0x0134 0x02E4 0x0368 0x6 0x0
-#define MX93_PAD_SD3_CLK__USDHC3_CLK                              0x0138 0x02E8 0x0460 0x0 0x1
+#define MX93_PAD_SD3_CLK__USDHC3_CLK                              0x0138 0x02E8 0x0458 0x0 0x1
 #define MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK                         0x0138 0x02E8 0x0000 0x1 0x0
 #define MX93_PAD_SD3_CLK__FLEXIO1_FLEXIO20                        0x0138 0x02E8 0x03B4 0x4 0x1
 #define MX93_PAD_SD3_CLK__GPIO3_IO20                              0x0138 0x02E8 0x0000 0x5 0x0
-#define MX93_PAD_SD3_CMD__USDHC3_CMD                              0x013C 0x02EC 0x0464 0x0 0x1
+#define MX93_PAD_SD3_CMD__USDHC3_CMD                              0x013C 0x02EC 0x045C 0x0 0x1
 #define MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B                        0x013C 0x02EC 0x0000 0x1 0x0
 #define MX93_PAD_SD3_CMD__FLEXIO1_FLEXIO21                        0x013C 0x02EC 0x0000 0x4 0x0
 #define MX93_PAD_SD3_CMD__GPIO3_IO21                              0x013C 0x02EC 0x0000 0x5 0x0
-#define MX93_PAD_SD3_DATA0__USDHC3_DATA0                          0x0140 0x02F0 0x0468 0x0 0x1
+#define MX93_PAD_SD3_DATA0__USDHC3_DATA0                          0x0140 0x02F0 0x0460 0x0 0x1
 #define MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00                     0x0140 0x02F0 0x0000 0x1 0x0
 #define MX93_PAD_SD3_DATA0__FLEXIO1_FLEXIO22                      0x0140 0x02F0 0x03B8 0x4 0x1
 #define MX93_PAD_SD3_DATA0__GPIO3_IO22                            0x0140 0x02F0 0x0000 0x5 0x0
-#define MX93_PAD_SD3_DATA1__USDHC3_DATA1                          0x0144 0x02F4 0x046C 0x0 0x1
+#define MX93_PAD_SD3_DATA1__USDHC3_DATA1                          0x0144 0x02F4 0x0464 0x0 0x1
 #define MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01                     0x0144 0x02F4 0x0000 0x1 0x0
 #define MX93_PAD_SD3_DATA1__FLEXIO1_FLEXIO23                      0x0144 0x02F4 0x03BC 0x4 0x1
 #define MX93_PAD_SD3_DATA1__GPIO3_IO23                            0x0144 0x02F4 0x0000 0x5 0x0
-#define MX93_PAD_SD3_DATA2__USDHC3_DATA2                          0x0148 0x02F8 0x0470 0x0 0x1
+#define MX93_PAD_SD3_DATA2__USDHC3_DATA2                          0x0148 0x02F8 0x0468 0x0 0x1
 #define MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02                     0x0148 0x02F8 0x0000 0x1 0x0
 #define MX93_PAD_SD3_DATA2__FLEXIO1_FLEXIO24                      0x0148 0x02F8 0x03C0 0x4 0x1
 #define MX93_PAD_SD3_DATA2__GPIO3_IO24                            0x0148 0x02F8 0x0000 0x5 0x0
-#define MX93_PAD_SD3_DATA3__USDHC3_DATA3                          0x014C 0x02FC 0x0474 0x0 0x1
+#define MX93_PAD_SD3_DATA3__USDHC3_DATA3                          0x014C 0x02FC 0x046C 0x0 0x1
 #define MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03                     0x014C 0x02FC 0x0000 0x1 0x0
 #define MX93_PAD_SD3_DATA3__FLEXIO1_FLEXIO25                      0x014C 0x02FC 0x03C4 0x4 0x1
 #define MX93_PAD_SD3_DATA3__GPIO3_IO25                            0x014C 0x02FC 0x0000 0x5 0x0
 #define MX93_PAD_SD2_CD_B__USDHC2_CD_B                            0x0150 0x0300 0x0000 0x0 0x0
 #define MX93_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN                0x0150 0x0300 0x0000 0x1 0x0
-#define MX93_PAD_SD2_CD_B__I3C2_SCL                               0x0150 0x0300 0x03D4 0x2 0x1
+#define MX93_PAD_SD2_CD_B__I3C2_SCL                               0x0150 0x0300 0x03CC 0x2 0x1
 #define MX93_PAD_SD2_CD_B__FLEXIO1_FLEXIO00                       0x0150 0x0300 0x036C 0x4 0x1
 #define MX93_PAD_SD2_CD_B__GPIO3_IO00                             0x0150 0x0300 0x0000 0x5 0x0
-#define MX93_PAD_SD2_CD_B__CCMSRCGPCMIX_TESTER_ACK                0x0150 0x0300 0x0000 0x6 0x0
 #define MX93_PAD_SD2_CLK__USDHC2_CLK                              0x0154 0x0304 0x0000 0x0 0x0
 #define MX93_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT                0x0154 0x0304 0x0000 0x1 0x0
-#define MX93_PAD_SD2_CLK__I3C2_SDA                                0x0154 0x0304 0x03D8 0x2 0x1
+#define MX93_PAD_SD2_CLK__I3C2_SDA                                0x0154 0x0304 0x03D0 0x2 0x1
 #define MX93_PAD_SD2_CLK__FLEXIO1_FLEXIO01                        0x0154 0x0304 0x0370 0x4 0x1
 #define MX93_PAD_SD2_CLK__GPIO3_IO01                              0x0154 0x0304 0x0000 0x5 0x0
 #define MX93_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0                   0x0154 0x0304 0x0000 0x6 0x0
@@ -523,34 +521,34 @@
 #define MX93_PAD_SD2_DATA2__GPIO3_IO05                            0x0164 0x0314 0x0000 0x5 0x0
 #define MX93_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP                     0x0164 0x0314 0x0000 0x6 0x0
 #define MX93_PAD_SD2_DATA3__USDHC2_DATA3                          0x0168 0x0318 0x0000 0x0 0x0
-#define MX93_PAD_SD2_DATA3__LPTMR2_ALT1                           0x0168 0x0318 0x0410 0x1 0x1
+#define MX93_PAD_SD2_DATA3__LPTMR2_ALT1                           0x0168 0x0318 0x0408 0x1 0x1
 #define MX93_PAD_SD2_DATA3__MQS2_LEFT                             0x0168 0x0318 0x0000 0x2 0x0
 #define MX93_PAD_SD2_DATA3__FLEXIO1_FLEXIO06                      0x0168 0x0318 0x0384 0x4 0x1
 #define MX93_PAD_SD2_DATA3__GPIO3_IO06                            0x0168 0x0318 0x0000 0x5 0x0
 #define MX93_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET              0x0168 0x0318 0x0000 0x6 0x0
 #define MX93_PAD_SD2_RESET_B__USDHC2_RESET_B                      0x016C 0x031C 0x0000 0x0 0x0
-#define MX93_PAD_SD2_RESET_B__LPTMR2_ALT2                         0x016C 0x031C 0x0414 0x1 0x1
+#define MX93_PAD_SD2_RESET_B__LPTMR2_ALT2                         0x016C 0x031C 0x040C 0x1 0x1
 #define MX93_PAD_SD2_RESET_B__FLEXIO1_FLEXIO07                    0x016C 0x031C 0x0388 0x4 0x1
 #define MX93_PAD_SD2_RESET_B__GPIO3_IO07                          0x016C 0x031C 0x0000 0x5 0x0
 #define MX93_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET           0x016C 0x031C 0x0000 0x6 0x0
-#define MX93_PAD_I2C1_SCL__LPI2C1_SCL                             0x0170 0x0320 0x0000 0x0 0x0
+#define MX93_PAD_I2C1_SCL__LPI2C1_SCL                             0x0170 0x0320 0x0000 0x10 0x0
 #define MX93_PAD_I2C1_SCL__I3C1_SCL                               0x0170 0x0320 0x0000 0x1 0x0
 #define MX93_PAD_I2C1_SCL__LPUART1_DCB_B                          0x0170 0x0320 0x0000 0x2 0x0
 #define MX93_PAD_I2C1_SCL__TPM2_CH0                               0x0170 0x0320 0x0000 0x3 0x0
 #define MX93_PAD_I2C1_SCL__GPIO1_IO00                             0x0170 0x0320 0x0000 0x5 0x0
-#define MX93_PAD_I2C1_SDA__LPI2C1_SDA                             0x0174 0x0324 0x0000 0x0 0x0
+#define MX93_PAD_I2C1_SDA__LPI2C1_SDA                             0x0174 0x0324 0x0000 0x10 0x0
 #define MX93_PAD_I2C1_SDA__I3C1_SDA                               0x0174 0x0324 0x0000 0x1 0x0
 #define MX93_PAD_I2C1_SDA__LPUART1_RIN_B                          0x0174 0x0324 0x0000 0x2 0x0
 #define MX93_PAD_I2C1_SDA__TPM2_CH1                               0x0174 0x0324 0x0000 0x3 0x0
 #define MX93_PAD_I2C1_SDA__GPIO1_IO01                             0x0174 0x0324 0x0000 0x5 0x0
-#define MX93_PAD_I2C2_SCL__LPI2C2_SCL                             0x0178 0x0328 0x0000 0x0 0x0
+#define MX93_PAD_I2C2_SCL__LPI2C2_SCL                             0x0178 0x0328 0x0000 0x10 0x0
 #define MX93_PAD_I2C2_SCL__I3C1_PUR                               0x0178 0x0328 0x0000 0x1 0x0
 #define MX93_PAD_I2C2_SCL__LPUART2_DCB_B                          0x0178 0x0328 0x0000 0x2 0x0
 #define MX93_PAD_I2C2_SCL__TPM2_CH2                               0x0178 0x0328 0x0000 0x3 0x0
 #define MX93_PAD_I2C2_SCL__SAI1_RX_SYNC                           0x0178 0x0328 0x0000 0x4 0x0
 #define MX93_PAD_I2C2_SCL__GPIO1_IO02                             0x0178 0x0328 0x0000 0x5 0x0
 #define MX93_PAD_I2C2_SCL__I3C1_PUR_B                             0x0178 0x0328 0x0000 0x6 0x0
-#define MX93_PAD_I2C2_SDA__LPI2C2_SDA                             0x017C 0x032C 0x0000 0x0 0x0
+#define MX93_PAD_I2C2_SDA__LPI2C2_SDA                             0x017C 0x032C 0x0000 0x10 0x0
 #define MX93_PAD_I2C2_SDA__LPUART2_RIN_B                          0x017C 0x032C 0x0000 0x2 0x0
 #define MX93_PAD_I2C2_SDA__TPM2_CH3                               0x017C 0x032C 0x0000 0x3 0x0
 #define MX93_PAD_I2C2_SDA__SAI1_RX_BCLK                           0x017C 0x032C 0x0000 0x4 0x0
@@ -569,7 +567,7 @@
 #define MX93_PAD_UART2_RXD__LPUART1_CTS_B                         0x0188 0x0338 0x0000 0x1 0x0
 #define MX93_PAD_UART2_RXD__LPSPI2_SOUT                           0x0188 0x0338 0x0000 0x2 0x0
 #define MX93_PAD_UART2_RXD__TPM1_CH2                              0x0188 0x0338 0x0000 0x3 0x0
-#define MX93_PAD_UART2_RXD__SAI1_MCLK                             0x0188 0x0338 0x0450 0x4 0x0
+#define MX93_PAD_UART2_RXD__SAI1_MCLK                             0x0188 0x0338 0x0448 0x4 0x0
 #define MX93_PAD_UART2_RXD__GPIO1_IO06                            0x0188 0x0338 0x0000 0x5 0x0
 #define MX93_PAD_UART2_TXD__LPUART2_TX                            0x018C 0x033C 0x0000 0x0 0x0
 #define MX93_PAD_UART2_TXD__LPUART1_RTS_B                         0x018C 0x033C 0x0000 0x1 0x0
@@ -581,14 +579,14 @@
 #define MX93_PAD_PDM_CLK__LPTMR1_ALT1                             0x0190 0x0340 0x0000 0x4 0x0
 #define MX93_PAD_PDM_CLK__GPIO1_IO08                              0x0190 0x0340 0x0000 0x5 0x0
 #define MX93_PAD_PDM_CLK__CAN1_TX                                 0x0190 0x0340 0x0000 0x6 0x0
-#define MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00                0x0194 0x0344 0x0440 0x0 0x2
+#define MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00                0x0194 0x0344 0x0438 0x0 0x2
 #define MX93_PAD_PDM_BIT_STREAM0__MQS1_RIGHT                      0x0194 0x0344 0x0000 0x1 0x0
 #define MX93_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1                     0x0194 0x0344 0x0000 0x2 0x0
 #define MX93_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK                     0x0194 0x0344 0x0000 0x3 0x0
 #define MX93_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2                     0x0194 0x0344 0x0000 0x4 0x0
 #define MX93_PAD_PDM_BIT_STREAM0__GPIO1_IO09                      0x0194 0x0344 0x0000 0x5 0x0
 #define MX93_PAD_PDM_BIT_STREAM0__CAN1_RX                         0x0194 0x0344 0x0360 0x6 0x0
-#define MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01                0x0198 0x0348 0x0444 0x0 0x2
+#define MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01                0x0198 0x0348 0x043C 0x0 0x2
 #define MX93_PAD_PDM_BIT_STREAM1__NMI_GLUE_NMI                    0x0198 0x0348 0x0000 0x1 0x0
 #define MX93_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1                     0x0198 0x0348 0x0000 0x2 0x0
 #define MX93_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK                     0x0198 0x0348 0x0000 0x3 0x0
@@ -614,7 +612,7 @@
 #define MX93_PAD_SAI1_TXD0__CAN1_TX                               0x01A4 0x0354 0x0000 0x4 0x0
 #define MX93_PAD_SAI1_TXD0__GPIO1_IO13                            0x01A4 0x0354 0x0000 0x5 0x0
 #define MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00                        0x01A8 0x0358 0x0000 0x0 0x0
-#define MX93_PAD_SAI1_RXD0__SAI1_MCLK                             0x01A8 0x0358 0x0450 0x1 0x1
+#define MX93_PAD_SAI1_RXD0__SAI1_MCLK                             0x01A8 0x0358 0x0448 0x1 0x1
 #define MX93_PAD_SAI1_RXD0__LPSPI1_SOUT                           0x01A8 0x0358 0x0000 0x2 0x0
 #define MX93_PAD_SAI1_RXD0__LPUART2_DSR_B                         0x01A8 0x0358 0x0000 0x3 0x0
 #define MX93_PAD_SAI1_RXD0__MQS1_RIGHT                            0x01A8 0x0358 0x0000 0x4 0x0
diff --git a/arch/arm/dts/imx93.dtsi b/arch/arm/dts/imx93.dtsi
index 28026cc..13cf32d 100644
--- a/arch/arm/dts/imx93.dtsi
+++ b/arch/arm/dts/imx93.dtsi
@@ -1,15 +1,14 @@
 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
- * Copyright 2021 NXP
+ * Copyright 2022 NXP
  */
 
 #include <dt-bindings/clock/imx93-clock.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/fsl,imx93-power.h>
 #include <dt-bindings/thermal/thermal.h>
-#include <dt-bindings/power/imx93-power.h>
-#include <dt-bindings/usb/pd.h>
 
 #include "imx93-pinfunc.h"
 
@@ -23,11 +22,17 @@
 		gpio1 = &gpio2;
 		gpio2 = &gpio3;
 		gpio3 = &gpio4;
+		i2c0 = &lpi2c1;
+		i2c1 = &lpi2c2;
+		i2c2 = &lpi2c3;
+		i2c3 = &lpi2c4;
+		i2c4 = &lpi2c5;
+		i2c5 = &lpi2c6;
+		i2c6 = &lpi2c7;
+		i2c7 = &lpi2c8;
 		mmc0 = &usdhc1;
 		mmc1 = &usdhc2;
 		mmc2 = &usdhc3;
-		ethernet0 = &fec;
-		ethernet1 = &eqos;
 		serial0 = &lpuart1;
 		serial1 = &lpuart2;
 		serial2 = &lpuart3;
@@ -36,14 +41,6 @@
 		serial5 = &lpuart6;
 		serial6 = &lpuart7;
 		serial7 = &lpuart8;
-		i2c0 = &lpi2c1;
-		i2c1 = &lpi2c2;
-		i2c2 = &lpi2c3;
-		i2c3 = &lpi2c4;
-		i2c4 = &lpi2c5;
-		i2c5 = &lpi2c6;
-		usb0 = &usbotg1;
-		usb1 = &usbotg2;
 	};
 
 	cpus {
@@ -89,6 +86,11 @@
 		clock-output-names = "clk_ext1";
 	};
 
+	pmu {
+		compatible = "arm,cortex-a55-pmu";
+		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+	};
+
 	psci {
 		compatible = "arm,psci-1.0";
 		method = "smc";
@@ -115,6 +117,38 @@
 		interrupt-parent = <&gic>;
 	};
 
+	thermal-zones {
+		cpu-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <2000>;
+
+			thermal-sensors = <&tmu 0>;
+
+			trips {
+				cpu_alert: cpu-alert {
+					temperature = <80000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu_crit: cpu-crit {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu_alert>;
+					cooling-device =
+						<&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+	};
+
 	soc@0 {
 		compatible = "simple-bus";
 		#address-cells = <1>;
@@ -129,46 +163,53 @@
 			#size-cells = <1>;
 			ranges;
 
+			anomix_ns_gpr: syscon@44210000 {
+				compatible = "fsl,imx93-aonmix-ns-syscfg", "syscon";
+				reg = <0x44210000 0x1000>;
+			};
+
 			mu1: mailbox@44230000 {
 				compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
 				reg = <0x44230000 0x10000>;
 				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_MU1_B_GATE>;
 				#mbox-cells = <2>;
 				status = "disabled";
 			};
 
-			anomix_ns_gpr: blk-ctrl-anomix@42420000 {
-				compatible = "syscon";
-				reg = <0x44210000 0x1000>;
-			};
-
 			system_counter: timer@44290000 {
 				compatible = "nxp,sysctr-timer";
 				reg = <0x44290000 0x30000>;
 				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&osc_24m>;
 				clock-names = "per";
+				nxp,no-divider;
 			};
 
-			i3c1: i3c-master@44330000 {
-				#address-cells = <3>;
-				#size-cells = <0>;
-				compatible = "fsl,imx93-i3c-master", "silvaco,i3c-master";
-				reg = <0x44330000 0x10000>;
-				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clk IMX93_CLK_I3C1_GATE>,
-					 <&clk IMX93_CLK_I3C1_GATE>,
-					 <&clk IMX93_CLK_DUMMY>;
-				clock-names = "pclk", "fast_clk", "slow_clk";
+			tpm1: pwm@44310000 {
+				compatible = "fsl,imx7ulp-pwm";
+				reg = <0x44310000 0x1000>;
+				clocks = <&clk IMX93_CLK_TPM1_GATE>;
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			tpm2: pwm@44320000 {
+				compatible = "fsl,imx7ulp-pwm";
+				reg = <0x44320000 0x10000>;
+				clocks = <&clk IMX93_CLK_TPM2_GATE>;
+				#pwm-cells = <3>;
 				status = "disabled";
 			};
 
 			lpi2c1: i2c@44340000 {
 				compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
 				reg = <0x44340000 0x10000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX93_CLK_LPI2C1_GATE>,
-					 <&clk IMX93_CLK_LPI2C1_GATE>;
+					 <&clk IMX93_CLK_BUS_AON>;
 				clock-names = "per", "ipg";
 				status = "disabled";
 			};
@@ -176,9 +217,11 @@
 			lpi2c2: i2c@44350000 {
 				compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
 				reg = <0x44350000 0x10000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX93_CLK_LPI2C2_GATE>,
-					 <&clk IMX93_CLK_LPI2C2_GATE>;
+					 <&clk IMX93_CLK_BUS_AON>;
 				clock-names = "per", "ipg";
 				status = "disabled";
 			};
@@ -190,7 +233,7 @@
 				reg = <0x44360000 0x10000>;
 				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX93_CLK_LPSPI1_GATE>,
-					 <&clk IMX93_CLK_LPSPI1_GATE>;
+					 <&clk IMX93_CLK_BUS_AON>;
 				clock-names = "per", "ipg";
 				status = "disabled";
 			};
@@ -202,14 +245,13 @@
 				reg = <0x44370000 0x10000>;
 				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX93_CLK_LPSPI2_GATE>,
-					 <&clk IMX93_CLK_LPSPI2_GATE>;
+					 <&clk IMX93_CLK_BUS_AON>;
 				clock-names = "per", "ipg";
 				status = "disabled";
 			};
 
 			lpuart1: serial@44380000 {
-				compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart",
-					     "fsl,imx7ulp-lpuart";
+				compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
 				reg = <0x44380000 0x1000>;
 				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX93_CLK_LPUART1_GATE>;
@@ -218,8 +260,7 @@
 			};
 
 			lpuart2: serial@44390000 {
-				compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart",
-					     "fsl,imx7ulp-lpuart";
+				compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
 				reg = <0x44390000 0x1000>;
 				interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX93_CLK_LPUART2_GATE>;
@@ -227,9 +268,40 @@
 				status = "disabled";
 			};
 
+			flexcan1: can@443a0000 {
+				compatible = "fsl,imx93-flexcan";
+				reg = <0x443a0000 0x10000>;
+				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_BUS_AON>,
+					 <&clk IMX93_CLK_CAN1_GATE>;
+				clock-names = "ipg", "per";
+				assigned-clocks = <&clk IMX93_CLK_CAN1>;
+				assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
+				assigned-clock-rates = <40000000>;
+				fsl,clk-source = /bits/ 8 <0>;
+				status = "disabled";
+			};
+
 			iomuxc: pinctrl@443c0000 {
 				compatible = "fsl,imx93-iomuxc";
 				reg = <0x443c0000 0x10000>;
+				status = "okay";
+			};
+
+			bbnsm: bbnsm@44440000 {
+				compatible = "nxp,imx93-bbnsm", "syscon", "simple-mfd";
+				reg = <0x44440000 0x10000>;
+
+				bbnsm_rtc: rtc {
+					compatible = "nxp,imx93-bbnsm-rtc";
+					interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+				};
+
+				bbnsm_pwrkey: pwrkey {
+					compatible = "nxp,imx93-bbnsm-pwrkey";
+					interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+					linux,code = <KEY_POWER>;
+				};
 			};
 
 			clk: clock-controller@44450000 {
@@ -238,25 +310,63 @@
 				#clock-cells = <1>;
 				clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>;
 				clock-names = "osc_32k", "osc_24m", "clk_ext1";
-				assigned-clocks = <&clk IMX93_CLK_AUDIO_PLL>;
-				assigned-clock-rates = <393216000>;
 				status = "okay";
 			};
 
+			src: system-controller@44460000 {
+				compatible = "fsl,imx93-src", "syscon";
+				reg = <0x44460000 0x10000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges;
+
+				mediamix: power-domain@44462400 {
+					compatible = "fsl,imx93-src-slice";
+					reg = <0x44462400 0x400>, <0x44465800 0x400>;
+					#power-domain-cells = <0>;
+					clocks = <&clk IMX93_CLK_MEDIA_AXI>,
+						 <&clk IMX93_CLK_MEDIA_APB>;
+				};
+
+				mlmix: power-domain@44461800 {
+					compatible = "fsl,imx93-src-slice";
+					reg = <0x44461800 0x400>, <0x44464800 0x400>;
+					#power-domain-cells = <0>;
+					clocks = <&clk IMX93_CLK_ML_APB>,
+						 <&clk IMX93_CLK_ML>;
+				};
+			};
+
 			anatop: anatop@44480000 {
 				compatible = "fsl,imx93-anatop", "syscon";
 				reg = <0x44480000 0x10000>;
 			};
 
+			tmu: tmu@44482000 {
+				compatible = "fsl,imx93-tmu";
+				reg = <0x44482000 0x1000>;
+				clocks = <&clk IMX93_CLK_TMC_GATE>;
+				little-endian;
+				fsl,tmu-calibration = <0x0000000e 0x800000da
+						       0x00000029 0x800000e9
+						       0x00000056 0x80000102
+						       0x000000a2 0x8000012a
+						       0x00000116 0x80000166
+						       0x00000195 0x800001a7
+						       0x000001b2 0x800001b6>;
+				#thermal-sensor-cells = <1>;
+			};
+
 			adc1: adc@44530000 {
 				compatible = "nxp,imx93-adc";
 				reg = <0x44530000 0x10000>;
 				interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
-						<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
-						<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
-						<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+					     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX93_CLK_ADC1_GATE>;
 				clock-names = "ipg";
+				#io-channel-cells = <1>;
 				status = "disabled";
 			};
 		};
@@ -268,8 +378,8 @@
 			#size-cells = <1>;
 			ranges;
 
-			wakeupmix_gpr: blk-ctrl-wakeupmix@42420000 {
-				compatible = "syscon";
+			wakeupmix_gpr: syscon@42420000 {
+				compatible = "fsl,imx93-wakeupmix-syscfg", "syscon";
 				reg = <0x42420000 0x1000>;
 			};
 
@@ -277,6 +387,7 @@
 				compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
 				reg = <0x42440000 0x10000>;
 				interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_MU2_B_GATE>;
 				#mbox-cells = <2>;
 				status = "disabled";
 			};
@@ -287,39 +398,48 @@
 				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX93_CLK_WDOG3_GATE>;
 				timeout-sec = <40>;
+			};
+
+			tpm3: pwm@424e0000 {
+				compatible = "fsl,imx7ulp-pwm";
+				reg = <0x424e0000 0x1000>;
+				clocks = <&clk IMX93_CLK_TPM3_GATE>;
+				#pwm-cells = <3>;
 				status = "disabled";
 			};
 
 			tpm4: pwm@424f0000 {
 				compatible = "fsl,imx7ulp-pwm";
-				reg = <0x424f0000 0x1000>;
+				reg = <0x424f0000 0x10000>;
 				clocks = <&clk IMX93_CLK_TPM4_GATE>;
-				assigned-clocks = <&clk IMX93_CLK_TPM4>;
-				assigned-clock-parents = <&clk IMX93_CLK_24M>;
-				assigned-clock-rates = <24000000>;
 				#pwm-cells = <3>;
 				status = "disabled";
 			};
 
-			i3c2: i3c-master@42520000 {
-				#address-cells = <3>;
-				#size-cells = <0>;
-				compatible = "fsl,imx93-i3c-master", "silvaco,i3c-master";
-				reg = <0x42520000 0x10000>;
-				interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clk IMX93_CLK_I3C2_GATE>,
-					 <&clk IMX93_CLK_I3C2_GATE>,
-					 <&clk IMX93_CLK_DUMMY>;
-				clock-names = "pclk", "fast_clk", "slow_clk";
+			tpm5: pwm@42500000 {
+				compatible = "fsl,imx7ulp-pwm";
+				reg = <0x42500000 0x10000>;
+				clocks = <&clk IMX93_CLK_TPM5_GATE>;
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			tpm6: pwm@42510000 {
+				compatible = "fsl,imx7ulp-pwm";
+				reg = <0x42510000 0x10000>;
+				clocks = <&clk IMX93_CLK_TPM6_GATE>;
+				#pwm-cells = <3>;
 				status = "disabled";
 			};
 
 			lpi2c3: i2c@42530000 {
 				compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
 				reg = <0x42530000 0x10000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX93_CLK_LPI2C3_GATE>,
-					 <&clk IMX93_CLK_LPI2C3_GATE>;
+					 <&clk IMX93_CLK_BUS_WAKEUP>;
 				clock-names = "per", "ipg";
 				status = "disabled";
 			};
@@ -327,9 +447,11 @@
 			lpi2c4: i2c@42540000 {
 				compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
 				reg = <0x42540000 0x10000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX93_CLK_LPI2C4_GATE>,
-					 <&clk IMX93_CLK_LPI2C4_GATE>;
+					 <&clk IMX93_CLK_BUS_WAKEUP>;
 				clock-names = "per", "ipg";
 				status = "disabled";
 			};
@@ -341,7 +463,7 @@
 				reg = <0x42550000 0x10000>;
 				interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX93_CLK_LPSPI3_GATE>,
-					 <&clk IMX93_CLK_LPSPI3_GATE>;
+					 <&clk IMX93_CLK_BUS_WAKEUP>;
 				clock-names = "per", "ipg";
 				status = "disabled";
 			};
@@ -353,14 +475,13 @@
 				reg = <0x42560000 0x10000>;
 				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX93_CLK_LPSPI4_GATE>,
-					 <&clk IMX93_CLK_LPSPI4_GATE>;
+					 <&clk IMX93_CLK_BUS_WAKEUP>;
 				clock-names = "per", "ipg";
 				status = "disabled";
 			};
 
 			lpuart3: serial@42570000 {
-				compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart",
-					     "fsl,imx7ulp-lpuart";
+				compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
 				reg = <0x42570000 0x1000>;
 				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX93_CLK_LPUART3_GATE>;
@@ -369,8 +490,7 @@
 			};
 
 			lpuart4: serial@42580000 {
-				compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart",
-					     "fsl,imx7ulp-lpuart";
+				compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
 				reg = <0x42580000 0x1000>;
 				interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX93_CLK_LPUART4_GATE>;
@@ -379,8 +499,7 @@
 			};
 
 			lpuart5: serial@42590000 {
-				compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart",
-					     "fsl,imx7ulp-lpuart";
+				compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
 				reg = <0x42590000 0x1000>;
 				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX93_CLK_LPUART5_GATE>;
@@ -389,8 +508,7 @@
 			};
 
 			lpuart6: serial@425a0000 {
-				compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart",
-					     "fsl,imx7ulp-lpuart";
+				compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
 				reg = <0x425a0000 0x1000>;
 				interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX93_CLK_LPUART6_GATE>;
@@ -398,22 +516,37 @@
 				status = "disabled";
 			};
 
-			flexspi: spi@425e0000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
+			flexcan2: can@425b0000 {
+				compatible = "fsl,imx93-flexcan";
+				reg = <0x425b0000 0x10000>;
+				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
+					 <&clk IMX93_CLK_CAN2_GATE>;
+				clock-names = "ipg", "per";
+				assigned-clocks = <&clk IMX93_CLK_CAN2>;
+				assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
+				assigned-clock-rates = <40000000>;
+				fsl,clk-source = /bits/ 8 <0>;
+				status = "disabled";
+			};
+
+			flexspi1: spi@425e0000 {
 				compatible = "nxp,imx8mm-fspi";
 				reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>;
 				reg-names = "fspi_base", "fspi_mmap";
+				#address-cells = <1>;
+				#size-cells = <0>;
 				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clk IMX93_CLK_DUMMY>,
-					 <&clk IMX93_CLK_DUMMY>;
-				clock-names = "fspi", "fspi_en";
+				clocks = <&clk IMX93_CLK_FLEXSPI1_GATE>,
+					 <&clk IMX93_CLK_FLEXSPI1_GATE>;
+				clock-names = "fspi_en", "fspi";
+				assigned-clocks = <&clk IMX93_CLK_FLEXSPI1>;
+				assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>;
 				status = "disabled";
 			};
 
 			lpuart7: serial@42690000 {
-				compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart",
-					     "fsl,imx7ulp-lpuart";
+				compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
 				reg = <0x42690000 0x1000>;
 				interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX93_CLK_LPUART7_GATE>;
@@ -422,8 +555,7 @@
 			};
 
 			lpuart8: serial@426a0000 {
-				compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart",
-					     "fsl,imx7ulp-lpuart";
+				compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
 				reg = <0x426a0000 0x1000>;
 				interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX93_CLK_LPUART8_GATE>;
@@ -434,9 +566,11 @@
 			lpi2c5: i2c@426b0000 {
 				compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
 				reg = <0x426b0000 0x10000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX93_CLK_LPI2C5_GATE>,
-					 <&clk IMX93_CLK_LPI2C5_GATE>;
+					 <&clk IMX93_CLK_BUS_WAKEUP>;
 				clock-names = "per", "ipg";
 				status = "disabled";
 			};
@@ -444,12 +578,87 @@
 			lpi2c6: i2c@426c0000 {
 				compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
 				reg = <0x426c0000 0x10000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX93_CLK_LPI2C6_GATE>,
-					 <&clk IMX93_CLK_LPI2C6_GATE>;
+					 <&clk IMX93_CLK_BUS_WAKEUP>;
 				clock-names = "per", "ipg";
 				status = "disabled";
 			};
+
+			lpi2c7: i2c@426d0000 {
+				compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
+				reg = <0x426d0000 0x10000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_LPI2C7_GATE>,
+					 <&clk IMX93_CLK_BUS_WAKEUP>;
+				clock-names = "per", "ipg";
+				status = "disabled";
+			};
+
+			lpi2c8: i2c@426e0000 {
+				compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
+				reg = <0x426e0000 0x10000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_LPI2C8_GATE>,
+					 <&clk IMX93_CLK_BUS_WAKEUP>;
+				clock-names = "per", "ipg";
+				status = "disabled";
+			};
+
+			lpspi5: spi@426f0000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
+				reg = <0x426f0000 0x10000>;
+				interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_LPSPI5_GATE>,
+					 <&clk IMX93_CLK_BUS_WAKEUP>;
+				clock-names = "per", "ipg";
+				status = "disabled";
+			};
+
+			lpspi6: spi@42700000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
+				reg = <0x42700000 0x10000>;
+				interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_LPSPI6_GATE>,
+					 <&clk IMX93_CLK_BUS_WAKEUP>;
+				clock-names = "per", "ipg";
+				status = "disabled";
+			};
+
+			lpspi7: spi@42710000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
+				reg = <0x42710000 0x10000>;
+				interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_LPSPI7_GATE>,
+					 <&clk IMX93_CLK_BUS_WAKEUP>;
+				clock-names = "per", "ipg";
+				status = "disabled";
+			};
+
+			lpspi8: spi@42720000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
+				reg = <0x42720000 0x10000>;
+				interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_LPSPI8_GATE>,
+					 <&clk IMX93_CLK_BUS_WAKEUP>;
+				clock-names = "per", "ipg";
+				status = "disabled";
+			};
+
 		};
 
 		aips3: bus@42800000 {
@@ -463,8 +672,8 @@
 				compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
 				reg = <0x42850000 0x10000>;
 				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clk IMX93_CLK_DUMMY>,
-					 <&clk IMX93_CLK_DUMMY>,
+				clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
+					 <&clk IMX93_CLK_WAKEUP_AXI>,
 					 <&clk IMX93_CLK_USDHC1_GATE>;
 				clock-names = "ipg", "ahb", "per";
 				bus-width = <8>;
@@ -477,8 +686,8 @@
 				compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
 				reg = <0x42860000 0x10000>;
 				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clk IMX93_CLK_DUMMY>,
-					 <&clk IMX93_CLK_DUMMY>,
+				clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
+					 <&clk IMX93_CLK_WAKEUP_AXI>,
 					 <&clk IMX93_CLK_USDHC2_GATE>;
 				clock-names = "ipg", "ahb", "per";
 				bus-width = <4>;
@@ -487,15 +696,37 @@
 				status = "disabled";
 			};
 
+			eqos: ethernet@428a0000 {
+				compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a";
+				reg = <0x428a0000 0x10000>;
+				interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "macirq", "eth_wake_irq";
+				clocks = <&clk IMX93_CLK_ENET_QOS_GATE>,
+					 <&clk IMX93_CLK_ENET_QOS_GATE>,
+					 <&clk IMX93_CLK_ENET_TIMER2>,
+					 <&clk IMX93_CLK_ENET>,
+					 <&clk IMX93_CLK_ENET_QOS_GATE>;
+				clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";
+				assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>,
+						  <&clk IMX93_CLK_ENET>;
+				assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
+							 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
+				assigned-clock-rates = <100000000>, <250000000>;
+				intf_mode = <&wakeupmix_gpr 0x28>;
+				snps,clk-csr = <0>;
+				status = "disabled";
+			};
+
 			fec: ethernet@42890000 {
-				compatible = "fsl,imx93-fec", "fsl,imx8mp-fec", "fsl,imx8mq-fec";
+				compatible = "fsl,imx93-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
 				reg = <0x42890000 0x10000>;
 				interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clk IMX93_CLK_WAKEUP_AXI>,
-					 <&clk IMX93_CLK_WAKEUP_AXI>,
+				clocks = <&clk IMX93_CLK_ENET1_GATE>,
+					 <&clk IMX93_CLK_ENET1_GATE>,
 					 <&clk IMX93_CLK_ENET_TIMER1>,
 					 <&clk IMX93_CLK_ENET_REF>,
 					 <&clk IMX93_CLK_ENET_REF_PHY>;
@@ -510,29 +741,6 @@
 				assigned-clock-rates = <100000000>, <250000000>, <50000000>;
 				fsl,num-tx-queues = <3>;
 				fsl,num-rx-queues = <3>;
-				fsl,wakeup_irq = <2>;
-				status = "disabled";
-			};
-
-			eqos: ethernet@428a0000 {
-				compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a";
-				reg = <0x428a0000 0x10000>;
-				interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
-				interrupt-names = "eth_wake_irq", "macirq";
-				clocks = <&clk IMX93_CLK_WAKEUP_AXI>,
-					 <&clk IMX93_CLK_WAKEUP_AXI>,
-					 <&clk IMX93_CLK_ENET_TIMER2>,
-					 <&clk IMX93_CLK_ENET>,
-					 <&clk IMX93_CLK_WAKEUP_AXI>;
-				clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";
-				assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>,
-						  <&clk IMX93_CLK_ENET>;
-				assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
-							 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
-				assigned-clock-rates = <100000000>, <250000000>;
-				intf_mode = <&wakeupmix_gpr 0x28>;
-				clk_csr = <0>;
 				status = "disabled";
 			};
 
@@ -540,8 +748,8 @@
 				compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
 				reg = <0x428b0000 0x10000>;
 				interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clk IMX93_CLK_DUMMY>,
-					 <&clk IMX93_CLK_DUMMY>,
+				clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
+					 <&clk IMX93_CLK_WAKEUP_AXI>,
 					 <&clk IMX93_CLK_USDHC3_GATE>;
 				clock-names = "ipg", "ahb", "per";
 				bus-width = <4>;
@@ -551,138 +759,90 @@
 			};
 		};
 
-		gpio2: gpio@43810000 {
-				compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
-				reg = <0x43810080 0x1000>, <0x43810040 0x40>;
-				gpio-controller;
-				#gpio-cells = <2>;
-				interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				gpio-ranges = <&iomuxc 0 32 32>;
+		gpio2: gpio@43810080 {
+			compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
+			reg = <0x43810080 0x1000>, <0x43810040 0x40>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&clk IMX93_CLK_GPIO2_GATE>,
+				 <&clk IMX93_CLK_GPIO2_GATE>;
+			clock-names = "gpio", "port";
+			gpio-ranges = <&iomuxc 0 4 30>;
 		};
 
-		gpio3: gpio@43820000 {
-				compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
-				reg = <0x43820080 0x1000>, <0x43820040 0x40>;
-				gpio-controller;
-				#gpio-cells = <2>;
-				interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				gpio-ranges = <&iomuxc 0 64 32>;
+		gpio3: gpio@43820080 {
+			compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
+			reg = <0x43820080 0x1000>, <0x43820040 0x40>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&clk IMX93_CLK_GPIO3_GATE>,
+				 <&clk IMX93_CLK_GPIO3_GATE>;
+			clock-names = "gpio", "port";
+			gpio-ranges = <&iomuxc 0 84 8>, <&iomuxc 8 66 18>,
+				      <&iomuxc 26 34 2>, <&iomuxc 28 0 4>;
 		};
 
-		gpio4: gpio@43830000 {
-				compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
-				reg = <0x43830080 0x1000>, <0x43830040 0x40>;
-				gpio-controller;
-				#gpio-cells = <2>;
-				interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				gpio-ranges = <&iomuxc 0 96 32>;
+		gpio4: gpio@43830080 {
+			compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
+			reg = <0x43830080 0x1000>, <0x43830040 0x40>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&clk IMX93_CLK_GPIO4_GATE>,
+				 <&clk IMX93_CLK_GPIO4_GATE>;
+			clock-names = "gpio", "port";
+			gpio-ranges = <&iomuxc 0 38 28>, <&iomuxc 28 36 2>;
 		};
 
-		gpio1: gpio@47400000 {
-				compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
-				reg = <0x47400080 0x1000>, <0x47400040 0x40>;
-				gpio-controller;
-				#gpio-cells = <2>;
-				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				gpio-ranges = <&iomuxc 0 0 32>;
+		gpio1: gpio@47400080 {
+			compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
+			reg = <0x47400080 0x1000>, <0x47400040 0x40>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&clk IMX93_CLK_GPIO1_GATE>,
+				 <&clk IMX93_CLK_GPIO1_GATE>;
+			clock-names = "gpio", "port";
+			gpio-ranges = <&iomuxc 0 92 16>;
 		};
 
-		ocotp: efuse@47510000 {
-			#address-cells = <1>;
-			#size-cells = <1>;
-			compatible = "fsl,imx93-ocotp", "syscon";
-			reg = <0x47510000 0x1000>;
-			status = "disabled";
-		};
-
-		s4muap: s4muap@47520000 {
+		s4muap: mailbox@47520000 {
 			compatible = "fsl,imx93-mu-s4";
 			reg = <0x47520000 0x10000>;
 			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "txirq", "rxirq";
+			interrupt-names = "tx", "rx";
 			#mbox-cells = <2>;
-			status = "okay";
-		};
-
-		sentnl_mu: sentnl-mu {
-			#address-cells = <1>;
-			#size-cells = <1>;
-			compatible = "fsl,imx-sentnl";
-			mboxes = <&s4muap 0 0 &s4muap 1 0>;
-			mbox-names = "tx", "rx";
-			fsl,sentnl_mu_id = <2>;
-			fsl,sentnl_mu_max_users = <4>;
-			status = "okay";
-			dma-ranges = <0x80000000 0x80000000 0x20000000>;
-		};
-
-		ddr-pmu@4e300e00 {
-			compatible = "fsl,imx93-ddr-pmu";
-			reg = <0x4e300dc0 0x200>; /* _dc0 ~ _eb8 */
-			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
-		usbphynop1: usbphynop1 {
-			compatible = "usb-nop-xceiv";
-			clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>;
-			clock-names = "main_clk";
-		};
-
-		usbotg1: usb@4c100000 {
-			compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
-			reg = <0x4c100000 0x200>;
-			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>;
-			clock-names = "usb1_ctrl_root_clk";
-			assigned-clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>;
-			assigned-clock-parents = <&clk IMX93_CLK_HSIO>;
-			fsl,usbphy = <&usbphynop1>;
-			fsl,usbmisc = <&usbmisc1 0>;
+		media_blk_ctrl: system-controller@4ac10000 {
+			compatible = "fsl,imx93-media-blk-ctrl", "syscon";
+			reg = <0x4ac10000 0x10000>;
+			power-domains = <&mediamix>;
+			clocks = <&clk IMX93_CLK_MEDIA_APB>,
+				 <&clk IMX93_CLK_MEDIA_AXI>,
+				 <&clk IMX93_CLK_NIC_MEDIA_GATE>,
+				 <&clk IMX93_CLK_MEDIA_DISP_PIX>,
+				 <&clk IMX93_CLK_CAM_PIX>,
+				 <&clk IMX93_CLK_PXP_GATE>,
+				 <&clk IMX93_CLK_LCDIF_GATE>,
+				 <&clk IMX93_CLK_ISI_GATE>,
+				 <&clk IMX93_CLK_MIPI_CSI_GATE>,
+				 <&clk IMX93_CLK_MIPI_DSI_GATE>;
+			clock-names = "apb", "axi", "nic", "disp", "cam",
+				      "pxp", "lcdif", "isi", "csi", "dsi";
+			#power-domain-cells = <1>;
 			status = "disabled";
 		};
-
-		usbmisc1: usbmisc@4c100200 {
-			compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
-			#index-cells = <1>;
-			reg = <0x4c100200 0x200>;
-		};
-
-		usbphynop2: usbphynop2 {
-			compatible = "usb-nop-xceiv";
-			clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>;
-			clock-names = "main_clk";
-		};
-
-		usbotg2: usb@4c200000 {
-			compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
-			reg = <0x4c200000 0x200>;
-			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>;
-			clock-names = "usb2_ctrl_root_clk";
-			assigned-clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>;
-			assigned-clock-parents = <&clk IMX93_CLK_HSIO>;
-			fsl,usbphy = <&usbphynop2>;
-			fsl,usbmisc = <&usbmisc2 0>;
-			status = "disabled";
-		};
-
-		usbmisc2: usbmisc@4c200200 {
-			compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
-			#index-cells = <1>;
-			reg = <0x4c200200 0x200>;
-		};
 	};
 };
diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
index a666271..cbd2717 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -61,6 +61,13 @@
 #define MXC_CPU_MX7ULP		0xE1 /* Temporally hard code */
 #define MXC_CPU_VF610		0xF6 /* dummy ID */
 #define MXC_CPU_IMX93		0xC1 /* dummy ID */
+#define MXC_CPU_IMX9351		0xC2 /* dummy ID */
+#define MXC_CPU_IMX9332		0xC3 /* dummy ID */
+#define MXC_CPU_IMX9331		0xC4 /* dummy ID */
+#define MXC_CPU_IMX9322		0xC5 /* dummy ID */
+#define MXC_CPU_IMX9321		0xC6 /* dummy ID */
+#define MXC_CPU_IMX9312		0xC7 /* dummy ID */
+#define MXC_CPU_IMX9311		0xC8 /* dummy ID */
 
 #define MXC_SOC_MX6		0x60
 #define MXC_SOC_MX7		0x70
diff --git a/arch/arm/include/asm/arch-imx8/power-domain.h b/arch/arm/include/asm/arch-imx8/power-domain.h
index 1db86a1..bdb0baa 100644
--- a/arch/arm/include/asm/arch-imx8/power-domain.h
+++ b/arch/arm/include/asm/arch-imx8/power-domain.h
@@ -6,7 +6,7 @@
 #ifndef _ASM_ARCH_IMX8_POWER_DOMAIN_H
 #define _ASM_ARCH_IMX8_POWER_DOMAIN_H
 
-#include <asm/arch/sci/types.h>
+#include <firmware/imx/sci/types.h>
 
 struct imx8_power_domain_plat {
 	sc_rsrc_t resource_id;
diff --git a/arch/arm/include/asm/arch-imx8/sci/rpc.h b/arch/arm/include/asm/arch-imx8/sci/rpc.h
deleted file mode 100644
index 39de7f0..0000000
--- a/arch/arm/include/asm/arch-imx8/sci/rpc.h
+++ /dev/null
@@ -1,230 +0,0 @@
-/* SPDX-License-Identifier:     GPL-2.0+ */
-/*
- * Copyright 2017-2018 NXP
- *
- */
-
-#ifndef SC_RPC_H
-#define SC_RPC_H
-
-/* Note: Check SCFW API Released DOC before you want to modify something */
-/* Defines */
-
-#define SCFW_API_VERSION_MAJOR  1U
-#define SCFW_API_VERSION_MINOR  21U
-
-#define SC_RPC_VERSION          1U
-
-#define SC_RPC_MAX_MSG          8U
-
-#define RPC_VER(MSG)            ((MSG)->version)
-#define RPC_SIZE(MSG)           ((MSG)->size)
-#define RPC_SVC(MSG)            ((MSG)->svc)
-#define RPC_FUNC(MSG)           ((MSG)->func)
-#define RPC_R8(MSG)             ((MSG)->func)
-#define RPC_I64(MSG, IDX)       ((s64)(RPC_U32((MSG), (IDX))) << 32ULL) | \
-				  (s64)(RPC_U32((MSG), (IDX) + 4U))
-#define RPC_I32(MSG, IDX)       ((MSG)->DATA.i32[(IDX) / 4U])
-#define RPC_I16(MSG, IDX)       ((MSG)->DATA.i16[(IDX) / 2U])
-#define RPC_I8(MSG, IDX)        ((MSG)->DATA.i8[(IDX)])
-#define RPC_U64(MSG, IDX)       ((u64)(RPC_U32((MSG), (IDX))) << 32ULL) | \
-				  (u64)(RPC_U32((MSG), (IDX) + 4U))
-#define RPC_U32(MSG, IDX)       ((MSG)->DATA.u32[(IDX) / 4U])
-#define RPC_U16(MSG, IDX)       ((MSG)->DATA.u16[(IDX) / 2U])
-#define RPC_U8(MSG, IDX)        ((MSG)->DATA.u8[(IDX)])
-
-#define SC_RPC_SVC_UNKNOWN      0U
-#define SC_RPC_SVC_RETURN       1U
-#define SC_RPC_SVC_PM           2U
-#define SC_RPC_SVC_RM           3U
-#define SC_RPC_SVC_TIMER        5U
-#define SC_RPC_SVC_PAD          6U
-#define SC_RPC_SVC_MISC         7U
-#define SC_RPC_SVC_IRQ          8U
-#define SC_RPC_SVC_SECO         9U
-#define SC_RPC_SVC_ABORT        10U
-
-
-/* Types */
-
-struct sc_rpc_msg_s {
-	u8 version;
-	u8 size;
-	u8 svc;
-	u8 func;
-	union {
-		s32 i32[(SC_RPC_MAX_MSG - 1U)];
-		s16 i16[(SC_RPC_MAX_MSG - 1U) * 2U];
-		s8 i8[(SC_RPC_MAX_MSG - 1U) * 4U];
-		u32 u32[(SC_RPC_MAX_MSG - 1U)];
-		u16 u16[(SC_RPC_MAX_MSG - 1U) * 2U];
-		u8 u8[(SC_RPC_MAX_MSG - 1U) * 4U];
-	} DATA;
-};
-
-/* PM RPC */
-#define PM_FUNC_UNKNOWN				0
-#define PM_FUNC_SET_SYS_POWER_MODE		19U
-#define PM_FUNC_SET_PARTITION_POWER_MODE	1U
-#define PM_FUNC_GET_SYS_POWER_MODE		2U
-#define PM_FUNC_SET_RESOURCE_POWER_MODE		3U
-#define PM_FUNC_GET_RESOURCE_POWER_MODE		4U
-#define PM_FUNC_REQ_LOW_POWER_MODE		16U
-#define PM_FUNC_REQ_CPU_LOW_POWER_MODE		20U
-#define PM_FUNC_SET_CPU_RESUME_ADDR		17U
-#define PM_FUNC_SET_CPU_RESUME			21U
-#define PM_FUNC_REQ_SYS_IF_POWER_MODE		18U
-#define PM_FUNC_SET_CLOCK_RATE			5U
-#define PM_FUNC_GET_CLOCK_RATE			6U
-#define PM_FUNC_CLOCK_ENABLE			7U
-#define PM_FUNC_SET_CLOCK_PARENT		14U
-#define PM_FUNC_GET_CLOCK_PARENT		15U
-#define PM_FUNC_RESET				13U
-#define PM_FUNC_RESET_REASON			10U
-#define PM_FUNC_BOOT				8U
-#define PM_FUNC_REBOOT				9U
-#define PM_FUNC_REBOOT_PARTITION		12U
-#define PM_FUNC_CPU_START			11U
-#define PM_FUNC_CPU_RESET			23U
-#define PM_FUNC_RESOURCE_RESET			29U
-#define PM_FUNC_IS_PARTITION_STARTED 24U
-
-/* MISC RPC */
-#define MISC_FUNC_UNKNOWN			0
-#define MISC_FUNC_SET_CONTROL			1U
-#define MISC_FUNC_GET_CONTROL			2U
-#define MISC_FUNC_SET_MAX_DMA_GROUP		4U
-#define MISC_FUNC_SET_DMA_GROUP			5U
-#define MISC_FUNC_SECO_IMAGE_LOAD		8U
-#define MISC_FUNC_SECO_AUTHENTICATE		9U
-#define MISC_FUNC_SECO_FUSE_WRITE		20U
-#define MISC_FUNC_SECO_ENABLE_DEBUG		21U
-#define MISC_FUNC_SECO_FORWARD_LIFECYCLE	22U
-#define MISC_FUNC_SECO_RETURN_LIFECYCLE		23U
-#define MISC_FUNC_SECO_BUILD_INFO		24U
-#define MISC_FUNC_DEBUG_OUT			10U
-#define MISC_FUNC_WAVEFORM_CAPTURE		6U
-#define MISC_FUNC_BUILD_INFO			15U
-#define MISC_FUNC_UNIQUE_ID			19U
-#define MISC_FUNC_SET_ARI			3U
-#define MISC_FUNC_BOOT_STATUS			7U
-#define MISC_FUNC_BOOT_DONE			14U
-#define MISC_FUNC_OTP_FUSE_READ			11U
-#define MISC_FUNC_OTP_FUSE_WRITE		17U
-#define MISC_FUNC_SET_TEMP			12U
-#define MISC_FUNC_GET_TEMP			13U
-#define MISC_FUNC_GET_BOOT_DEV			16U
-#define MISC_FUNC_GET_BUTTON_STATUS		18U
-#define MISC_FUNC_GET_BOOT_CONTAINER	36U
-
-/* PAD RPC */
-#define PAD_FUNC_UNKNOWN			0
-#define PAD_FUNC_SET_MUX			1U
-#define PAD_FUNC_GET_MUX			6U
-#define PAD_FUNC_SET_GP				2U
-#define PAD_FUNC_GET_GP				7U
-#define PAD_FUNC_SET_WAKEUP			4U
-#define PAD_FUNC_GET_WAKEUP			9U
-#define PAD_FUNC_SET_ALL			5U
-#define PAD_FUNC_GET_ALL			10U
-#define PAD_FUNC_SET				15U
-#define PAD_FUNC_GET				16U
-#define PAD_FUNC_SET_GP_28FDSOI			11U
-#define PAD_FUNC_GET_GP_28FDSOI			12U
-#define PAD_FUNC_SET_GP_28FDSOI_HSIC		3U
-#define PAD_FUNC_GET_GP_28FDSOI_HSIC		8U
-#define PAD_FUNC_SET_GP_28FDSOI_COMP		13U
-#define PAD_FUNC_GET_GP_28FDSOI_COMP		14U
-
-/* RM RPC */
-#define RM_FUNC_UNKNOWN				0
-#define RM_FUNC_PARTITION_ALLOC			1U
-#define RM_FUNC_SET_CONFIDENTIAL		31U
-#define RM_FUNC_PARTITION_FREE			2U
-#define RM_FUNC_GET_DID				26U
-#define RM_FUNC_PARTITION_STATIC		3U
-#define RM_FUNC_PARTITION_LOCK			4U
-#define RM_FUNC_GET_PARTITION			5U
-#define RM_FUNC_SET_PARENT			6U
-#define RM_FUNC_MOVE_ALL			7U
-#define RM_FUNC_ASSIGN_RESOURCE			8U
-#define RM_FUNC_SET_RESOURCE_MOVABLE		9U
-#define RM_FUNC_SET_SUBSYS_RSRC_MOVABLE		28U
-#define RM_FUNC_SET_MASTER_ATTRIBUTES		10U
-#define RM_FUNC_SET_MASTER_SID			11U
-#define RM_FUNC_SET_PERIPHERAL_PERMISSIONS	12U
-#define RM_FUNC_IS_RESOURCE_OWNED		13U
-#define RM_FUNC_GET_RESOURCE_OWNER 33U
-#define RM_FUNC_IS_RESOURCE_MASTER		14U
-#define RM_FUNC_IS_RESOURCE_PERIPHERAL		15U
-#define RM_FUNC_GET_RESOURCE_INFO		16U
-#define RM_FUNC_MEMREG_ALLOC			17U
-#define RM_FUNC_MEMREG_SPLIT			29U
-#define RM_FUNC_MEMREG_FREE			18U
-#define RM_FUNC_FIND_MEMREG			30U
-#define RM_FUNC_ASSIGN_MEMREG			19U
-#define RM_FUNC_SET_MEMREG_PERMISSIONS		20U
-#define RM_FUNC_IS_MEMREG_OWNED			21U
-#define RM_FUNC_GET_MEMREG_INFO			22U
-#define RM_FUNC_ASSIGN_PAD			23U
-#define RM_FUNC_SET_PAD_MOVABLE			24U
-#define RM_FUNC_IS_PAD_OWNED			25U
-#define RM_FUNC_DUMP				27U
-
-/* SECO RPC */
-#define SECO_FUNC_UNKNOWN 0 /* Unknown function */
-#define SECO_FUNC_IMAGE_LOAD 1U /* Index for seco_image_load() RPC call */
-#define SECO_FUNC_AUTHENTICATE 2U /* Index for seco_authenticate() RPC call */
-#define SECO_FUNC_ENH_AUTHENTICATE 24U /* Index for sc_seco_enh_authenticate() RPC call */
-#define SECO_FUNC_FORWARD_LIFECYCLE 3U /* Index for seco_forward_lifecycle() RPC call */
-#define SECO_FUNC_RETURN_LIFECYCLE 4U /* Index for seco_return_lifecycle() RPC call */
-#define SECO_FUNC_COMMIT 5U /* Index for seco_commit() RPC call */
-#define SECO_FUNC_ATTEST_MODE 6U /* Index for seco_attest_mode() RPC call */
-#define SECO_FUNC_ATTEST 7U /* Index for seco_attest() RPC call */
-#define SECO_FUNC_GET_ATTEST_PKEY 8U /* Index for seco_get_attest_pkey() RPC call */
-#define SECO_FUNC_GET_ATTEST_SIGN 9U /* Index for seco_get_attest_sign() RPC call */
-#define SECO_FUNC_ATTEST_VERIFY 10U /* Index for seco_attest_verify() RPC call */
-#define SECO_FUNC_GEN_KEY_BLOB 11U /* Index for seco_gen_key_blob() RPC call */
-#define SECO_FUNC_LOAD_KEY 12U /* Index for seco_load_key() RPC call */
-#define SECO_FUNC_GET_MP_KEY 13U /* Index for seco_get_mp_key() RPC call */
-#define SECO_FUNC_UPDATE_MPMR 14U /* Index for seco_update_mpmr() RPC call */
-#define SECO_FUNC_GET_MP_SIGN 15U /* Index for seco_get_mp_sign() RPC call */
-#define SECO_FUNC_BUILD_INFO 16U /* Index for seco_build_info() RPC call */
-#define SECO_FUNC_CHIP_INFO 17U /* Index for seco_chip_info() RPC call */
-#define SECO_FUNC_ENABLE_DEBUG 18U /* Index for seco_enable_debug() RPC call */
-#define SECO_FUNC_GET_EVENT 19U /* Index for seco_get_event() RPC call */
-#define SECO_FUNC_FUSE_WRITE 20U /* Index for seco_fuse_write() RPC call */
-#define SECO_FUNC_PATCH 21U /* Index for sc_seco_patch() RPC call */
-#define SECO_FUNC_START_RNG 22U /* Index for sc_seco_start_rng() RPC call */
-#define SECO_FUNC_SAB_MSG 23U /* Index for sc_seco_sab_msg() RPC call */
-#define SECO_FUNC_SECVIO_ENABLE 25U /* Index for sc_seco_secvio_enable() RPC call */
-#define SECO_FUNC_SECVIO_CONFIG 26U /* Index for sc_seco_secvio_config() RPC call */
-#define SECO_FUNC_SECVIO_DGO_CONFIG 27U /* Index for sc_seco_secvio_dgo_config() RPC call */
-
-/* IRQ RPC */
-#define IRQ_FUNC_UNKNOWN 0 /* Unknown function */
-#define IRQ_FUNC_ENABLE 1U /* Index for sc_irq_enable() RPC call */
-#define IRQ_FUNC_STATUS 2U /* Index for sc_irq_status() RPC call */
-
-/* TIMER RPC */
-#define TIMER_FUNC_UNKNOWN 0 /* Unknown function */
-#define TIMER_FUNC_SET_WDOG_TIMEOUT 1U /* Index for sc_timer_set_wdog_timeout() RPC call */
-#define TIMER_FUNC_SET_WDOG_PRE_TIMEOUT 12U /* Index for sc_timer_set_wdog_pre_timeout() RPC call */
-#define TIMER_FUNC_START_WDOG 2U /* Index for sc_timer_start_wdog() RPC call */
-#define TIMER_FUNC_STOP_WDOG 3U /* Index for sc_timer_stop_wdog() RPC call */
-#define TIMER_FUNC_PING_WDOG 4U /* Index for sc_timer_ping_wdog() RPC call */
-#define TIMER_FUNC_GET_WDOG_STATUS 5U /* Index for sc_timer_get_wdog_status() RPC call */
-#define TIMER_FUNC_PT_GET_WDOG_STATUS 13U /* Index for sc_timer_pt_get_wdog_status() RPC call */
-#define TIMER_FUNC_SET_WDOG_ACTION 10U /* Index for sc_timer_set_wdog_action() RPC call */
-#define TIMER_FUNC_SET_RTC_TIME 6U /* Index for sc_timer_set_rtc_time() RPC call */
-#define TIMER_FUNC_GET_RTC_TIME 7U /* Index for sc_timer_get_rtc_time() RPC call */
-#define TIMER_FUNC_GET_RTC_SEC1970 9U /* Index for sc_timer_get_rtc_sec1970() RPC call */
-#define TIMER_FUNC_SET_RTC_ALARM 8U /* Index for sc_timer_set_rtc_alarm() RPC call */
-#define TIMER_FUNC_SET_RTC_PERIODIC_ALARM 14U /* Index for sc_timer_set_rtc_periodic_alarm() RPC call */
-#define TIMER_FUNC_CANCEL_RTC_ALARM 15U /* Index for sc_timer_cancel_rtc_alarm() RPC call */
-#define TIMER_FUNC_SET_RTC_CALB 11U /* Index for sc_timer_set_rtc_calb() RPC call */
-#define TIMER_FUNC_SET_SYSCTR_ALARM 16U /* Index for sc_timer_set_sysctr_alarm() RPC call */
-#define TIMER_FUNC_SET_SYSCTR_PERIODIC_ALARM 17U /* Index for sc_timer_set_sysctr_periodic_alarm() RPC call */
-#define TIMER_FUNC_CANCEL_SYSCTR_ALARM 18U /* Index for sc_timer_cancel_sysctr_alarm() RPC call */
-
-#endif /* SC_RPC_H */
diff --git a/arch/arm/include/asm/arch-imx8/sci/sci.h b/arch/arm/include/asm/arch-imx8/sci/sci.h
deleted file mode 100644
index 1c29209..0000000
--- a/arch/arm/include/asm/arch-imx8/sci/sci.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2018 NXP
- */
-
-#ifndef _SC_SCI_H
-#define _SC_SCI_H
-
-#include <log.h>
-#include <asm/arch/sci/types.h>
-#include <asm/arch/sci/svc/misc/api.h>
-#include <asm/arch/sci/svc/pad/api.h>
-#include <asm/arch/sci/svc/pm/api.h>
-#include <asm/arch/sci/svc/rm/api.h>
-#include <asm/arch/sci/svc/seco/api.h>
-#include <asm/arch/sci/rpc.h>
-#include <dt-bindings/soc/imx_rsrc.h>
-#include <linux/errno.h>
-
-static inline int sc_err_to_linux(sc_err_t err)
-{
-	int ret;
-
-	switch (err) {
-	case SC_ERR_NONE:
-		return 0;
-	case SC_ERR_VERSION:
-	case SC_ERR_CONFIG:
-	case SC_ERR_PARM:
-		ret = -EINVAL;
-		break;
-	case SC_ERR_NOACCESS:
-	case SC_ERR_LOCKED:
-	case SC_ERR_UNAVAILABLE:
-		ret = -EACCES;
-		break;
-	case SC_ERR_NOTFOUND:
-	case SC_ERR_NOPOWER:
-		ret = -ENODEV;
-		break;
-	case SC_ERR_IPC:
-		ret = -EIO;
-		break;
-	case SC_ERR_BUSY:
-		ret = -EBUSY;
-		break;
-	case SC_ERR_FAIL:
-		ret = -EIO;
-		break;
-	default:
-		ret = 0;
-		break;
-	}
-
-	debug("%s %d %d\n", __func__, err, ret);
-
-	return ret;
-}
-
-/* PM API*/
-int sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
-				  sc_pm_power_mode_t mode);
-int sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
-				  sc_pm_power_mode_t *mode);
-int sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
-			 sc_pm_clock_rate_t *rate);
-int sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
-			 sc_pm_clock_rate_t *rate);
-int sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
-		       sc_bool_t enable, sc_bool_t autog);
-int sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
-			   sc_pm_clk_parent_t parent);
-int sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable,
-		    sc_faddr_t address);
-sc_bool_t sc_pm_is_partition_started(sc_ipc_t ipc, sc_rm_pt_t pt);
-int sc_pm_resource_reset(sc_ipc_t ipc, sc_rsrc_t resource);
-
-/* MISC API */
-int sc_misc_set_control(sc_ipc_t ipc, sc_rsrc_t resource,
-			sc_ctrl_t ctrl, u32 val);
-int sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource, sc_ctrl_t ctrl,
-			u32 *val);
-void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *boot_dev);
-void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status);
-int sc_misc_get_boot_container(sc_ipc_t ipc, u8 *idx);
-void sc_misc_build_info(sc_ipc_t ipc, u32 *build, u32 *commit);
-int sc_misc_otp_fuse_read(sc_ipc_t ipc, u32 word, u32 *val);
-int sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, sc_misc_temp_t temp,
-		     s16 *celsius, s8 *tenths);
-
-/* RM API */
-sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr);
-int sc_rm_find_memreg(sc_ipc_t ipc, sc_rm_mr_t *mr, sc_faddr_t addr_start,
-		      sc_faddr_t addr_end);
-int sc_rm_set_memreg_permissions(sc_ipc_t ipc, sc_rm_mr_t mr,
-				 sc_rm_pt_t pt, sc_rm_perm_t perm);
-int sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr, sc_faddr_t *addr_start,
-			  sc_faddr_t *addr_end);
-sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource);
-int sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, sc_bool_t secure,
-			  sc_bool_t isolated, sc_bool_t restricted,
-			  sc_bool_t grant, sc_bool_t coherent);
-int sc_rm_partition_free(sc_ipc_t ipc, sc_rm_pt_t pt);
-int sc_rm_get_partition(sc_ipc_t ipc, sc_rm_pt_t *pt);
-int sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_pt_t pt_parent);
-int sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rsrc_t resource);
-int sc_rm_assign_pad(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pad_t pad);
-sc_bool_t sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad);
-int sc_rm_get_resource_owner(sc_ipc_t ipc, sc_rsrc_t resource,
-			     sc_rm_pt_t *pt);
-
-/* PAD API */
-int sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, u32 val);
-int sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val);
-
-/* SMMU API */
-int sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid);
-
-/* SECO API */
-int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd,
-			 sc_faddr_t addr);
-int sc_seco_forward_lifecycle(sc_ipc_t ipc, u32 change);
-int sc_seco_chip_info(sc_ipc_t ipc, u16 *lc, u16 *monotonic, u32 *uid_l,
-		      u32 *uid_h);
-void sc_seco_build_info(sc_ipc_t ipc, u32 *version, u32 *commit);
-int sc_seco_get_event(sc_ipc_t ipc, u8 idx, u32 *event);
-int sc_seco_gen_key_blob(sc_ipc_t ipc, u32 id, sc_faddr_t load_addr,
-			 sc_faddr_t export_addr, u16 max_size);
-int sc_seco_get_mp_key(sc_ipc_t ipc, sc_faddr_t dst_addr, u16 dst_size);
-int sc_seco_update_mpmr(sc_ipc_t ipc, sc_faddr_t addr, u8 size, u8 lock);
-int sc_seco_get_mp_sign(sc_ipc_t ipc, sc_faddr_t msg_addr,
-			u16 msg_size, sc_faddr_t dst_addr, u16 dst_size);
-int sc_seco_secvio_dgo_config(sc_ipc_t ipc, u8 id, u8 access, u32 *data);
-int sc_seco_secvio_config(sc_ipc_t ipc, u8 id, u8 access,
-			  u32 *data0, u32 *data1, u32 *data2, u32 *data3,
-			  u32 *data4, u8 size);
-
-#endif
diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h
deleted file mode 100644
index 3629eb6..0000000
--- a/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier:     GPL-2.0+ */
-/*
- * Copyright 2018 NXP
- */
-
-#ifndef SC_MISC_API_H
-#define SC_MISC_API_H
-
-/* Defines for sc_misc_boot_status_t */
-#define SC_MISC_BOOT_STATUS_SUCCESS	0U	/* Success */
-#define SC_MISC_BOOT_STATUS_SECURITY	1U	/* Security violation */
-
-/* Defines for sc_misc_seco_auth_cmd_t */
-#define SC_MISC_SECO_AUTH_SECO_FW	0U   /* SECO Firmware */
-#define SC_MISC_SECO_AUTH_HDMI_TX_FW	1U   /* HDMI TX Firmware */
-#define SC_MISC_SECO_AUTH_HDMI_RX_FW	2U   /* HDMI RX Firmware */
-
-/* Defines for sc_misc_temp_t */
-#define SC_MISC_TEMP			0U	/* Temp sensor */
-#define SC_MISC_TEMP_HIGH		1U	/* Temp high alarm */
-#define SC_MISC_TEMP_LOW		2U	/* Temp low alarm */
-
-/* Defines for sc_misc_seco_auth_cmd_t */
-#define SC_MISC_AUTH_CONTAINER	0U	/* Authenticate container */
-#define SC_MISC_VERIFY_IMAGE	1U	/* Verify image */
-#define SC_MISC_REL_CONTAINER	2U	/* Release container */
-
-typedef u8 sc_misc_boot_status_t;
-typedef u8 sc_misc_temp_t;
-
-#endif /* SC_MISC_API_H */
diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h
deleted file mode 100644
index df368e8..0000000
--- a/arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* SPDX-License-Identifier:     GPL-2.0+ */
-/*
- * Copyright 2018 NXP
- */
-
-#ifndef SC_PAD_API_H
-#define SC_PAD_API_H
-
-/* Defines for type widths */
-#define SC_PAD_MUX_W            3U    /* Width of mux parameter */
-
-/* Defines for sc_pad_config_t */
-#define SC_PAD_CONFIG_NORMAL	0U	/* Normal */
-#define SC_PAD_CONFIG_OD	1U	/* Open Drain */
-#define SC_PAD_CONFIG_OD_IN	2U	/* Open Drain and input */
-#define SC_PAD_CONFIG_OUT_IN	3U	/* Output and input */
-
-/* Defines for sc_pad_iso_t */
-#define SC_PAD_ISO_OFF		0U	/* ISO latch is transparent */
-#define SC_PAD_ISO_EARLY	1U	/* Follow EARLY_ISO */
-#define SC_PAD_ISO_LATE		2U	/* Follow LATE_ISO */
-#define SC_PAD_ISO_ON		3U	/* ISO latched data is held */
-
-/* Defines for sc_pad_28fdsoi_dse_t */
-#define SC_PAD_28FDSOI_DSE_18V_1MA	0U /* Drive strength of 1mA for 1.8v */
-#define SC_PAD_28FDSOI_DSE_18V_2MA	1U /* Drive strength of 2mA for 1.8v */
-#define SC_PAD_28FDSOI_DSE_18V_4MA	2U /* Drive strength of 4mA for 1.8v */
-#define SC_PAD_28FDSOI_DSE_18V_6MA	3U /* Drive strength of 6mA for 1.8v */
-#define SC_PAD_28FDSOI_DSE_18V_8MA	4U /* Drive strength of 8mA for 1.8v */
-#define SC_PAD_28FDSOI_DSE_18V_10MA	5U /* Drive strength of 10mA for 1.8v */
-#define SC_PAD_28FDSOI_DSE_18V_12MA	6U /* Drive strength of 12mA for 1.8v */
-#define SC_PAD_28FDSOI_DSE_18V_HS	7U /* High-speed for 1.8v */
-#define SC_PAD_28FDSOI_DSE_33V_2MA	0U /* Drive strength of 2mA for 3.3v */
-#define SC_PAD_28FDSOI_DSE_33V_4MA	1U /* Drive strength of 4mA for 3.3v */
-#define SC_PAD_28FDSOI_DSE_33V_8MA	2U /* Drive strength of 8mA for 3.3v */
-#define SC_PAD_28FDSOI_DSE_33V_12MA	3U /* Drive strength of 12mA for 3.3v */
-#define SC_PAD_28FDSOI_DSE_DV_HIGH	0U /* High drive strength dual volt */
-#define SC_PAD_28FDSOI_DSE_DV_LOW	1U /* Low drive strength  dual volt */
-
-/* Defines for sc_pad_28fdsoi_ps_t */
-#define SC_PAD_28FDSOI_PS_KEEPER 0U /* Bus-keeper (only valid for 1.8v) */
-#define SC_PAD_28FDSOI_PS_PU	1U /* Pull-up */
-#define SC_PAD_28FDSOI_PS_PD	2U /* Pull-down */
-#define SC_PAD_28FDSOI_PS_NONE	3U /* No pull (disabled) */
-
-/* Defines for sc_pad_28fdsoi_pus_t */
-#define SC_PAD_28FDSOI_PUS_30K_PD	0U /* 30K pull-down */
-#define SC_PAD_28FDSOI_PUS_100K_PU	1U /* 100K pull-up */
-#define SC_PAD_28FDSOI_PUS_3K_PU	2U /* 3K pull-up */
-#define SC_PAD_28FDSOI_PUS_30K_PU	3U /* 30K pull-up */
-
-/* Defines for sc_pad_wakeup_t */
-#define SC_PAD_WAKEUP_OFF	0U /* Off */
-#define SC_PAD_WAKEUP_CLEAR	1U /* Clears pending flag */
-#define SC_PAD_WAKEUP_LOW_LVL	4U /* Low level */
-#define SC_PAD_WAKEUP_FALL_EDGE	5U /* Falling edge */
-#define SC_PAD_WAKEUP_RISE_EDGE	6U /* Rising edge */
-#define SC_PAD_WAKEUP_HIGH_LVL	7U /* High-level */
-
-#endif /* SC_PAD_API_H */
diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h
deleted file mode 100644
index 9008b85..0000000
--- a/arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* SPDX-License-Identifier:     GPL-2.0+ */
-/*
- * Copyright 2018 NXP
- */
-
-#ifndef SC_PM_API_H
-#define SC_PM_API_H
-
-/* Defines for sc_pm_power_mode_t */
-#define SC_PM_PW_MODE_OFF	0U /* Power off */
-#define SC_PM_PW_MODE_STBY	1U /* Power in standby */
-#define SC_PM_PW_MODE_LP	2U /* Power in low-power */
-#define SC_PM_PW_MODE_ON	3U /* Power on */
-
-/* Defines for sc_pm_clk_t */
-#define SC_PM_CLK_SLV_BUS	0U /* Slave bus clock */
-#define SC_PM_CLK_MST_BUS	1U /* Master bus clock */
-#define SC_PM_CLK_PER		2U /* Peripheral clock */
-#define SC_PM_CLK_PHY		3U /* Phy clock */
-#define SC_PM_CLK_MISC		4U /* Misc clock */
-#define SC_PM_CLK_MISC0		0U /* Misc 0 clock */
-#define SC_PM_CLK_MISC1		1U /* Misc 1 clock */
-#define SC_PM_CLK_MISC2		2U /* Misc 2 clock */
-#define SC_PM_CLK_MISC3		3U /* Misc 3 clock */
-#define SC_PM_CLK_MISC4		4U /* Misc 4 clock */
-#define SC_PM_CLK_CPU		2U /* CPU clock */
-#define SC_PM_CLK_PLL		4U /* PLL */
-#define SC_PM_CLK_BYPASS	4U /* Bypass clock */
-
-/* Defines for sc_pm_clk_mode_t */
-#define SC_PM_CLK_MODE_ROM_INIT		0U /* Clock is initialized by ROM. */
-#define SC_PM_CLK_MODE_OFF		1U /* Clock is disabled */
-#define SC_PM_CLK_MODE_ON		2U /* Clock is enabled. */
-#define SC_PM_CLK_MODE_AUTOGATE_SW	3U /* Clock is in SW autogate mode */
-#define SC_PM_CLK_MODE_AUTOGATE_HW	4U /* Clock is in HW autogate mode */
-#define SC_PM_CLK_MODE_AUTOGATE_SW_HW	5U /* Clock is in SW-HW autogate mode */
-
-typedef u8 sc_pm_power_mode_t;
-typedef u8 sc_pm_clk_t;
-typedef u8 sc_pm_clk_mode_t;
-typedef u8 sc_pm_clk_parent_t;
-typedef u32 sc_pm_clock_rate_t;
-
-#endif /* SC_PM_API_H */
diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h
deleted file mode 100644
index ed30388..0000000
--- a/arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/* SPDX-License-Identifier:     GPL-2.0+ */
-/*
- * Copyright 2018 NXP
- */
-
-#ifndef SC_RM_API_H
-#define SC_RM_API_H
-
-#include <asm/arch/sci/types.h>
-
-/* Defines for type widths */
-#define SC_RM_PARTITION_W   5U      /* Width of sc_rm_pt_t */
-#define SC_RM_MEMREG_W      6U      /* Width of sc_rm_mr_t */
-#define SC_RM_DID_W         4U      /* Width of sc_rm_did_t */
-#define SC_RM_SID_W         6U      /* Width of sc_rm_sid_t */
-#define SC_RM_SPA_W         2U      /* Width of sc_rm_spa_t */
-#define SC_RM_PERM_W        3U      /* Width of sc_rm_perm_t */
-
-/* Defines for ALL parameters */
-#define SC_RM_PT_ALL        ((sc_rm_pt_t)UINT8_MAX)   /* All partitions */
-#define SC_RM_MR_ALL        ((sc_rm_mr_t)UINT8_MAX)   /* All memory regions */
-
-/* Defines for sc_rm_spa_t */
-#define SC_RM_SPA_PASSTHRU  0U   /* Pass through (attribute driven by master) */
-#define SC_RM_SPA_PASSSID   1U   /* Pass through and output on SID */
-#define SC_RM_SPA_ASSERT    2U   /* Assert (force to be secure/privileged) */
-#define SC_RM_SPA_NEGATE    3U   /* Negate (force to be non-secure/user) */
-
-/* Defines for sc_rm_perm_t */
-#define SC_RM_PERM_NONE         0U /* No access */
-#define SC_RM_PERM_SEC_R        1U /* Secure RO */
-#define SC_RM_PERM_SECPRIV_RW   2U /* Secure privilege R/W */
-#define SC_RM_PERM_SEC_RW       3U /* Secure R/W */
-#define SC_RM_PERM_NSPRIV_R     4U /* Secure R/W, non-secure privilege RO */
-#define SC_RM_PERM_NS_R         5U /* Secure R/W, non-secure RO */
-#define SC_RM_PERM_NSPRIV_RW    6U /* Secure R/W, non-secure privilege R/W */
-#define SC_RM_PERM_FULL         7U /* Full access */
-
-/* Types */
-
-/*!
- * This type is used to declare a resource partition.
- */
-typedef u8 sc_rm_pt_t;
-
-/*!
- * This type is used to declare a memory region.
- */
-typedef u8 sc_rm_mr_t;
-
-/*!
- * This type is used to declare a resource domain ID used by the
- * isolation HW.
- */
-typedef u8 sc_rm_did_t;
-
-/*!
- * This type is used to declare an SMMU StreamID.
- */
-typedef u16 sc_rm_sid_t;
-
-/*!
- * This type is a used to declare master transaction attributes.
- */
-typedef u8 sc_rm_spa_t;
-
-typedef u8 sc_rm_perm_t;
-
-#endif /* SC_RM_API_H */
diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/seco/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/seco/api.h
deleted file mode 100644
index 3ed0584..0000000
--- a/arch/arm/include/asm/arch-imx8/sci/svc/seco/api.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier:     GPL-2.0+ */
-/*
- * Copyright 2019 NXP
- */
-
-#ifndef SC_SECO_API_H
-#define SC_SECO_API_H
-
-/* Includes */
-
-#include <asm/arch/sci/types.h>
-
-/* Defines */
-#define SC_SECO_AUTH_CONTAINER          0U   /* Authenticate container */
-#define SC_SECO_VERIFY_IMAGE            1U   /* Verify image */
-#define SC_SECO_REL_CONTAINER           2U   /* Release container */
-#define SC_SECO_AUTH_SECO_FW            3U   /* SECO Firmware */
-#define SC_SECO_AUTH_HDMI_TX_FW         4U   /* HDMI TX Firmware */
-#define SC_SECO_AUTH_HDMI_RX_FW         5U   /* HDMI RX Firmware */
-
-#define SC_SECO_RNG_STAT_UNAVAILABLE    0U  /* Unable to initialize the RNG */
-#define SC_SECO_RNG_STAT_INPROGRESS     1U  /* Initialization is on-going */
-#define SC_SECO_RNG_STAT_READY          2U  /* Initialized */
-
-/* Types */
-
-/*!
- * This type is used to issue SECO authenticate commands.
- */
-typedef u8 sc_seco_auth_cmd_t;
-
-/*!
- * This type is used to return the RNG initialization status.
- */
-typedef u32 sc_seco_rng_stat_t;
-
-#endif /* SC_SECO_API_H */
diff --git a/arch/arm/include/asm/arch-imx8/sci/types.h b/arch/arm/include/asm/arch-imx8/sci/types.h
deleted file mode 100644
index adfed13..0000000
--- a/arch/arm/include/asm/arch-imx8/sci/types.h
+++ /dev/null
@@ -1,226 +0,0 @@
-/* SPDX-License-Identifier:     GPL-2.0+ */
-/*
- * Copyright 2018 NXP
- */
-
-#ifndef SC_TYPES_H
-#define SC_TYPES_H
-
-/* Includes */
-#include <linux/types.h>
-
-/* Defines */
-/*
- * This type is used to declare a handle for an IPC communication
- * channel. Its meaning is specific to the IPC implementation.
- */
-typedef u64 sc_ipc_t;
-
-/* Defines for common frequencies */
-#define SC_32KHZ            32768U   /* 32KHz */
-#define SC_10MHZ         10000000U   /* 10MHz */
-#define SC_20MHZ         20000000U   /* 20MHz */
-#define SC_25MHZ         25000000U   /* 25MHz */
-#define SC_27MHZ         27000000U   /* 27MHz */
-#define SC_40MHZ         40000000U   /* 40MHz */
-#define SC_45MHZ         45000000U   /* 45MHz */
-#define SC_50MHZ         50000000U   /* 50MHz */
-#define SC_60MHZ         60000000U   /* 60MHz */
-#define SC_66MHZ         66666666U   /* 66MHz */
-#define SC_74MHZ         74250000U   /* 74.25MHz */
-#define SC_80MHZ         80000000U   /* 80MHz */
-#define SC_83MHZ         83333333U   /* 83MHz */
-#define SC_84MHZ         84375000U   /* 84.37MHz */
-#define SC_100MHZ       100000000U   /* 100MHz */
-#define SC_114MHZ       114000000U   /* 114MHz */
-#define SC_125MHZ       125000000U   /* 125MHz */
-#define SC_133MHZ       133333333U   /* 133MHz */
-#define SC_135MHZ       135000000U   /* 135MHz */
-#define SC_150MHZ       150000000U   /* 150MHz */
-#define SC_160MHZ       160000000U   /* 160MHz */
-#define SC_166MHZ       166666666U   /* 166MHz */
-#define SC_175MHZ       175000000U   /* 175MHz */
-#define SC_180MHZ       180000000U   /* 180MHz */
-#define SC_200MHZ       200000000U   /* 200MHz */
-#define SC_250MHZ       250000000U   /* 250MHz */
-#define SC_266MHZ       266666666U   /* 266MHz */
-#define SC_300MHZ       300000000U   /* 300MHz */
-#define SC_312MHZ       312500000U   /* 312.5MHZ */
-#define SC_320MHZ       320000000U   /* 320MHz */
-#define SC_325MHZ       325000000U   /* 325MHz */
-#define SC_333MHZ       333333333U   /* 333MHz */
-#define SC_350MHZ       350000000U   /* 350MHz */
-#define SC_372MHZ       372000000U   /* 372MHz */
-#define SC_375MHZ       375000000U   /* 375MHz */
-#define SC_400MHZ       400000000U   /* 400MHz */
-#define SC_465MHZ       465000000U   /* 465MHz */
-#define SC_500MHZ       500000000U   /* 500MHz */
-#define SC_594MHZ       594000000U   /* 594MHz */
-#define SC_625MHZ       625000000U   /* 625MHz */
-#define SC_640MHZ       640000000U   /* 640MHz */
-#define SC_650MHZ       650000000U   /* 650MHz */
-#define SC_667MHZ       666666667U   /* 667MHz */
-#define SC_675MHZ       675000000U   /* 675MHz */
-#define SC_700MHZ       700000000U   /* 700MHz */
-#define SC_720MHZ       720000000U   /* 720MHz */
-#define SC_750MHZ       750000000U   /* 750MHz */
-#define SC_800MHZ       800000000U   /* 800MHz */
-#define SC_850MHZ       850000000U   /* 850MHz */
-#define SC_900MHZ       900000000U   /* 900MHz */
-#define SC_1000MHZ     1000000000U   /* 1GHz */
-#define SC_1060MHZ     1060000000U   /* 1.06GHz */
-#define SC_1188MHZ     1188000000U   /* 1.188GHz */
-#define SC_1260MHZ     1260000000U   /* 1.26GHz */
-#define SC_1280MHZ     1280000000U   /* 1.28GHz */
-#define SC_1300MHZ     1300000000U   /* 1.3GHz */
-#define SC_1400MHZ     1400000000U   /* 1.4GHz */
-#define SC_1500MHZ     1500000000U   /* 1.5GHz */
-#define SC_1600MHZ     1600000000U   /* 1.6GHz */
-#define SC_1800MHZ     1800000000U   /* 1.8GHz */
-#define SC_1860MHZ     1860000000U   /* 1.86GHz */
-#define SC_2000MHZ     2000000000U   /* 2.0GHz */
-#define SC_2112MHZ     2112000000U   /* 2.12GHz */
-
-/* Defines for 24M related frequencies */
-#define SC_8MHZ           8000000U   /* 8MHz */
-#define SC_12MHZ         12000000U   /* 12MHz */
-#define SC_19MHZ         19800000U   /* 19.8MHz */
-#define SC_24MHZ         24000000U   /* 24MHz */
-#define SC_48MHZ         48000000U   /* 48MHz */
-#define SC_120MHZ       120000000U   /* 120MHz */
-#define SC_132MHZ       132000000U   /* 132MHz */
-#define SC_144MHZ       144000000U   /* 144MHz */
-#define SC_192MHZ       192000000U   /* 192MHz */
-#define SC_211MHZ       211200000U   /* 211.2MHz */
-#define SC_228MHZ       228000000U   /* 233MHz */
-#define SC_240MHZ       240000000U   /* 240MHz */
-#define SC_264MHZ       264000000U   /* 264MHz */
-#define SC_352MHZ       352000000U   /* 352MHz */
-#define SC_360MHZ       360000000U   /* 360MHz */
-#define SC_384MHZ       384000000U   /* 384MHz */
-#define SC_396MHZ       396000000U   /* 396MHz */
-#define SC_432MHZ       432000000U   /* 432MHz */
-#define SC_456MHZ       456000000U   /* 466MHz */
-#define SC_480MHZ       480000000U   /* 480MHz */
-#define SC_600MHZ       600000000U   /* 600MHz */
-#define SC_744MHZ       744000000U   /* 744MHz */
-#define SC_792MHZ       792000000U   /* 792MHz */
-#define SC_864MHZ       864000000U   /* 864MHz */
-#define SC_912MHZ       912000000U   /* 912MHz */
-#define SC_960MHZ       960000000U   /* 960MHz */
-#define SC_1056MHZ     1056000000U   /* 1056MHz */
-#define SC_1104MHZ     1104000000U   /* 1104MHz */
-#define SC_1200MHZ     1200000000U   /* 1.2GHz */
-#define SC_1464MHZ     1464000000U   /* 1.464GHz */
-#define SC_2400MHZ     2400000000U   /* 2.4GHz */
-
-/* Defines for A/V related frequencies */
-#define SC_62MHZ         62937500U   /* 62.9375MHz */
-#define SC_755MHZ       755250000U   /* 755.25MHz */
-
-/* Defines for type widths */
-#define SC_FADDR_W      36U          /* Width of sc_faddr_t */
-#define SC_BOOL_W       1U           /* Width of sc_bool_t */
-#define SC_ERR_W        4U           /* Width of sc_err_t */
-#define SC_RSRC_W       10U          /* Width of sc_rsrc_t */
-#define SC_CTRL_W       6U           /* Width of sc_ctrl_t */
-
-/* Defines for sc_bool_t */
-#define SC_FALSE        ((sc_bool_t)0U)
-#define SC_TRUE         ((sc_bool_t)1U)
-
-/* Defines for sc_err_t */
-#define SC_ERR_NONE         0U      /* Success */
-#define SC_ERR_VERSION      1U      /* Incompatible API version */
-#define SC_ERR_CONFIG       2U      /* Configuration error */
-#define SC_ERR_PARM         3U      /* Bad parameter */
-#define SC_ERR_NOACCESS     4U      /* Permission error (no access) */
-#define SC_ERR_LOCKED       5U      /* Permission error (locked) */
-#define SC_ERR_UNAVAILABLE  6U      /* Unavailable (out of resources) */
-#define SC_ERR_NOTFOUND     7U      /* Not found */
-#define SC_ERR_NOPOWER      8U      /* No power */
-#define SC_ERR_IPC          9U      /* Generic IPC error */
-#define SC_ERR_BUSY         10U     /* Resource is currently busy/active */
-#define SC_ERR_FAIL         11U     /* General I/O failure */
-#define SC_ERR_LAST         12U
-
-/* Defines for sc_ctrl_t. */
-#define SC_C_TEMP                       0U
-#define SC_C_TEMP_HI                    1U
-#define SC_C_TEMP_LOW                   2U
-#define SC_C_PXL_LINK_MST1_ADDR         3U
-#define SC_C_PXL_LINK_MST2_ADDR         4U
-#define SC_C_PXL_LINK_MST_ENB           5U
-#define SC_C_PXL_LINK_MST1_ENB          6U
-#define SC_C_PXL_LINK_MST2_ENB          7U
-#define SC_C_PXL_LINK_SLV1_ADDR         8U
-#define SC_C_PXL_LINK_SLV2_ADDR         9U
-#define SC_C_PXL_LINK_MST_VLD           10U
-#define SC_C_PXL_LINK_MST1_VLD          11U
-#define SC_C_PXL_LINK_MST2_VLD          12U
-#define SC_C_SINGLE_MODE                13U
-#define SC_C_ID                         14U
-#define SC_C_PXL_CLK_POLARITY           15U
-#define SC_C_LINESTATE                  16U
-#define SC_C_PCIE_G_RST                 17U
-#define SC_C_PCIE_BUTTON_RST            18U
-#define SC_C_PCIE_PERST                 19U
-#define SC_C_PHY_RESET                  20U
-#define SC_C_PXL_LINK_RATE_CORRECTION   21U
-#define SC_C_PANIC                      22U
-#define SC_C_PRIORITY_GROUP             23U
-#define SC_C_TXCLK                      24U
-#define SC_C_CLKDIV                     25U
-#define SC_C_DISABLE_50                 26U
-#define SC_C_DISABLE_125                27U
-#define SC_C_SEL_125                    28U
-#define SC_C_MODE                       29U
-#define SC_C_SYNC_CTRL0                 30U
-#define SC_C_KACHUNK_CNT                31U
-#define SC_C_KACHUNK_SEL                32U
-#define SC_C_SYNC_CTRL1                 33U
-#define SC_C_DPI_RESET                  34U
-#define SC_C_MIPI_RESET                 35U
-#define SC_C_DUAL_MODE                  36U
-#define SC_C_VOLTAGE                    37U
-#define SC_C_PXL_LINK_SEL               38U
-#define SC_C_OFS_SEL                    39U
-#define SC_C_OFS_AUDIO                  40U
-#define SC_C_OFS_PERIPH                 41U
-#define SC_C_OFS_IRQ                    42U
-#define SC_C_RST0                       43U
-#define SC_C_RST1                       44U
-#define SC_C_SEL0                       45U
-#define SC_C_LAST                       46U
-
-#define SC_P_ALL        ((sc_pad_t)UINT16_MAX)   /* All pads */
-
-/* Types */
-
-/* This type is used to store a boolean */
-typedef u8 sc_bool_t;
-
-/* This type is used to store a system (full-size) address.  */
-typedef u64 sc_faddr_t;
-
-/* This type is used to indicate error response for most functions.  */
-typedef u8 sc_err_t;
-
-/*
- * This type is used to indicate a resource. Resources include peripherals
- * and bus masters (but not memory regions). Note items from list should
- * never be changed or removed (only added to at the end of the list).
- */
-typedef u16 sc_rsrc_t;
-
-/* This type is used to indicate a control.  */
-typedef u8 sc_ctrl_t;
-
-/*
- * This type is used to indicate a pad. Valid values are SoC specific.
- *
- * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
- */
-typedef u16 sc_pad_t;
-
-#endif /* SC_TYPES_H */
diff --git a/arch/arm/include/asm/arch-imx8/sys_proto.h b/arch/arm/include/asm/arch-imx8/sys_proto.h
index d38f606..e7625c4 100644
--- a/arch/arm/include/asm/arch-imx8/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8/sys_proto.h
@@ -3,7 +3,7 @@
  * Copyright 2018 NXP
  */
 
-#include <asm/arch/sci/sci.h>
+#include <firmware/imx/sci/sci.h>
 #include <asm/mach-imx/sys_proto.h>
 #include <asm/arch/power-domain.h>
 #include <dm/platdata.h>
diff --git a/arch/arm/include/asm/arch-imx8m/ddr.h b/arch/arm/include/asm/arch-imx8m/ddr.h
index 2f76e7d..c14855d 100644
--- a/arch/arm/include/asm/arch-imx8m/ddr.h
+++ b/arch/arm/include/asm/arch-imx8m/ddr.h
@@ -709,7 +709,7 @@ int ddr_init(struct dram_timing_info *timing_info);
 int ddr_cfg_phy(struct dram_timing_info *timing_info);
 void load_lpddr4_phy_pie(void);
 void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num);
-void dram_config_save(struct dram_timing_info *info, unsigned long base);
+void *dram_config_save(struct dram_timing_info *info, unsigned long base);
 void board_dram_ecc_scrub(void);
 void ddrc_inline_ecc_scrub(unsigned int start_address,
 			   unsigned int range_address);
diff --git a/arch/arm/include/asm/arch-imx9/clock.h b/arch/arm/include/asm/arch-imx9/clock.h
index 336d861..1169ffd 100644
--- a/arch/arm/include/asm/arch-imx9/clock.h
+++ b/arch/arm/include/asm/arch-imx9/clock.h
@@ -205,6 +205,12 @@ struct clk_root_map {
 	u32 mux_type;
 };
 
+struct imx_clk_setting {
+	u32 clk_root;
+	enum ccm_clk_src src;
+	u32 div;
+};
+
 int clock_init(void);
 u32 get_clk_src_rate(enum ccm_clk_src source);
 u32 get_lpuart_clk(void);
diff --git a/arch/arm/include/asm/arch-imx9/ddr.h b/arch/arm/include/asm/arch-imx9/ddr.h
index 62e6f7d..2b22f3a 100644
--- a/arch/arm/include/asm/arch-imx9/ddr.h
+++ b/arch/arm/include/asm/arch-imx9/ddr.h
@@ -13,9 +13,21 @@
 #define DDR_PHY_BASE			0x4E100000
 #define DDRMIX_BLK_CTRL_BASE		0x4E010000
 
+#define REG_DDR_SDRAM_MD_CNTL	(DDR_CTL_BASE + 0x120)
+#define REG_DDR_CS0_BNDS        (DDR_CTL_BASE + 0x0)
+#define REG_DDR_CS1_BNDS        (DDR_CTL_BASE + 0x8)
 #define REG_DDRDSR_2			(DDR_CTL_BASE + 0xB24)
+#define REG_DDR_TIMING_CFG_0	(DDR_CTL_BASE + 0x104)
 #define REG_DDR_SDRAM_CFG		(DDR_CTL_BASE + 0x110)
+#define REG_DDR_TIMING_CFG_4	(DDR_CTL_BASE + 0x160)
 #define REG_DDR_DEBUG_19		(DDR_CTL_BASE + 0xF48)
+#define REG_DDR_SDRAM_CFG_3	(DDR_CTL_BASE + 0x260)
+#define REG_DDR_SDRAM_CFG_4	(DDR_CTL_BASE + 0x264)
+#define REG_DDR_SDRAM_MD_CNTL_2	(DDR_CTL_BASE + 0x270)
+#define REG_DDR_SDRAM_MPR4	(DDR_CTL_BASE + 0x28C)
+#define REG_DDR_SDRAM_MPR5	(DDR_CTL_BASE + 0x290)
+
+#define REG_DDR_ERR_EN		(DDR_CTL_BASE + 0x1000)
 
 #define SRC_BASE_ADDR			(0x44460000)
 #define SRC_DPHY_BASE_ADDR		(SRC_BASE_ADDR + 0x1400)
@@ -50,6 +62,12 @@ struct dram_cfg_param {
 	unsigned int val;
 };
 
+struct dram_fsp_cfg {
+	struct dram_cfg_param ddrc_cfg[20];
+	struct dram_cfg_param mr_cfg[10];
+	unsigned int bypass;
+};
+
 struct dram_fsp_msg {
 	unsigned int drate;
 	enum fw_type fw_type;
@@ -61,6 +79,9 @@ struct dram_timing_info {
 	/* umctl2 config */
 	struct dram_cfg_param *ddrc_cfg;
 	unsigned int ddrc_cfg_num;
+	/* fsp config */
+	struct dram_fsp_cfg *fsp_cfg;
+	unsigned int fsp_cfg_num;
 	/* ddrphy config */
 	struct dram_cfg_param *ddrphy_cfg;
 	unsigned int ddrphy_cfg_num;
@@ -84,7 +105,7 @@ int ddr_init(struct dram_timing_info *timing_info);
 int ddr_cfg_phy(struct dram_timing_info *timing_info);
 void load_lpddr4_phy_pie(void);
 void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num);
-void dram_config_save(struct dram_timing_info *info, unsigned long base);
+void *dram_config_save(struct dram_timing_info *info, unsigned long base);
 void board_dram_ecc_scrub(void);
 void ddrc_inline_ecc_scrub(unsigned int start_address,
 			   unsigned int range_address);
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h b/arch/arm/include/asm/arch-imx9/imx-regs.h
index 065fd1f..76d241e 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -48,6 +48,9 @@
 #define BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII        (0x1 << 1)
 #define BCTRL_GPR_ENET_QOS_CLK_GEN_EN            (0x1 << 0)
 
+#define MARKETING_GRADING_MASK	GENMASK(5, 4)
+#define SPEED_GRADING_MASK	GENMASK(11, 6)
+
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
 #include <asm/types.h>
 #include <stdbool.h>
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
index 2eacddb..85d9ca6 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -82,7 +82,17 @@ struct bd_info;
 
 #define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP))
 
-#define is_imx93() (is_cpu_type(MXC_CPU_IMX93))
+#define is_imx93() (is_cpu_type(MXC_CPU_IMX93) || is_cpu_type(MXC_CPU_IMX9331) || \
+	is_cpu_type(MXC_CPU_IMX9332) || is_cpu_type(MXC_CPU_IMX9351) || \
+	is_cpu_type(MXC_CPU_IMX9322) || is_cpu_type(MXC_CPU_IMX9321) || \
+	is_cpu_type(MXC_CPU_IMX9312) || is_cpu_type(MXC_CPU_IMX9311))
+#define is_imx9351() (is_cpu_type(MXC_CPU_IMX9351))
+#define is_imx9332() (is_cpu_type(MXC_CPU_IMX9332))
+#define is_imx9331() (is_cpu_type(MXC_CPU_IMX9331))
+#define is_imx9322() (is_cpu_type(MXC_CPU_IMX9322))
+#define is_imx9321() (is_cpu_type(MXC_CPU_IMX9321))
+#define is_imx9312() (is_cpu_type(MXC_CPU_IMX9312))
+#define is_imx9311() (is_cpu_type(MXC_CPU_IMX9311))
 
 #define is_imxrt1020() (is_cpu_type(MXC_CPU_IMXRT1020))
 #define is_imxrt1050() (is_cpu_type(MXC_CPU_IMXRT1050))
diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c
index b65bf87..69ed575 100644
--- a/arch/arm/mach-imx/cmd_dek.c
+++ b/arch/arm/mach-imx/cmd_dek.c
@@ -17,7 +17,7 @@
 #include <mapmem.h>
 #include <tee.h>
 #ifdef CONFIG_IMX_SECO_DEK_ENCAP
-#include <asm/arch/sci/sci.h>
+#include <firmware/imx/sci/sci.h>
 #include <asm/mach-imx/image.h>
 #endif
 #include <cpu_func.h>
diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c
index 5a4d39c..9addb82 100644
--- a/arch/arm/mach-imx/imx8/ahab.c
+++ b/arch/arm/mach-imx/imx8/ahab.c
@@ -9,7 +9,7 @@
 #include <log.h>
 #include <asm/global_data.h>
 #include <asm/io.h>
-#include <asm/arch/sci/sci.h>
+#include <firmware/imx/sci/sci.h>
 #include <asm/mach-imx/sys_proto.h>
 #include <asm/arch-imx/cpu.h>
 #include <asm/arch/sys_proto.h>
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index 99772f6..7b292c07 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -19,7 +19,7 @@
 #include <errno.h>
 #include <spl.h>
 #include <thermal.h>
-#include <asm/arch/sci/sci.h>
+#include <firmware/imx/sci/sci.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch-imx/cpu.h>
 #include <asm/armv8/cpu.h>
diff --git a/arch/arm/mach-imx/imx8/fdt.c b/arch/arm/mach-imx/imx8/fdt.c
index a132ce2..02b3ee5 100644
--- a/arch/arm/mach-imx/imx8/fdt.c
+++ b/arch/arm/mach-imx/imx8/fdt.c
@@ -5,7 +5,7 @@
 
 #include <common.h>
 #include <log.h>
-#include <asm/arch/sci/sci.h>
+#include <firmware/imx/sci/sci.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/global_data.h>
 #include <dm/ofnode.h>
diff --git a/arch/arm/mach-imx/imx8/iomux.c b/arch/arm/mach-imx/imx8/iomux.c
index 9c3cfbf..e4f7651 100644
--- a/arch/arm/mach-imx/imx8/iomux.c
+++ b/arch/arm/mach-imx/imx8/iomux.c
@@ -8,7 +8,7 @@
 #include <asm/global_data.h>
 #include <asm/io.h>
 #include <asm/arch/iomux.h>
-#include <asm/arch/sci/sci.h>
+#include <firmware/imx/sci/sci.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
diff --git a/arch/arm/mach-imx/imx8/misc.c b/arch/arm/mach-imx/imx8/misc.c
index de19955..0ce3036 100644
--- a/arch/arm/mach-imx/imx8/misc.c
+++ b/arch/arm/mach-imx/imx8/misc.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 #include <common.h>
 #include <log.h>
-#include <asm/arch/sci/sci.h>
+#include <firmware/imx/sci/sci.h>
 #include <asm/mach-imx/sys_proto.h>
 #include <imx_sip.h>
 #include <linux/arm-smccc.h>
diff --git a/arch/arm/mach-imx/imx8/snvs_security_sc.c b/arch/arm/mach-imx/imx8/snvs_security_sc.c
index 507b5b4..d7b20a1 100644
--- a/arch/arm/mach-imx/imx8/snvs_security_sc.c
+++ b/arch/arm/mach-imx/imx8/snvs_security_sc.c
@@ -15,7 +15,7 @@
 #include <log.h>
 #include <stddef.h>
 #include <common.h>
-#include <asm/arch/sci/sci.h>
+#include <firmware/imx/sci/sci.h>
 #include <asm/arch-imx8/imx8-pins.h>
 #include <asm/arch-imx8/snvs_security_sc.h>
 #include <asm/global_data.h>
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 5a4f835..5ffdcab 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -671,6 +671,7 @@ int spl_mmc_emmc_boot_partition(struct mmc *mmc)
 		/* Log entries with 1 parameter, skip 1 */
 		case 0x80: /* Start to perform the device initialization */
 		case 0x81: /* The boot device initialization completes */
+		case 0x82: /* Starts to execute boot device driver pre-config */
 		case 0x8f: /* The boot device initialization fails */
 		case 0x90: /* Start to read data from boot device */
 		case 0x91: /* Reading data from boot device completes */
@@ -1429,79 +1430,6 @@ int arch_misc_init(void)
 }
 #endif
 
-void imx_tmu_arch_init(void *reg_base)
-{
-	if (is_imx8mm() || is_imx8mn()) {
-		/* Load TCALIV and TASR from fuses */
-		struct ocotp_regs *ocotp =
-			(struct ocotp_regs *)OCOTP_BASE_ADDR;
-		struct fuse_bank *bank = &ocotp->bank[3];
-		struct fuse_bank3_regs *fuse =
-			(struct fuse_bank3_regs *)bank->fuse_regs;
-
-		u32 tca_rt, tca_hr, tca_en;
-		u32 buf_vref, buf_slope;
-
-		tca_rt = fuse->ana0 & 0xFF;
-		tca_hr = (fuse->ana0 & 0xFF00) >> 8;
-		tca_en = (fuse->ana0 & 0x2000000) >> 25;
-
-		buf_vref = (fuse->ana0 & 0x1F00000) >> 20;
-		buf_slope = (fuse->ana0 & 0xF0000) >> 16;
-
-		writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
-		writel((tca_en << 31) | (tca_hr << 16) | tca_rt,
-		       (ulong)reg_base + 0x30);
-	}
-#ifdef CONFIG_IMX8MP
-	/* Load TCALIV0/1/m40 and TRIM from fuses */
-	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
-	struct fuse_bank *bank = &ocotp->bank[38];
-	struct fuse_bank38_regs *fuse =
-		(struct fuse_bank38_regs *)bank->fuse_regs;
-	struct fuse_bank *bank2 = &ocotp->bank[39];
-	struct fuse_bank39_regs *fuse2 =
-		(struct fuse_bank39_regs *)bank2->fuse_regs;
-	u32 buf_vref, buf_slope, bjt_cur, vlsb, bgr;
-	u32 reg;
-	u32 tca40[2], tca25[2], tca105[2];
-
-	/* For blank sample */
-	if (!fuse->ana_trim2 && !fuse->ana_trim3 &&
-	    !fuse->ana_trim4 && !fuse2->ana_trim5) {
-		/* Use a default 25C binary codes */
-		tca25[0] = 1596;
-		tca25[1] = 1596;
-		writel(tca25[0], (ulong)reg_base + 0x30);
-		writel(tca25[1], (ulong)reg_base + 0x34);
-		return;
-	}
-
-	buf_vref = (fuse->ana_trim2 & 0xc0) >> 6;
-	buf_slope = (fuse->ana_trim2 & 0xF00) >> 8;
-	bjt_cur = (fuse->ana_trim2 & 0xF000) >> 12;
-	bgr = (fuse->ana_trim2 & 0xF0000) >> 16;
-	vlsb = (fuse->ana_trim2 & 0xF00000) >> 20;
-	writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
-
-	reg = (bgr << 28) | (bjt_cur << 20) | (vlsb << 12) | (1 << 7);
-	writel(reg, (ulong)reg_base + 0x3c);
-
-	tca40[0] = (fuse->ana_trim3 & 0xFFF0000) >> 16;
-	tca25[0] = (fuse->ana_trim3 & 0xF0000000) >> 28;
-	tca25[0] |= ((fuse->ana_trim4 & 0xFF) << 4);
-	tca105[0] = (fuse->ana_trim4 & 0xFFF00) >> 8;
-	tca40[1] = (fuse->ana_trim4 & 0xFFF00000) >> 20;
-	tca25[1] = fuse2->ana_trim5 & 0xFFF;
-	tca105[1] = (fuse2->ana_trim5 & 0xFFF000) >> 12;
-
-	/* use 25c for 1p calibration */
-	writel(tca25[0] | (tca105[0] << 16), (ulong)reg_base + 0x30);
-	writel(tca25[1] | (tca105[1] << 16), (ulong)reg_base + 0x34);
-	writel(tca40[0] | (tca40[1] << 16), (ulong)reg_base + 0x38);
-#endif
-}
-
 #if defined(CONFIG_SPL_BUILD)
 #if defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN)
 bool serror_need_skip = true;
diff --git a/arch/arm/mach-imx/imx8ulp/Kconfig b/arch/arm/mach-imx/imx8ulp/Kconfig
index c1c1aa0..49ea252 100644
--- a/arch/arm/mach-imx/imx8ulp/Kconfig
+++ b/arch/arm/mach-imx/imx8ulp/Kconfig
@@ -1,5 +1,10 @@
 if ARCH_IMX8ULP
 
+config AHAB_BOOT
+	bool "Support i.MX8ULP AHAB features"
+	help
+	  This option enables the support for AHAB secure boot.
+
 config IMX8ULP
 	bool
 
diff --git a/arch/arm/mach-imx/imx8ulp/Makefile b/arch/arm/mach-imx/imx8ulp/Makefile
index 2c9938f..f7692cf 100644
--- a/arch/arm/mach-imx/imx8ulp/Makefile
+++ b/arch/arm/mach-imx/imx8ulp/Makefile
@@ -5,6 +5,7 @@
 
 obj-y += lowlevel_init.o
 obj-y += soc.o clock.o iomux.o pcc.o cgc.o rdc.o
+obj-$(CONFIG_AHAB_BOOT) += ahab.o
 
 ifeq ($(CONFIG_SPL_BUILD),y)
 obj-y += upower/
diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig
index c06102b..c51f80f 100644
--- a/arch/arm/mach-imx/imx9/Kconfig
+++ b/arch/arm/mach-imx/imx9/Kconfig
@@ -5,6 +5,11 @@ config AHAB_BOOT
     help
     This option enables the support for AHAB secure boot.
 
+config IMX9_LOW_DRIVE_MODE
+    bool "Configure to i.MX9 low drive mode"
+    help
+    This option enables the settings for iMX9 low drive mode.
+
 config IMX9
 	bool
 	select HAS_CAAM
diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c
index 04f3116..a7eccca 100644
--- a/arch/arm/mach-imx/imx9/clock.c
+++ b/arch/arm/mach-imx/imx9/clock.c
@@ -26,6 +26,7 @@ static struct anatop_reg *ana_regs = (struct anatop_reg *)ANATOP_BASE_ADDR;
 static struct imx_intpll_rate_table imx9_intpll_tbl[] = {
 	INT_PLL_RATE(1800000000U, 1, 150, 2), /* 1.8Ghz */
 	INT_PLL_RATE(1700000000U, 1, 141, 2), /* 1.7Ghz */
+	INT_PLL_RATE(1500000000U, 1, 125, 2), /* 1.5Ghz */
 	INT_PLL_RATE(1400000000U, 1, 175, 3), /* 1.4Ghz */
 	INT_PLL_RATE(1000000000U, 1, 166, 4), /* 1000Mhz */
 	INT_PLL_RATE(900000000U, 1, 150, 4), /* 900Mhz */
@@ -35,8 +36,11 @@ static struct imx_fracpll_rate_table imx9_fracpll_tbl[] = {
 	FRAC_PLL_RATE(1000000000U, 1, 166, 4, 2, 3), /* 1000Mhz */
 	FRAC_PLL_RATE(933000000U, 1, 155, 4, 1, 2), /* 933Mhz */
 	FRAC_PLL_RATE(700000000U, 1, 145, 5, 5, 6), /* 700Mhz */
+	FRAC_PLL_RATE(484000000U, 1, 121, 6, 0, 1),
+	FRAC_PLL_RATE(445333333U, 1, 167, 9, 0, 1),
 	FRAC_PLL_RATE(466000000U, 1, 155, 8, 1, 3), /* 466Mhz */
 	FRAC_PLL_RATE(400000000U, 1, 200, 12, 0, 1), /* 400Mhz */
+	FRAC_PLL_RATE(300000000U, 1, 150, 12, 0, 1),
 };
 
 /* return in khz */
@@ -202,6 +206,9 @@ int configure_intpll(enum ccm_clk_src pll, u32 freq)
 		return -EPERM;
 	}
 
+	/* Clear PLL HW CTRL SEL */
+	setbits_le32(&reg->ctrl.reg_clr, PLL_CTRL_HW_CTRL_SEL);
+
 	/* Bypass the PLL to ref */
 	writel(PLL_CTRL_CLKMUX_BYPASS, &reg->ctrl.reg_set);
 
@@ -570,7 +577,7 @@ u32 imx_get_i2cclk(u32 i2c_num)
 	if (i2c_num > 7)
 		return -EINVAL;
 
-	return ccm_clk_root_get_rate(LPUART1_CLK_ROOT + i2c_num);
+	return ccm_clk_root_get_rate(LPI2C1_CLK_ROOT + i2c_num);
 }
 
 u32 get_lpuart_clk(void)
@@ -594,21 +601,27 @@ void init_uart_clk(u32 index)
 
 void init_clk_usdhc(u32 index)
 {
-	/* 400 Mhz */
+	u32 div;
+
+	if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE))
+		div = 3; /* 266.67 Mhz */
+	else
+		div = 2; /* 400 Mhz */
+
 	switch (index) {
 	case 0:
 		ccm_lpcg_on(CCGR_USDHC1, 0);
-		ccm_clk_root_cfg(USDHC1_CLK_ROOT, SYS_PLL_PFD1, 2);
+		ccm_clk_root_cfg(USDHC1_CLK_ROOT, SYS_PLL_PFD1, div);
 		ccm_lpcg_on(CCGR_USDHC1, 1);
 		break;
 	case 1:
 		ccm_lpcg_on(CCGR_USDHC2, 0);
-		ccm_clk_root_cfg(USDHC2_CLK_ROOT, SYS_PLL_PFD1, 2);
+		ccm_clk_root_cfg(USDHC2_CLK_ROOT, SYS_PLL_PFD1, div);
 		ccm_lpcg_on(CCGR_USDHC2, 1);
 		break;
 	case 2:
 		ccm_lpcg_on(CCGR_USDHC3, 0);
-		ccm_clk_root_cfg(USDHC3_CLK_ROOT, SYS_PLL_PFD1, 2);
+		ccm_clk_root_cfg(USDHC3_CLK_ROOT, SYS_PLL_PFD1, div);
 		ccm_lpcg_on(CCGR_USDHC3, 1);
 		break;
 	default:
@@ -635,6 +648,9 @@ void dram_pll_init(ulong pll_val)
 void dram_enable_bypass(ulong clk_val)
 {
 	switch (clk_val) {
+	case MHZ(625):
+		ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD2, 1);
+		break;
 	case MHZ(400):
 		ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD1, 2);
 		break;
@@ -670,42 +686,95 @@ void set_arm_clk(ulong freq)
 {
 	/* Increase ARM clock to 1.7Ghz */
 	ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_CCM);
-	configure_intpll(ARM_PLL_CLK, 1700000000);
+	configure_intpll(ARM_PLL_CLK, freq);
 	ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_PLL);
 }
 
+void set_arm_core_max_clk(void)
+{
+	/* Increase ARM clock to max rate according to speed grade */
+	u32 speed = get_cpu_speed_grade_hz();
+
+	set_arm_clk(speed);
+}
+
 #endif
 
-int clock_init(void)
-{
-	int i;
+#if IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)
+struct imx_clk_setting imx_clk_settings[] = {
+	/* Set A55 clk to 500M */
+	{ARM_A55_CLK_ROOT, SYS_PLL_PFD0, 2},
+	/* Set A55 periphal to 200M */
+	{ARM_A55_PERIPH_CLK_ROOT, SYS_PLL_PFD1, 4},
+	/* Set A55 mtr bus to 133M */
+	{ARM_A55_MTR_BUS_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
 
+	/* Sentinel to 133M */
+	{SENTINEL_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
+	/* Bus_wakeup to 133M */
+	{BUS_WAKEUP_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
+	/* Bus_AON to 133M */
+	{BUS_AON_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
+	/* M33 to 133M */
+	{M33_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
+	/* WAKEUP_AXI to 200M  */
+	{WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD1, 4},
+	/* SWO TRACE to 133M */
+	{SWO_TRACE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
+	/* M33 systetick to 24M */
+	{M33_SYSTICK_CLK_ROOT, OSC_24M_CLK, 1},
+	/* NIC to 250M */
+	{NIC_CLK_ROOT, SYS_PLL_PFD0, 4},
+	/* NIC_APB to 133M */
+	{NIC_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3}
+};
+#else
+struct imx_clk_setting imx_clk_settings[] = {
+	/*
+	 * Set A55 clk to 500M. This clock root is normally used as intermediate
+	 * clock source for A55 core/DSU when doing ARM PLL reconfig. set it to
+	 * 500MHz(LD mode frequency) should be ok.
+	 */
+	{ARM_A55_CLK_ROOT, SYS_PLL_PFD0, 2},
 	/* Set A55 periphal to 333M */
-	ccm_clk_root_cfg(ARM_A55_PERIPH_CLK_ROOT, SYS_PLL_PFD0, 3);
+	{ARM_A55_PERIPH_CLK_ROOT, SYS_PLL_PFD0, 3},
 	/* Set A55 mtr bus to 133M */
-	ccm_clk_root_cfg(ARM_A55_MTR_BUS_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
-
+	{ARM_A55_MTR_BUS_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
 	/* Sentinel to 200M */
-	ccm_clk_root_cfg(SENTINEL_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2);
+	{SENTINEL_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2},
 	/* Bus_wakeup to 133M */
-	ccm_clk_root_cfg(BUS_WAKEUP_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+	{BUS_WAKEUP_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
 	/* Bus_AON to 133M */
-	ccm_clk_root_cfg(BUS_AON_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+	{BUS_AON_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
 	/* M33 to 200M */
-	ccm_clk_root_cfg(M33_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2);
+	{M33_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2},
 	/*
 	 * WAKEUP_AXI to 312.5M, because of FEC only can support to 320M for
 	 * generating MII clock at 2.5M
 	 */
-	ccm_clk_root_cfg(WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD2, 2);
+	{WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD2, 2},
 	/* SWO TRACE to 133M */
-	ccm_clk_root_cfg(SWO_TRACE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
-	/* M33 systetick to 133M */
-	ccm_clk_root_cfg(M33_SYSTICK_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+	{SWO_TRACE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
+	/* M33 systetick to 24M */
+	{M33_SYSTICK_CLK_ROOT, OSC_24M_CLK, 1},
 	/* NIC to 400M */
-	ccm_clk_root_cfg(NIC_CLK_ROOT, SYS_PLL_PFD1, 2);
+	{NIC_CLK_ROOT, SYS_PLL_PFD1, 2},
 	/* NIC_APB to 133M */
-	ccm_clk_root_cfg(NIC_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+	{NIC_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3}
+};
+#endif
+
+int clock_init(void)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(imx_clk_settings); i++) {
+		ccm_clk_root_cfg(imx_clk_settings[i].clk_root,
+				 imx_clk_settings[i].src, imx_clk_settings[i].div);
+	}
+
+	if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE))
+		set_arm_clk(MHZ(900));
 
 	/* allow for non-secure access */
 	for (i = 0; i < OSCPLL_END; i++)
diff --git a/arch/arm/mach-imx/imx9/imx_bootaux.c b/arch/arm/mach-imx/imx9/imx_bootaux.c
index 3b6662a..256e6fa 100644
--- a/arch/arm/mach-imx/imx9/imx_bootaux.c
+++ b/arch/arm/mach-imx/imx9/imx_bootaux.c
@@ -34,17 +34,13 @@ int arch_auxiliary_core_down(u32 core_id)
 int arch_auxiliary_core_up(u32 core_id, ulong addr)
 {
 	struct arm_smccc_res res;
-	u32 stack, pc;
 
 	if (!addr)
 		return -EINVAL;
 
-	stack = *(u32 *)addr;
-	pc = *(u32 *)(addr + 4);
+	printf("## Starting auxiliary core addr = 0x%08lX...\n", addr);
 
-	printf("## Starting auxiliary core stack = 0x%08X, pc = 0x%08X...\n", stack, pc);
-
-	arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0,
+	arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, addr, 0,
 		      0, 0, 0, 0, &res);
 
 	return 0;
@@ -129,5 +125,5 @@ U_BOOT_CMD(
 	"Start auxiliary core",
 	"<address> [<core>]\n"
 	"   - start auxiliary core [<core>] (default 0),\n"
-	"     at address <address>\n"
+	"     at address <address> of auxiliary core view\n"
 );
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 252663a..64e8ac6 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -19,17 +19,24 @@
 #include <asm/mach-imx/boot_mode.h>
 #include <asm/mach-imx/syscounter.h>
 #include <asm/armv8/mmu.h>
+#include <dm/device.h>
+#include <dm/device_compat.h>
 #include <dm/uclass.h>
 #include <env.h>
 #include <env_internal.h>
 #include <errno.h>
 #include <fdt_support.h>
+#include <imx_thermal.h>
 #include <linux/bitops.h>
+#include <linux/bitfield.h>
+#include <linux/delay.h>
+#include <thermal.h>
 #include <asm/setup.h>
 #include <asm/bootm.h>
 #include <asm/arch-imx/cpu.h>
 #include <asm/mach-imx/s400_api.h>
-#include <linux/delay.h>
+#include <fuse.h>
+#include <asm/arch/ddr.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -38,19 +45,17 @@ struct rom_api *g_rom_api = (struct rom_api *)0x1980;
 #ifdef CONFIG_ENV_IS_IN_MMC
 __weak int board_mmc_get_env_dev(int devno)
 {
-	return devno; }
+	return devno;
+}
 
 int mmc_get_env_dev(void)
 {
-	volatile gd_t *pgd = gd;
 	int ret;
 	u32 boot;
 	u16 boot_type;
 	u8 boot_instance;
 
-	ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
-					  ((uintptr_t)&boot) ^ QUERY_BT_DEV);
-	set_gd(pgd);
+	ret = rom_api_query_boot_infor(QUERY_BT_DEV, &boot);
 
 	if (ret != ROM_API_OKAY) {
 		puts("ROMAPI: failure at query_boot_info\n");
@@ -70,6 +75,82 @@ int mmc_get_env_dev(void)
 }
 #endif
 
+/*
+ * SPEED_GRADE[5:4]    SPEED_GRADE[3:0]    MHz
+ * xx                  0000                2300
+ * xx                  0001                2200
+ * xx                  0010                2100
+ * xx                  0011                2000
+ * xx                  0100                1900
+ * xx                  0101                1800
+ * xx                  0110                1700
+ * xx                  0111                1600
+ * xx                  1000                1500
+ * xx                  1001                1400
+ * xx                  1010                1300
+ * xx                  1011                1200
+ * xx                  1100                1100
+ * xx                  1101                1000
+ * xx                  1110                900
+ * xx                  1111                800
+ */
+u32 get_cpu_speed_grade_hz(void)
+{
+	u32 speed, max_speed;
+	u32 val;
+
+	fuse_read(2, 3, &val);
+	val = FIELD_GET(SPEED_GRADING_MASK, val) & 0xF;
+
+	speed = MHZ(2300) - val * MHZ(100);
+
+	if (is_imx93())
+		max_speed = MHZ(1700);
+
+	/* In case the fuse of speed grade not programmed */
+	if (speed > max_speed)
+		speed = max_speed;
+
+	return speed;
+}
+
+/*
+ * `00` - Consumer 0C to 95C
+ * `01` - Ext. Consumer -20C to 105C
+ * `10` - Industrial -40C to 105C
+ * `11` - Automotive -40C to 125C
+ */
+u32 get_cpu_temp_grade(int *minc, int *maxc)
+{
+	u32 val;
+
+	fuse_read(2, 3, &val);
+	val = FIELD_GET(MARKETING_GRADING_MASK, val);
+
+	if (minc && maxc) {
+		if (val == TEMP_AUTOMOTIVE) {
+			*minc = -40;
+			*maxc = 125;
+		} else if (val == TEMP_INDUSTRIAL) {
+			*minc = -40;
+			*maxc = 105;
+		} else if (val == TEMP_EXTCOMMERCIAL) {
+			if (is_imx93()) {
+				/* imx93 only has extended industrial*/
+				*minc = -40;
+				*maxc = 125;
+			} else {
+				*minc = -20;
+				*maxc = 105;
+			}
+		} else {
+			*minc = 0;
+			*maxc = 95;
+		}
+	}
+	return val;
+}
+
 static void set_cpu_info(struct sentinel_get_info_data *info)
 {
 	gd->arch.soc_rev = info->soc;
@@ -77,11 +158,34 @@ static void set_cpu_info(struct sentinel_get_info_data *info)
 	memcpy((void *)&gd->arch.uid, &info->uid, 4 * sizeof(u32));
 }
 
+static u32 get_cpu_variant_type(u32 type)
+{
+	/* word 19 */
+	u32 val = readl((ulong)FSB_BASE_ADDR + 0x8000 + (19 << 2));
+	u32 val2 = readl((ulong)FSB_BASE_ADDR + 0x8000 + (20 << 2));
+	bool npu_disable = !!(val & BIT(13));
+	bool core1_disable = !!(val & BIT(15));
+	u32 pack_9x9_fused = BIT(4) | BIT(17) | BIT(19) | BIT(24);
+
+	if ((val2 & pack_9x9_fused) == pack_9x9_fused)
+		type = MXC_CPU_IMX9322;
+
+	if (npu_disable && core1_disable)
+		return type + 3;
+	else if (npu_disable)
+		return type + 2;
+	else if (core1_disable)
+		return type + 1;
+
+	return type;
+}
+
 u32 get_cpu_rev(void)
 {
 	u32 rev = (gd->arch.soc_rev >> 24) - 0xa0;
 
-	return (MXC_CPU_IMX93 << 12) | (CHIP_REV_1_0 + rev);
+	return (get_cpu_variant_type(MXC_CPU_IMX93) << 12) |
+		(CHIP_REV_1_0 + rev);
 }
 
 #define UNLOCK_WORD 0xD928C520 /* unlock word */
@@ -180,21 +284,216 @@ static struct mm_region imx93_mem_map[] = {
 
 struct mm_region *mem_map = imx93_mem_map;
 
+static unsigned int imx9_find_dram_entry_in_mem_map(void)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(imx93_mem_map); i++)
+		if (imx93_mem_map[i].phys == CFG_SYS_SDRAM_BASE)
+			return i;
+
+	hang();	/* Entry not found, this must never happen. */
+}
+
+void enable_caches(void)
+{
+	/* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch
+	 * If OPTEE does not run, still update the MMU table according to dram banks structure
+	 * to set correct dram size from board_phys_sdram_size
+	 */
+	int i = 0;
+	/*
+	 * please make sure that entry initial value matches
+	 * imx93_mem_map for DRAM1
+	 */
+	int entry = imx9_find_dram_entry_in_mem_map();
+	u64 attrs = imx93_mem_map[entry].attrs;
+
+	while (i < CONFIG_NR_DRAM_BANKS &&
+	       entry < ARRAY_SIZE(imx93_mem_map)) {
+		if (gd->bd->bi_dram[i].start == 0)
+			break;
+		imx93_mem_map[entry].phys = gd->bd->bi_dram[i].start;
+		imx93_mem_map[entry].virt = gd->bd->bi_dram[i].start;
+		imx93_mem_map[entry].size = gd->bd->bi_dram[i].size;
+		imx93_mem_map[entry].attrs = attrs;
+		debug("Added memory mapping (%d): %llx %llx\n", entry,
+		      imx93_mem_map[entry].phys, imx93_mem_map[entry].size);
+		i++; entry++;
+	}
+
+	icache_enable();
+	dcache_enable();
+}
+
+__weak int board_phys_sdram_size(phys_size_t *size)
+{
+	phys_size_t start, end;
+	phys_size_t val;
+
+	if (!size)
+		return -EINVAL;
+
+	val = readl(REG_DDR_CS0_BNDS);
+	start = (val >> 16) << 24;
+	end   = (val & 0xFFFF);
+	end   = end ? end + 1 : 0;
+	end   = end << 24;
+	*size = end - start;
+
+	val = readl(REG_DDR_CS1_BNDS);
+	start = (val >> 16) << 24;
+	end   = (val & 0xFFFF);
+	end   = end ? end + 1 : 0;
+	end   = end << 24;
+	*size += end - start;
+
+	return 0;
+}
+
 int dram_init(void)
 {
-	gd->ram_size = PHYS_SDRAM_SIZE;
+	phys_size_t sdram_size;
+	int ret;
+
+	ret = board_phys_sdram_size(&sdram_size);
+	if (ret)
+		return ret;
+
+	/* rom_pointer[1] contains the size of TEE occupies */
+	if (rom_pointer[1])
+		gd->ram_size = sdram_size - rom_pointer[1];
+	else
+		gd->ram_size = sdram_size;
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	int bank = 0;
+	int ret;
+	phys_size_t sdram_size;
+	phys_size_t sdram_b1_size, sdram_b2_size;
+
+	ret = board_phys_sdram_size(&sdram_size);
+	if (ret)
+		return ret;
+
+	/* Bank 1 can't cross over 4GB space */
+	if (sdram_size > 0x80000000) {
+		sdram_b1_size = 0x80000000;
+		sdram_b2_size = sdram_size - 0x80000000;
+	} else {
+		sdram_b1_size = sdram_size;
+		sdram_b2_size = 0;
+	}
+
+	gd->bd->bi_dram[bank].start = PHYS_SDRAM;
+	if (rom_pointer[1]) {
+		phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
+		phys_size_t optee_size = (size_t)rom_pointer[1];
+
+		gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start;
+		if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) {
+			if (++bank >= CONFIG_NR_DRAM_BANKS) {
+				puts("CONFIG_NR_DRAM_BANKS is not enough\n");
+				return -1;
+			}
+
+			gd->bd->bi_dram[bank].start = optee_start + optee_size;
+			gd->bd->bi_dram[bank].size = PHYS_SDRAM +
+				sdram_b1_size - gd->bd->bi_dram[bank].start;
+		}
+	} else {
+		gd->bd->bi_dram[bank].size = sdram_b1_size;
+	}
+
+	if (sdram_b2_size) {
+		if (++bank >= CONFIG_NR_DRAM_BANKS) {
+			puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n");
+			return -1;
+		}
+		gd->bd->bi_dram[bank].start = 0x100000000UL;
+		gd->bd->bi_dram[bank].size = sdram_b2_size;
+	}
 
 	return 0;
 }
 
+phys_size_t get_effective_memsize(void)
+{
+	int ret;
+	phys_size_t sdram_size;
+	phys_size_t sdram_b1_size;
+
+	ret = board_phys_sdram_size(&sdram_size);
+	if (!ret) {
+		/* Bank 1 can't cross over 4GB space */
+		if (sdram_size > 0x80000000)
+			sdram_b1_size = 0x80000000;
+		else
+			sdram_b1_size = sdram_size;
+
+		if (rom_pointer[1]) {
+			/* We will relocate u-boot to top of dram1. TEE position has two cases:
+			 * 1. At the top of dram1,  Then return the size removed optee size.
+			 * 2. In the middle of dram1, return the size of dram1.
+			 */
+			if ((rom_pointer[0] + rom_pointer[1]) == (PHYS_SDRAM + sdram_b1_size))
+				return ((phys_addr_t)rom_pointer[0] - PHYS_SDRAM);
+		}
+
+		return sdram_b1_size;
+	} else {
+		return PHYS_SDRAM_SIZE;
+	}
+}
+
 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 {
-	mac[0] = 0x1;
-	mac[1] = 0x2;
-	mac[2] = 0x3;
-	mac[3] = 0x4;
-	mac[4] = 0x5;
-	mac[5] = 0x6;
+	u32 val[2] = {};
+	int ret;
+
+	if (dev_id == 0) {
+		ret = fuse_read(39, 3, &val[0]);
+		if (ret)
+			goto err;
+
+		ret = fuse_read(39, 4, &val[1]);
+		if (ret)
+			goto err;
+
+		mac[0] = val[1] >> 8;
+		mac[1] = val[1];
+		mac[2] = val[0] >> 24;
+		mac[3] = val[0] >> 16;
+		mac[4] = val[0] >> 8;
+		mac[5] = val[0];
+
+	} else {
+		ret = fuse_read(39, 5, &val[0]);
+		if (ret)
+			goto err;
+
+		ret = fuse_read(39, 4, &val[1]);
+		if (ret)
+			goto err;
+
+		mac[0] = val[1] >> 24;
+		mac[1] = val[1] >> 16;
+		mac[2] = val[0] >> 24;
+		mac[3] = val[0] >> 16;
+		mac[4] = val[0] >> 8;
+		mac[5] = val[0];
+	}
+
+	debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n",
+	      __func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+	return;
+err:
+	memset(mac, 0, 6);
+	printf("%s: fuse read err: %d\n", __func__, ret);
 }
 
 int print_cpuinfo(void)
@@ -224,6 +523,18 @@ void get_board_serial(struct tag_serialnr *serialnr)
 }
 #endif
 
+static void save_reset_cause(void)
+{
+	struct src_general_regs *src = (struct src_general_regs *)SRC_GLOBAL_RBASE;
+	u32 srsr = readl(&src->srsr);
+
+	/* clear srsr in sec mode */
+	writel(srsr, &src->srsr);
+
+	/* Save value to GPR1 to pass to nonsecure */
+	writel(srsr, &src->gpr[0]);
+}
+
 int arch_cpu_init(void)
 {
 	if (IS_ENABLED(CONFIG_SPL_BUILD)) {
@@ -233,6 +544,9 @@ int arch_cpu_init(void)
 		clock_init();
 
 		trdc_early_init();
+
+		/* Save SRC SRSR to GPR1 and clear it */
+		save_reset_cause();
 	}
 
 	return 0;
@@ -466,3 +780,45 @@ int m33_prepare(void)
 
 	return 0;
 }
+
+int psci_sysreset_get_status(struct udevice *dev, char *buf, int size)
+{
+	static const char *reset_cause[] = {
+		"POR ",
+		"JTAG ",
+		"IPP USER ",
+		"WDOG1 ",
+		"WDOG2 ",
+		"WDOG3 ",
+		"WDOG4 ",
+		"WDOG5 ",
+		"TEMPSENSE ",
+		"CSU ",
+		"JTAG_SW ",
+		"M33_REQ ",
+		"M33_LOCKUP ",
+		"UNK ",
+		"UNK ",
+		"UNK "
+	};
+
+	struct src_general_regs *src = (struct src_general_regs *)SRC_GLOBAL_RBASE;
+	u32 srsr;
+	u32 i;
+	int res;
+
+	srsr = readl(&src->gpr[0]);
+
+	for (i = ARRAY_SIZE(reset_cause); i > 0; i--) {
+		if (srsr & (BIT(i - 1)))
+			break;
+	}
+
+	res = snprintf(buf, size, "Reset Status: %s\n", i ? reset_cause[i - 1] : "unknown reset");
+	if (res < 0) {
+		dev_err(dev, "Could not write reset status message (err = %d)\n", res);
+		return -EIO;
+	}
+
+	return 0;
+}
diff --git a/arch/arm/mach-imx/parse-container.c b/arch/arm/mach-imx/parse-container.c
index a4214d5..f758282 100644
--- a/arch/arm/mach-imx/parse-container.c
+++ b/arch/arm/mach-imx/parse-container.c
@@ -9,7 +9,7 @@
 #include <spl.h>
 #include <asm/mach-imx/image.h>
 #ifdef CONFIG_AHAB_BOOT
-#include <asm/arch/sci/sci.h>
+#include <firmware/imx/sci/sci.h>
 #endif
 
 #define SEC_SECURE_RAM_BASE		0x31800000UL
diff --git a/arch/arm/mach-imx/spl_imx_romapi.c b/arch/arm/mach-imx/spl_imx_romapi.c
index 830d5d1..9164045 100644
--- a/arch/arm/mach-imx/spl_imx_romapi.c
+++ b/arch/arm/mach-imx/spl_imx_romapi.c
@@ -367,7 +367,7 @@ int board_return_to_bootrom(struct spl_image_info *spl_image,
 		printf("USB boot\n");
 		break;
 	default:
-		printf("Unknow (0x%x)\n", bstage);
+		printf("Unknown (0x%x)\n", bstage);
 	}
 
 	if (is_boot_from_stream_device(boot))