diff options
author | Simon Glass <sjg@chromium.org> | 2019-11-14 12:57:36 -0700 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2019-12-02 18:23:14 -0500 |
commit | 6cc915b5fb2e3467b20735b112a7463cc77ec3c3 (patch) | |
tree | 333c09c4aff924b1913865d5f174e47b37217220 /arch | |
parent | 62270f4395f86bd5231fcb9c1710e42be7d67d60 (diff) | |
download | u-boot-6cc915b5fb2e3467b20735b112a7463cc77ec3c3.zip u-boot-6cc915b5fb2e3467b20735b112a7463cc77ec3c3.tar.gz u-boot-6cc915b5fb2e3467b20735b112a7463cc77ec3c3.tar.bz2 |
arm: powerpc: Tidy up code style for cache functions
Remove the unwanted space before the bracket.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/lib/cache-cp15.c | 12 | ||||
-rw-r--r-- | arch/microblaze/cpu/cache.c | 18 |
2 files changed, 17 insertions, 13 deletions
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 47c2239..8ca8e48 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -253,17 +253,17 @@ static void cache_disable(uint32_t cache_bit) #endif #if CONFIG_IS_ENABLED(SYS_ICACHE_OFF) -void icache_enable (void) +void icache_enable(void) { return; } -void icache_disable (void) +void icache_disable(void) { return; } -int icache_status (void) +int icache_status(void) { return 0; /* always off */ } @@ -285,17 +285,17 @@ int icache_status(void) #endif #if CONFIG_IS_ENABLED(SYS_DCACHE_OFF) -void dcache_enable (void) +void dcache_enable(void) { return; } -void dcache_disable (void) +void dcache_disable(void) { return; } -int dcache_status (void) +int dcache_status(void) { return 0; /* always off */ } diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c index eebeb37..9411455 100644 --- a/arch/microblaze/cpu/cache.c +++ b/arch/microblaze/cpu/cache.c @@ -8,7 +8,7 @@ #include <common.h> #include <asm/asm.h> -int dcache_status (void) +int dcache_status(void) { int i = 0; int mask = 0x80; @@ -18,7 +18,7 @@ int dcache_status (void) return i; } -int icache_status (void) +int icache_status(void) { int i = 0; int mask = 0x20; @@ -28,28 +28,32 @@ int icache_status (void) return i; } -void icache_enable (void) { +void icache_enable(void) +{ MSRSET(0x20); } -void icache_disable(void) { +void icache_disable(void) +{ /* we are not generate ICACHE size -> flush whole cache */ flush_cache(0, 32768); MSRCLR(0x20); } -void dcache_enable (void) { +void dcache_enable(void) +{ MSRSET(0x80); } -void dcache_disable(void) { +void dcache_disable(void) +{ #ifdef XILINX_USE_DCACHE flush_cache(0, XILINX_DCACHE_BYTE_SIZE); #endif MSRCLR(0x80); } -void flush_cache (ulong addr, ulong size) +void flush_cache(ulong addr, ulong size) { int i; for (i = 0; i < size; i += 4) |