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author | Dalon Westergreen <dalon.westergreen@intel.com> | 2019-09-27 18:43:24 -0700 |
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committer | Ley Foon Tan <ley.foon.tan@intel.com> | 2020-10-09 17:53:14 +0800 |
commit | 5c0adb0a71f1c52e950edbac642b39d835fff845 (patch) | |
tree | ebe5917a9b2bf8a577257b8bf1c55a727c5b1cae /arch | |
parent | 5bbeaaefec67bd794ea8652a9cada9e5380b6805 (diff) | |
download | u-boot-5c0adb0a71f1c52e950edbac642b39d835fff845.zip u-boot-5c0adb0a71f1c52e950edbac642b39d835fff845.tar.gz u-boot-5c0adb0a71f1c52e950edbac642b39d835fff845.tar.bz2 |
arm: socfpga: arria10: Add qts-filter for Arria10 socfpga
Add a script to process HPS handoff data and generate a header
for inclusion in u-boot specific devicetree addons. The header
should be included in the top level of u-boot.dtsi.
Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Diffstat (limited to 'arch')
-rwxr-xr-x | arch/arm/mach-socfpga/qts-filter-a10.sh | 141 |
1 files changed, 141 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/qts-filter-a10.sh b/arch/arm/mach-socfpga/qts-filter-a10.sh new file mode 100755 index 0000000..57d77e8 --- /dev/null +++ b/arch/arm/mach-socfpga/qts-filter-a10.sh @@ -0,0 +1,141 @@ +#!/bin/bash + +# +# helper function to convert from DOS to Unix, if necessary, and handle +# lines ending in '\'. +# +fix_newlines_in_macros() { + sed -n ':next;s/\r$//;/[^\\]\\$/ {N;s/\\\n//;b next};p' $1 +} + +#filter out only what we need from a10 hps.xml +grep_a10_hps_config() { + egrep "clk_hz|i_clk_mgr|i_io48_pin_mux|AXI_SLAVE|AXI_MASTER" +} + +# +# Process hps.xml +# $1: hps.xml +# $2: Output File +# +process_a10_hps_config() { + hps_xml="$1" + outfile="$2" + + (cat << EOF +// SPDX-License-Identifier: BSD-3-Clause +/* + * Intel Arria 10 SoCFPGA configuration + */ + +#ifndef __SOCFPGA_ARRIA10_CONFIG_H__ +#define __SOCFPGA_ARRIA10_CONFIG_H__ + +EOF + + echo "/* Clocks */" + fix_newlines_in_macros \ + ${hps_xml} | egrep "clk_hz" | + awk -F"'" '{ gsub("\\.","_",$2) ; \ + print "#define" " " toupper($2) " " $4}' | + sed 's/\.[0-9]//' | + sed 's/I_CLK_MGR_//' | + sort + fix_newlines_in_macros \ + ${hps_xml} | egrep "i_clk_mgr_mainpll" | + awk -F"'" '{ gsub("\\.","_",$2) ; \ + print "#define" " " toupper($2) " " $4}' | + sed 's/\.[0-9]//' | + sed 's/I_CLK_MGR_//' | + sort + fix_newlines_in_macros \ + ${hps_xml} | egrep "i_clk_mgr_perpll" | + awk -F"'" '{ gsub("\\.","_",$2) ; \ + print "#define" " " toupper($2) " " $4}' | + sed 's/\.[0-9]//' | + sed 's/I_CLK_MGR_//' | + sort + fix_newlines_in_macros \ + ${hps_xml} | egrep "i_clk_mgr_clkmgr" | + awk -F"'" '{ gsub("\\.","_",$2) ; \ + print "#define" " " toupper($2) " " $4}' | + sed 's/\.[0-9]//' | + sed 's/I_CLK_MGR_//' | + sort + fix_newlines_in_macros \ + ${hps_xml} | egrep "i_clk_mgr_alteragrp" | + awk -F"'" '{ gsub("\\.","_",$2) ; \ + print "#define" " " toupper($2) " " $4}' | + sed 's/\.[0-9]//' | + sed 's/I_CLK_MGR_//' | + sort + echo "#define ALTERAGRP_MPUCLK ((ALTERAGRP_MPUCLK_PERICNT << 16) | \\" + echo " (ALTERAGRP_MPUCLK_MAINCNT))" + echo "#define ALTERAGRP_NOCCLK ((ALTERAGRP_NOCCLK_PERICNT << 16) | \\" + echo " (ALTERAGRP_NOCCLK_MAINCNT))" + + echo + echo "/* Pin Mux Configuration */" + fix_newlines_in_macros \ + ${hps_xml} | egrep "i_io48_pin_mux" | + awk -F"'" '{ gsub("\\.","_",$2) ; \ + print "#define" " " toupper($2) " " $4}' | + sed 's/I_IO48_PIN_MUX_//' | + sed 's/SHARED_3V_IO_GRP_//' | + sed 's/FPGA_INTERFACE_GRP_//' | + sed 's/DEDICATED_IO_GRP_//' | + sed 's/CONFIGURATION_DEDICATED/CONFIG/' | + sort + + echo + echo "/* Bridge Configuration */" + fix_newlines_in_macros \ + ${hps_xml} | egrep "AXI_SLAVE|AXI_MASTER" | + awk -F"'" '{ gsub("\\.","_",$2) ; \ + print "#define" " " toupper($2) " " $4}' | + sed 's/true/1/' | + sed 's/false/0/' | + sort + + echo + echo "/* Voltage Select for Config IO */" + echo "#define CONFIG_IO_BANK_VSEL \\" + echo " (((CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \\" + echo " (CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3))" + + echo + echo "/* Macro for Config IO bit mapping */" + echo -n "#define CONFIG_IO_MACRO(NAME) " + echo "(((NAME ## _RTRIM & 0xff) << 19) | \\" + echo " ((NAME ## _INPUT_BUF_EN & 0x3) << 17) | \\" + echo " ((NAME ## _WK_PU_EN & 0x1) << 16) | \\" + echo " ((NAME ## _PU_SLW_RT & 0x1) << 13) | \\" + echo " ((NAME ## _PU_DRV_STRG & 0xf) << 8) | \\" + echo " ((NAME ## _PD_SLW_RT & 0x1) << 5) | \\" + echo " (NAME ## _PD_DRV_STRG & 0x1f))" + + cat << EOF + +#endif /* __SOCFPGA_ARRIA10_CONFIG_H__ */ +EOF + ) > "${outfile}" +} + +usage() { + echo "$0 [hps_xml] [output_file]" + echo "Process QTS-generated hps.xml into devicetree header." + echo "" + echo " hps_xml - hps.xml file from hps_isw_handoff" + echo " output_file - Output header file for dtsi include" + echo "" +} + +hps_xml="$1" +outfile="$2" + +if [ "$#" -ne 2 ] ; then + usage + exit 1 +fi + +process_a10_hps_config "${hps_xml}" "${outfile}" |