Finish conversion of CONFIG_SYS_CLK_FREQ to Kconfig

In order to finish moving this symbol to Kconfig for all platforms, we
need to do a few more things.  First, for all platforms that define this
to a function, introduce CONFIG_DYNAMIC_SYS_CLK_FREQ, similar to
CONFIG_DYNAMIC_DDR_CLK_FREQ and populate clock_legacy.h.  This entails
also switching all users from CONFIG_SYS_CLK_FREQ to get_board_sys_clk()
and updating a few preprocessor tests.

With that done, all platforms that define a value here can be converted
to Kconfig, and a fall-back of zero is sufficiently safe to use (and
what is used today in cases where code may or may not have this
available).  Make sure that code which calls this function includes
<clock_legacy.h> to get the prototype.

Signed-off-by: Tom Rini <trini@konsulko.com>

20 files changed, 47 insertions, 37 deletions

diff --git a/arch/arc/lib/cpu.c b/arch/arc/lib/cpu.c
index 07f5787..6b21520 100644
--- a/arch/arc/lib/cpu.c
+++ b/arch/arc/lib/cpu.c
@@ -4,6 +4,7 @@
  */
 
 #include <common.h>
+#include <clock_legacy.h>
 #include <init.h>
 #include <malloc.h>
 #include <vsprintf.h>
@@ -18,7 +19,7 @@ int arch_cpu_init(void)
 {
 	timer_init();
 
-	gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
+	gd->cpu_clk = get_board_sys_clk();
 	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 
 	cache_init();
diff --git a/arch/arm/cpu/arm920t/ep93xx/speed.c b/arch/arm/cpu/arm920t/ep93xx/speed.c
index 51e9dda..8dd3904 100644
--- a/arch/arm/cpu/arm920t/ep93xx/speed.c
+++ b/arch/arm/cpu/arm920t/ep93xx/speed.c
@@ -6,12 +6,13 @@
  */
 
 #include <common.h>
+#include <clock_legacy.h>
 #include <asm/arch/ep93xx.h>
 #include <asm/io.h>
 #include <div64.h>
 
 /*
- * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
+ * get_board_sys_clk() should be defined as the input frequency of the PLL.
  *
  * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
  * the specified bus in HZ.
@@ -20,14 +21,14 @@
 /*
  * return the PLL output frequency
  *
- * PLL rate = CONFIG_SYS_CLK_FREQ * (X1FBD + 1) * (X2FBD + 1)
+ * PLL rate = get_board_sys_clk() * (X1FBD + 1) * (X2FBD + 1)
  * / (X2IPD + 1) / 2^PS
  */
 static ulong get_PLLCLK(uint32_t *pllreg)
 {
 	uint8_t i;
 	const uint32_t clkset = readl(pllreg);
-	uint64_t rate = CONFIG_SYS_CLK_FREQ;
+	uint64_t rate = get_board_sys_clk();
 	rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1;
 	rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1;
 	do_div(rate, (clkset  & 0x1f) + 1);			/* X2IPD */
@@ -87,9 +88,9 @@ ulong get_UCLK(void)
 
 	const uint32_t value = readl(&syscon->pwrcnt);
 	if (value & SYSCON_PWRCNT_UART_BAUD)
-		uclk_rate = CONFIG_SYS_CLK_FREQ;
+		uclk_rate = get_board_sys_clk();
 	else
-		uclk_rate = CONFIG_SYS_CLK_FREQ / 2;
+		uclk_rate = get_board_sys_clk() / 2;
 
 	return uclk_rate;
 }
diff --git a/arch/arm/cpu/arm920t/imx/speed.c b/arch/arm/cpu/arm920t/imx/speed.c
index eff6113..c19206a 100644
--- a/arch/arm/cpu/arm920t/imx/speed.c
+++ b/arch/arm/cpu/arm920t/imx/speed.c
@@ -7,13 +7,14 @@
 
 #include <common.h>
 #if defined (CONFIG_IMX)
+#include <clock_legacy.h>
 
 #include <asm/arch/imx-regs.h>
 
 /* ------------------------------------------------------------------------- */
 /* NOTE: This describes the proper use of this file.
  *
- * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
+ * get_board_sys_clk() should be defined as the input frequency of the PLL.
  * SH FIXME: 16780000 in our case
  * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
  * the specified bus in HZ.
@@ -45,7 +46,7 @@ ulong get_mcuPLLCLK(void)
 
 	mfi = mfi<=5 ? 5 : mfi;
 
-	return (2*(CONFIG_SYS_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
+	return (2*(get_board_sys_clk()>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
 }
 
 ulong get_FCLK(void)
diff --git a/arch/arm/cpu/armv7/ls102xa/clock.c b/arch/arm/cpu/armv7/ls102xa/clock.c
index 984ae8b..c5e6118 100644
--- a/arch/arm/cpu/armv7/ls102xa/clock.c
+++ b/arch/arm/cpu/armv7/ls102xa/clock.c
@@ -39,7 +39,7 @@ void get_sys_info(struct sys_info *sys_info)
 	uint i;
 	uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
 	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
-	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
+	unsigned long sysclk = get_board_sys_clk();
 
 	sys_info->freq_systembus = sysclk;
 #if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c
index bf6cc6d..e63a905 100644
--- a/arch/arm/cpu/armv7/ls102xa/fdt.c
+++ b/arch/arm/cpu/armv7/ls102xa/fdt.c
@@ -131,9 +131,9 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 	sysclk_path = fdt_get_alias(blob, "sysclk");
 	if (sysclk_path)
 		do_fixup_by_path_u32(blob, sysclk_path, "clock-frequency",
-				     CONFIG_SYS_CLK_FREQ, 1);
+				     get_board_sys_clk(), 1);
 	do_fixup_by_compat_u32(blob, "fsl,qoriq-sysclk-2.0",
-			       "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
+			       "clock-frequency", get_board_sys_clk(), 1);
 
 #if defined(CONFIG_DEEP_SLEEP) && defined(CONFIG_SD_BOOT)
 #define UBOOT_HEAD_LEN	0x1000
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 1a359d0..2ded3e4 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <clock_legacy.h>
 #include <cpu_func.h>
 #include <env.h>
 #include <fsl_ddr_sdram.h>
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 4ec0dbf..4354aa2 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -161,7 +161,7 @@ void fsl_fdt_disable_usb(void *blob)
 	 * controller is used, SYSCLK must meet the additional requirement
 	 * of 100 MHz.
 	 */
-	if (CONFIG_SYS_CLK_FREQ != 100000000) {
+	if (get_board_sys_clk() != 100000000) {
 		off = fdt_node_offset_by_compatible(blob, -1, "snps,dwc3");
 		while (off != -FDT_ERR_NOTFOUND) {
 			fdt_status_disabled(blob, off);
@@ -655,7 +655,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 #endif
 
 	do_fixup_by_path_u32(blob, "/sysclk", "clock-frequency",
-			     CONFIG_SYS_CLK_FREQ, 1);
+			     get_board_sys_clk(), 1);
 
 #ifdef CONFIG_GIC_V3_ITS
 	ls_gic_rd_tables_init(blob);
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
index 3f97c8a..570105a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -52,12 +52,12 @@ void get_sys_info(struct sys_info *sys_info)
 	uint i, cluster;
 	uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
 	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
-	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
+	unsigned long sysclk = get_board_sys_clk();
 	unsigned long cluster_clk;
 
 	sys_info->freq_systembus = sysclk;
 #ifndef CONFIG_CLUSTER_CLK_FREQ
-#define CONFIG_CLUSTER_CLK_FREQ	CONFIG_SYS_CLK_FREQ
+#define CONFIG_CLUSTER_CLK_FREQ	get_board_sys_clk()
 #endif
 	cluster_clk = CONFIG_CLUSTER_CLK_FREQ;
 
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
index 6f50cba..1c04a5b 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
@@ -72,7 +72,7 @@ void get_sys_info(struct sys_info *sys_info)
 #endif
 	uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
 	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
-	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
+	unsigned long sysclk = get_board_sys_clk();
 	int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
 	u32 c_pll_sel, cplx_pll;
 	void *offset;
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
index d28ab26..2e2688e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
@@ -4,6 +4,7 @@
  */
 
 #include <common.h>
+#include <clock_legacy.h>
 #include <cpu_func.h>
 #include <image.h>
 #include <log.h>
diff --git a/arch/arm/mach-davinci/cpu.c b/arch/arm/mach-davinci/cpu.c
index 439d2e2..0f68f9f 100644
--- a/arch/arm/mach-davinci/cpu.c
+++ b/arch/arm/mach-davinci/cpu.c
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <clock_legacy.h>
 #include <init.h>
 #include <asm/arch/hardware.h>
 #include <asm/global_data.h>
diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c
index ef48d35..99bca54 100644
--- a/arch/arm/mach-exynos/clock.c
+++ b/arch/arm/mach-exynos/clock.c
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <clock_legacy.h>
 #include <log.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
@@ -136,7 +137,7 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
 	/* SDIV [2:0] */
 	s = r & 0x7;
 
-	freq = CONFIG_SYS_CLK_FREQ;
+	freq = get_board_sys_clk();
 
 	if (pllreg == EPLL || pllreg == RPLL) {
 		k = k & 0xffff;
@@ -1051,7 +1052,7 @@ static unsigned long exynos5800_get_lcd_clk(void)
 									RPLL};
 		sclk = get_pll_clk(reg_map[sel]);
 	} else
-		sclk = CONFIG_SYS_CLK_FREQ;
+		sclk = get_board_sys_clk();
 	/*
 	 * CLK_DIV_DISP10
 	 * FIMD1_RATIO [3:0]
diff --git a/arch/nds32/cpu/n1213/ag101/timer.c b/arch/nds32/cpu/n1213/ag101/timer.c
index 394fc10..f6dcbf1 100644
--- a/arch/nds32/cpu/n1213/ag101/timer.c
+++ b/arch/nds32/cpu/n1213/ag101/timer.c
@@ -9,6 +9,7 @@
  */
 #ifndef CONFIG_TIMER
 #include <common.h>
+#include <clock_legacy.h>
 #include <init.h>
 #include <irq_func.h>
 #include <log.h>
@@ -76,7 +77,7 @@ void reset_timer_masked(void)
 	lastdec = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
 #else
 	lastdec = readl(&tmr->timer3_counter) /
-			(CONFIG_SYS_CLK_FREQ / 2 / CONFIG_SYS_HZ);
+			(get_board_sys_clk() / 2 / CONFIG_SYS_HZ);
 #endif
 	timestamp = 0;		/* start "advancing" time stamp from 0 */
 
@@ -101,7 +102,7 @@ ulong get_timer_masked(void)
 	ulong now = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
 #else
 	ulong now = readl(&tmr->timer3_counter) /
-			(CONFIG_SYS_CLK_FREQ / 2 / CONFIG_SYS_HZ);
+			(get_board_sys_clk() / 2 / CONFIG_SYS_HZ);
 #endif
 
 	debug("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec);
@@ -155,7 +156,7 @@ void __udelay(unsigned long usec)
 #ifdef CONFIG_FTTMR010_EXT_CLK
 	long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
 #else
-	long tmo = usec * ((CONFIG_SYS_CLK_FREQ / 2) / 1000) / 1000;
+	long tmo = usec * ((get_board_sys_clk() / 2) / 1000) / 1000;
 #endif
 	unsigned long now, last = readl(&tmr->timer3_counter);
 
@@ -190,7 +191,7 @@ ulong get_tbclk(void)
 #ifdef CONFIG_FTTMR010_EXT_CLK
 	return CONFIG_SYS_HZ;
 #else
-	return CONFIG_SYS_CLK_FREQ;
+	return get_board_sys_clk();
 #endif
 }
 #endif /* CONFIG_TIMER */
diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c
index c386e4e..d2b6b05 100644
--- a/arch/powerpc/cpu/mpc83xx/pcie.c
+++ b/arch/powerpc/cpu/mpc83xx/pcie.c
@@ -8,6 +8,7 @@
  */
 
 #include <common.h>
+#include <clock_legacy.h>
 #include <pci.h>
 #include <mpc83xx.h>
 #include <asm/global_data.h>
@@ -46,7 +47,7 @@ int get_pcie_clk(int index)
 
 	clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
 	sccr = im->clk.sccr;
-	pci_sync_in = CONFIG_SYS_CLK_FREQ / (1 + clkin_div);
+	pci_sync_in = get_board_sys_clk() / (1 + clkin_div);
 	spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
 	csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
 
diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c
index e5db96b..f835263 100644
--- a/arch/powerpc/cpu/mpc83xx/speed.c
+++ b/arch/powerpc/cpu/mpc83xx/speed.c
@@ -137,8 +137,8 @@ int get_clocks(void)
 	clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
 
 	if (im->reset.rcwh & HRCWH_PCI_HOST) {
-#if defined(CONFIG_SYS_CLK_FREQ)
-		pci_sync_in = CONFIG_SYS_CLK_FREQ / (1 + clkin_div);
+#if CONFIG_SYS_CLK_FREQ != 0
+		pci_sync_in = get_board_sys_clk() / (1 + clkin_div);
 #else
 		pci_sync_in = 0xDEADBEEF;
 #endif
diff --git a/arch/powerpc/cpu/mpc83xx/spl_minimal.c b/arch/powerpc/cpu/mpc83xx/spl_minimal.c
index 00cb2bd..11b1e61 100644
--- a/arch/powerpc/cpu/mpc83xx/spl_minimal.c
+++ b/arch/powerpc/cpu/mpc83xx/spl_minimal.c
@@ -102,5 +102,5 @@ ulong get_bus_freq(ulong dummy)
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	u8 spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
 
-	return CONFIG_SYS_CLK_FREQ * spmf;
+	return get_board_sys_clk() * spmf;
 }
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 3f2fc06..d4b828e 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -662,9 +662,9 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 
 #ifdef CONFIG_FSL_CORENET
 	do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0",
-		"clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
+		"clock-frequency", get_board_sys_clk(), 1);
 	do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-2.0",
-		"clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
+		"clock-frequency", get_board_sys_clk(), 1);
 	do_fixup_by_compat_u32(blob, "fsl,mpic",
 		"clock-frequency", get_bus_freq(0)/2, 1);
 #else
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 1fe914a..5a9cd28 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -75,7 +75,7 @@ void get_sys_info(sys_info_t *sys_info)
 	uint rcw_tmp;
 #endif
 	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
-	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
+	unsigned long sysclk = get_board_sys_clk();
 	uint mem_pll_rat;
 
 	sys_info->freq_systembus = sysclk;
@@ -102,7 +102,7 @@ void get_sys_info(sys_info_t *sys_info)
 	 * are driven by differential sysclock.
 	 */
 	if (ddr_refclk_sel == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK)
-		sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
+		sys_info->freq_ddrbus = get_board_sys_clk();
 	else
 #endif
 #if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
@@ -526,7 +526,7 @@ void get_sys_info(sys_info_t *sys_info)
 
 	plat_ratio = (gur->porpllsr) & 0x0000003e;
 	plat_ratio >>= 1;
-	sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;
+	sys_info->freq_systembus = plat_ratio * get_board_sys_clk();
 
 	/* Divide before multiply to avoid integer
 	 * overflow for processor speeds above 2GHz */
@@ -554,7 +554,7 @@ void get_sys_info(sys_info_t *sys_info)
 #else
 	qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
 			>> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
-	sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ;
+	sys_info->freq_qe = qe_ratio * get_board_sys_clk();
 #endif
 #endif
 
diff --git a/arch/sh/include/asm/config.h b/arch/sh/include/asm/config.h
index 406156d..09a15da 100644
--- a/arch/sh/include/asm/config.h
+++ b/arch/sh/include/asm/config.h
@@ -11,6 +11,6 @@
 /* Timer */
 #define CONFIG_SYS_TIMER_COUNTS_DOWN
 #define CONFIG_SYS_TIMER_COUNTER	(TMU_BASE + 0xc)	/* TCNT0 */
-#define CONFIG_SYS_TIMER_RATE		(CONFIG_SYS_CLK_FREQ / 4)
+#define CONFIG_SYS_TIMER_RATE		(get_board_sys_clk() / 4)
 
 #endif
diff --git a/arch/xtensa/lib/time.c b/arch/xtensa/lib/time.c
index 3a02c38..1c927d2 100644
--- a/arch/xtensa/lib/time.c
+++ b/arch/xtensa/lib/time.c
@@ -4,6 +4,7 @@
  */
 
 #include <common.h>
+#include <clock_legacy.h>
 #include <time.h>
 #include <asm/global_data.h>
 #include <linux/delay.h>
@@ -51,7 +52,7 @@ static void delay_cycles(unsigned cycles)
 void __udelay(unsigned long usec)
 {
 	ulong lo, hi, i;
-	ulong mhz = CONFIG_SYS_CLK_FREQ / 1000000;
+	ulong mhz = get_board_sys_clk() / 1000000;
 
 	/* Scale to support full 32-bit usec range */
 
@@ -74,7 +75,7 @@ ulong get_timer(ulong base)
 #if XCHAL_HAVE_CCOUNT
 	register ulong ccount;
 	__asm__ volatile ("rsr %0, CCOUNT" : "=a"(ccount));
-	return ccount / (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ) - base;
+	return ccount / (get_board_sys_clk() / CONFIG_SYS_HZ) - base;
 #else
 	/*
 	 * Add at least the overhead of this call (in cycles).
@@ -85,7 +86,7 @@ ulong get_timer(ulong base)
 	 */
 
 	fake_ccount += 20;
-	return fake_ccount / (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ) - base;
+	return fake_ccount / (get_board_sys_clk() / CONFIG_SYS_HZ) - base;
 #endif
 }
 
@@ -114,6 +115,6 @@ unsigned long timer_get_us(void)
 	unsigned long ccount;
 
 	__asm__ volatile ("rsr %0, CCOUNT" : "=a"(ccount));
-	return ccount / (CONFIG_SYS_CLK_FREQ / 1000000);
+	return ccount / (get_board_sys_clk() / 1000000);
 }
 #endif