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| author | Sean Anderson <seanga2@gmail.com> | 2021-04-08 22:13:12 -0400 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2021-05-14 16:20:49 +0800 |
| commit | 2111f4e8bf09386c849a6273c3b21b6eb1a3fc3c (patch) | |
| tree | a7d991294006647a1702ba8c62b02987c6405735 /arch | |
| parent | 2d64e3829b19fd5c8337296d6410551e4a753a3a (diff) | |
| download | u-boot-2111f4e8bf09386c849a6273c3b21b6eb1a3fc3c.zip u-boot-2111f4e8bf09386c849a6273c3b21b6eb1a3fc3c.tar.gz u-boot-2111f4e8bf09386c849a6273c3b21b6eb1a3fc3c.tar.bz2 | |
riscv: k210: Use AI as the parent clock of aisram, not PLL1
Testing showed that disabling AI while leaving PLL1 enabled disabled the
aisram. This suggests that AI is a more appropriate clock for that ram
bank.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/riscv/dts/k210.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/dts/k210.dtsi b/arch/riscv/dts/k210.dtsi index 2032f1e..75e1015 100644 --- a/arch/riscv/dts/k210.dtsi +++ b/arch/riscv/dts/k210.dtsi @@ -89,7 +89,7 @@ reg-names = "sram0", "sram1", "aisram"; clocks = <&sysclk K210_CLK_SRAM0>, <&sysclk K210_CLK_SRAM1>, - <&sysclk K210_CLK_PLL1>; + <&sysclk K210_CLK_AI>; clock-names = "sram0", "sram1", "aisram"; u-boot,dm-pre-reloc; }; |