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| author | Trevor Woerner <trevor@toganlabs.com> | 2019-05-03 09:41:00 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-05-18 08:15:35 -0400 |
| commit | 1001502545ff0125c39232cf0e7f26d9213ab55f (patch) | |
| tree | 6513e23c1df21e1a4bc55eb98a73a58f269ccf46 /arch/xtensa | |
| parent | a0aba8a2ebae51287fbee6848aece71655795fdb (diff) | |
| download | u-boot-1001502545ff0125c39232cf0e7f26d9213ab55f.zip u-boot-1001502545ff0125c39232cf0e7f26d9213ab55f.tar.gz u-boot-1001502545ff0125c39232cf0e7f26d9213ab55f.tar.bz2 | |
CONFIG_SPL_SYS_[DI]CACHE_OFF: add
While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances
where these configuration items are conditional on SPL. This commit adds SPL
variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates
the configurations as required.
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Trevor Woerner <trevor@toganlabs.com>
[trini: Make the default depend on the setting for full U-Boot, update
more zynq hardware]
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/xtensa')
| -rw-r--r-- | arch/xtensa/Kconfig | 14 | ||||
| -rw-r--r-- | arch/xtensa/cpu/start.S | 7 |
2 files changed, 18 insertions, 3 deletions
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index c8b72eb..6de31e8 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -22,12 +22,26 @@ config SYS_ICACHE_OFF help Do not enable instruction cache in U-Boot. +config SPL_SYS_ICACHE_OFF + bool "Do not enable icache in SPL" + depends on SPL + default SYS_ICACHE_OFF + help + Do not enable instruction cache in SPL. + config SYS_DCACHE_OFF bool "Do not enable dcache" default n help Do not enable data cache in U-Boot. +config SPL_SYS_DCACHE_OFF + bool "Do not enable dcache in SPL" + depends on SPL + default SYS_DCACHE_OFF + help + Do not enable data cache in SPL. + source "board/cadence/xtfpga/Kconfig" endmenu diff --git a/arch/xtensa/cpu/start.S b/arch/xtensa/cpu/start.S index 0fafb1c..38d2fa2 100644 --- a/arch/xtensa/cpu/start.S +++ b/arch/xtensa/cpu/start.S @@ -164,18 +164,19 @@ _start: * enable data/instruction cache for relocated image. */ #if XCHAL_HAVE_SPANNING_WAY && \ - !(defined(CONFIG_SYS_DCACHE_OFF) && defined(CONFIG_SYS_ICACHE_OFF)) + !(CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && \ + CONFIG_IS_ENABLED(SYS_ICACHE_OFF)) srli a7, a4, 29 slli a7, a7, 29 addi a7, a7, XCHAL_SPANNING_WAY -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) rdtlb1 a8, a7 srli a8, a8, 4 slli a8, a8, 4 addi a8, a8, CA_WRITEBACK wdtlb a8, a7 #endif -#ifndef CONFIG_SYS_ICACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) ritlb1 a8, a7 srli a8, a8, 4 slli a8, a8, 4 |